Finally! SODA across a soda-hub. Reset-problem solved (stuck quad reset on hub downlink)

 trbnet not working at all right now

diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd
index 120aabb88197cc4f1d1c9f1e09732b8791d24008..02eb39e258bb2d404baef009911458f09ed60753 100644 (file)
--- a/code/med_ecp3_sfp_4_sync_down.vhd
+++ b/code/med_ecp3_sfp_4_sync_down.vhd
@@ -15,7 +15,7 @@ entity med_ecp3_sfp_4_sync_down is
        generic(        SERDES_NUM : integer range 0 to 3 := 0;
                                IS_SYNC_SLAVE   : integer := c_NO);   -- hub downlink is NO slave
        port(
-               OSCCLK                                  : in  std_logic; -- 200 MHz reference clock
+               OSC_CLK                                 : in  std_logic; -- 200 MHz reference clock
                TX_DATACLK                              : in  std_logic; -- 200 MHz data clock
                SYSCLK                                  : in  std_logic; -- 100 MHz main clock net, synchronous to OSC clock
                RESET                                           : in  std_logic; -- synchronous reset
@@ -85,7 +85,8 @@ architecture med_ecp3_sfp_4_sync_down_arch of med_ecp3_sfp_4_sync_down is
 
 
 signal clk_200_osc                                             : std_logic;
-signal clk_200_tx_data                                         : std_logic;
+signal clk_200_txdata                                  : std_logic;
+signal clk_200_rxdn                                            : std_logic_vector(3 downto 0);
 signal clk_200_i                                                       : std_logic_vector(3 downto 0);
 signal clk_rx_full                                             : std_logic_vector(3 downto 0);
 signal clk_rx_half                                             : std_logic_vector(3 downto 0); 
@@ -101,7 +102,7 @@ signal rx_error                                                     : t_HUB_BIT;    --std_logic_vector(3 downto 0);
 signal rst_n                                                           : t_HUB_BIT;
 signal rst                                                                     : t_HUB_BIT;            -- PL!
 signal rx_serdes_rst                                           : t_HUB_BIT;
-signal tx_serdes_rst                                           : t_HUB_BIT; 
+signal tx_serdes_rst                                           : std_logic; 
 signal tx_pcs_rst                                                      : t_HUB_BIT; 
 signal rx_pcs_rst                                                      : t_HUB_BIT; 
 signal rst_qd                                                          : t_HUB_BIT; 
@@ -165,8 +166,8 @@ begin
 
 --SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
 
-clk_200_osc                    <= OSCCLK;                      -- This external clock is oscillator/pll generated !!!
-clk_200_tx_data        <= TX_DATACLK;          -- This external clock is the rx_full of the uplink !!!
+clk_200_osc                    <= OSC_CLK;                     -- This external clock is oscillator/pll generated !!!
+clk_200_txdata         <= TX_DATACLK;          -- This external clock is the rx_full of the uplink !!!
 
 
 gen_clocks     : for i in 0 to 3 generate
@@ -176,13 +177,14 @@ gen_clocks        : for i in 0 to 3 generate
 
        CLK_RX_FULL_OUT(i)      <= clk_rx_full(i);
 
-       gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
-               clk_200_i(i)                    <= clk_rx_full(i);
-       end generate;
+--     gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate             -- NO WAY IN HELL !! this downlink is a master
+--             clk_200_i(i)                    <= clk_rx_full(i);
+--     end generate;
 
-       gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
-               clk_200_i(i)    <= clk_200_tx_data;
-       end generate;
+--     gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
+       clk_200_i(i)            <= clk_200_txdata;
+       clk_200_rxdn(i) <= clk_rx_full(i);      -- These clocks are the rx_full of the DOWNLINKs !!!
+--     end generate;
 end generate;
 
 -------------------------------------------------  
@@ -195,9 +197,9 @@ THE_SERDES : entity work.serdes_4_sync_downstream
                hdinn_ch0                               => SD_RXD_N_IN(0),
                hdoutp_ch0                              => SD_TXD_P_OUT(0),
                hdoutn_ch0                              => SD_TXD_N_OUT(0),
-               rxiclk_ch0                              => clk_200_i(0),
+               rxiclk_ch0                              => clk_200_i(0),        --clk_200_txdata,
                sci_sel_ch0                             => sci_ch_i(0),
-               txiclk_ch0                              => clk_200_tx_data,
+               txiclk_ch0                              => clk_200_txdata,
                rx_full_clk_ch0         => clk_rx_full(0),
                rx_half_clk_ch0         => clk_rx_half(0),
                tx_full_clk_ch0         => clk_tx_full(0),
@@ -228,9 +230,9 @@ THE_SERDES : entity work.serdes_4_sync_downstream
                hdinn_ch1                               => SD_RXD_N_IN(1),
                hdoutp_ch1                              => SD_TXD_P_OUT(1),
                hdoutn_ch1                              => SD_TXD_N_OUT(1),
-               rxiclk_ch1                              => clk_200_i(1),
+               rxiclk_ch1                              => clk_200_i(1),        --clk_200_txdata,
                sci_sel_ch1                             => sci_ch_i(1),
-               txiclk_ch1                              => clk_200_tx_data,
+               txiclk_ch1                              => clk_200_txdata,
                rx_full_clk_ch1         => clk_rx_full(1),
                rx_half_clk_ch1         => clk_rx_half(1),
                tx_full_clk_ch1         => clk_tx_full(1),
@@ -261,9 +263,9 @@ THE_SERDES : entity work.serdes_4_sync_downstream
                hdinn_ch2                               => SD_RXD_N_IN(2),
                hdoutp_ch2                              => SD_TXD_P_OUT(2),
                hdoutn_ch2                              => SD_TXD_N_OUT(2),
-               rxiclk_ch2                              => clk_200_i(2),
+               rxiclk_ch2                              => clk_200_i(2),        --clk_200_txdata,
                sci_sel_ch2                             => sci_ch_i(2),
-               txiclk_ch2                              => clk_200_tx_data,
+               txiclk_ch2                              => clk_200_txdata,
                rx_full_clk_ch2         => clk_rx_full(2),
                rx_half_clk_ch2         => clk_rx_half(2),
                tx_full_clk_ch2         => clk_tx_full(2),
@@ -294,9 +296,9 @@ THE_SERDES : entity work.serdes_4_sync_downstream
                hdinn_ch3                               => SD_RXD_N_IN(3),
                hdoutp_ch3                              => SD_TXD_P_OUT(3),
                hdoutn_ch3                              => SD_TXD_N_OUT(3),
-               rxiclk_ch3                              => clk_200_i(3),
+               rxiclk_ch3                              => clk_200_i(3),        --clk_200_txdata,
                sci_sel_ch3                             => sci_ch_i(3),
-               txiclk_ch3                              => clk_200_tx_data,
+               txiclk_ch3                              => clk_200_txdata,
                rx_full_clk_ch3         => clk_rx_full(3),
                rx_half_clk_ch3         => clk_rx_half(3),
                tx_full_clk_ch3         => clk_tx_full(3),
@@ -331,17 +333,18 @@ THE_SERDES : entity work.serdes_4_sync_downstream
                sci_wrn                                 => sci_write_i,
 
                fpga_txrefclk                   => clk_200_osc, --clk_200_i(0),
-               tx_serdes_rst_c         => tx_serdes_rst(0),
+               tx_serdes_rst_c         => '0', --tx_serdes_rst(0),     -- resets tx_pll        PL 1906
                tx_pll_lol_qd_s         => tx_pll_lol_quad,
                tx_sync_qd_c                    => '0',                 -- unused; signal to synchronise channels/serdesses for multi-channel protocols
-               rst_qd_c                                        => rst_down_quad,
+               rst_qd_c                                        => rst_down_quad,                               -- jemig wat is Oscar toch gasfjkl[glk
                serdes_rst_qd_c         => serdes_rst_down_quad
        );
 
 -------------------------
 -- combined quad reset --
 -------------------------
-rst_down_quad                          <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
+--rst_down_quad                                <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
+rst_down_quad                          <= RESET;
 serdes_rst_down_quad           <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
 
 generated_logic        : for i in 0 to 3 generate
@@ -383,7 +386,7 @@ generated_logic     : for i in 0 to 3 generate
        
        PROC_ALLOW : process(clk_200_i(i))
        begin
-               if rising_edge(clk_200_i(i)) then       -- clk_200_tx_data ??
+               if rising_edge(clk_200_i(i)) then       -- clk_200_txdata ??
                        if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
                                rx_allow(i) <= '1';
                                tx_allow(i) <= '1';
@@ -398,7 +401,7 @@ generated_logic     : for i in 0 to 3 generate
        tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
 
 
-       PROC_START_TIMER : process(clk_200_i(i))        --clk_200_tx_data??
+       PROC_START_TIMER : process(clk_200_i(i))        --clk_200_txdata??
        begin
                if rising_edge(clk_200_i(i)) then
                        if got_link_ready_i(i) = '1' then
@@ -427,7 +430,7 @@ generated_logic     : for i in 0 to 3 generate
        -------------------------------------------------         
        THE_TX : soda_tx_control
        port map(
-               CLK_200                                         => clk_200_i(i),        --clk_200_tx_data??
+               CLK_200                                         => clk_200_i(i),        --clk_200_txdata??
                CLK_100                                         => SYSCLK,
                RESET_IN                                                => rst(i),              --CLEAR, PL!
 

diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd
index dabf48feeef860371061a22304e16f9adda3c33e..6f177198015912eca2bdeeab4e9715d485c6e5ce 100644 (file)
--- a/code/med_ecp3_sfp_sync_down.vhd
+++ b/code/med_ecp3_sfp_sync_down.vhd
@@ -186,13 +186,13 @@ SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches
 rst_n                                  <= not(CLEAR or internal_make_link_reset_out);
 rst                                    <=              (CLEAR or internal_make_link_reset_out);
 
-gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
-  clk_200_i        <= clk_rx_full;
-end generate;
+--gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
+-- clk_200_i        <= clk_rx_full;
+--end generate;
 
-gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
+--gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
   clk_200_i        <= clk_200_internal;
-end generate;
+--end generate;
 
 
 -------------------------------------------------      

diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd
index 3f0c78b68660f10425c35ad451edfb67591abd09..bced937bcd685c5937b32e7f63cd7c35895b3486 100644 (file)
--- a/code/med_ecp3_sfp_sync_up.vhd
+++ b/code/med_ecp3_sfp_sync_up.vhd
@@ -16,8 +16,8 @@ entity med_ecp3_sfp_sync_up is
                        --      MASTER_CLOCK_SWITCH     : integer := c_NO;   --just for debugging, should be NO
                                IS_SYNC_SLAVE                   : integer := c_YES);       --select slave mode
        port(
-               CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
-               SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
+               CLK                                             : in  std_logic; -- 200 MHz reference clock
+               SYSCLK                                  : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
                RESET              : in  std_logic; -- synchronous reset
                CLEAR              : in  std_logic; -- asynchronous reset
                --Internal Connection TX
@@ -40,6 +40,7 @@ entity med_ecp3_sfp_sync_up is
                TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
                TX_DLM_PREVIEW_IN               : in std_logic := '0'; --PL!
                LINK_PHASE_OUT                  : out   std_logic := '0';       --PL!
+               LINK_READY_OUT                  : out   std_logic := '0';       --PL!
 
                --SFP Connection
                SD_RXD_P_IN        : in  std_logic;
@@ -202,21 +203,23 @@ CLK_RX_FULL_OUT <= clk_rx_full;
 
 
 --SD_TXDIS_OUT <= not (rx_allow_q or not IS_SYNC_SLAVE);   --slave only switches on when RX is ready
-SD_TXDIS_OUT <= '0';   --not (rx_allow_q);   --slave only switches on when RX is ready
+SD_TXDIS_OUT           <= '0'; --not (rx_allow_q);   --slave only switches on when RX is ready
 
+LINK_READY_OUT         <= got_link_ready_i;
+\r
 
 --rst_n <= not CLEAR;  PL!
 rst_n                                  <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
 rst                                    <=              (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
 
 
-gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
+--gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
   clk_200_i        <= clk_rx_full;
-end generate;
+--end generate;
 
-gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
-  clk_200_i        <= clk_200_internal;
-end generate;
+--gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
+-- clk_200_i        <= clk_200_internal;
+--end generate;
 
 
 -------------------------------------------------      
@@ -291,7 +294,7 @@ THE_RX_FSM : rx_reset_fsm
 THE_TX_FSM : tx_reset_fsm
   port map(
     RST_N           => rst_n,
-    TX_REFCLK       => clk_200_i,      --nternal,                      -- allways running PL!
+    TX_REFCLK       => clk_200_internal,                       -- allways running PL! 18-06 was clk_200_i
     TX_PLL_LOL_QD_S => tx_pll_lol,
     RST_QD_C        => rst_qd,
     TX_PCS_RST_CH_C => tx_pcs_rst,

diff --git a/code/soda_components.vhd b/code/soda_components.vhd
index 4fc1ea45a195f94ee473dd12d0dea6a335c5566e..a987eee24c22ce3978be84ccde9d257bbac105e9 100644 (file)
--- a/code/soda_components.vhd
+++ b/code/soda_components.vhd
@@ -366,7 +366,7 @@ component med_ecp3_sfp_4_sync_down is
        generic(        SERDES_NUM : integer range 0 to 3 := 0;
                                IS_SYNC_SLAVE   : integer := c_NO);       --select slave mode
        port(
-               OSCCLK                                  : in  std_logic; -- 200 MHz reference clock
+               OSC_CLK                                 : in  std_logic; -- 200 MHz reference clock
                TX_DATACLK                              : in  std_logic; -- 200 MHz data clock
                SYSCLK                                  : in  std_logic; -- 100 MHz main clock net, synchronous to OSC clock
                RESET                                           : in  std_logic; -- synchronous reset
@@ -430,7 +430,7 @@ component med_ecp3_sfp_sync_up is
                                IS_SYNC_SLAVE   : integer := c_YES --select slave mode
                );
        port(
-               CLK                                             : in std_logic; -- _internal_ 200 MHz reference clock
+               CLK                                             : in  std_logic; -- 200 MHz reference clock
                SYSCLK                                  : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
                RESET                                           : in std_logic; -- synchronous reset
                CLEAR                                           : in std_logic; -- asynchronous reset
@@ -454,6 +454,7 @@ component med_ecp3_sfp_sync_up is
                TX_DLM_WORD                             : in std_logic_vector(7 downto 0) := x"00";
                TX_DLM_PREVIEW_IN               : in std_logic := '0'; --PL!
                LINK_PHASE_OUT                  : out   std_logic := '0';       --PL!
+               LINK_READY_OUT                  : out   std_logic := '0';       --PL!
 
                --SFP Connection
                SD_RXD_P_IN                             : in std_logic;

diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd
index a8ae65548271d62342a0cf7fd96ae66209d6520d..ae6114231481c19bcb193471b5fb54dd31d8f2bf 100644 (file)
--- a/code/trb3_periph_sodahub.vhd
+++ b/code/trb3_periph_sodahub.vhd
@@ -88,6 +88,8 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is
        signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
        signal clear_i                  : std_logic;
        signal reset_i                  : std_logic;
+       signal downlink_clear                           : std_logic;
+       signal downlink_reset                           : std_logic;
        signal GSR_N                    : std_logic;
        attribute syn_keep of GSR_N     : signal is true;
        attribute syn_preserve of GSR_N : signal is true;
@@ -185,6 +187,7 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is
        signal rxup_dlm_word                                    : std_logic_vector(7 downto 0);
        signal txup_dlm_preview_S                       : std_logic;    --PL!
        signal uplink_phase_S                           : std_logic;    --PL!
+       signal uplink_ready_S                           : std_logic;    --PL!
        signal sfp_txdis_S                      : std_logic_vector(6 downto 1)  := (others => '1'); 
 
        --SODA downlink
@@ -292,7 +295,7 @@ begin
 ---------------------------------------------------------------------------
 -- Clock Handling
 ---------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
+--gen_200_PLL : if USE_125_MHZ = c_NO generate
   THE_MAIN_PLL : pll_in200_out100
     port map(
       CLK   => CLK_GPLL_RIGHT,
@@ -300,20 +303,20 @@ gen_200_PLL : if USE_125_MHZ = c_NO generate
       CLKOK => clk_raw_internal,
       LOCK  => pll_lock
       );
-end generate;      
+--end generate;      
 
-gen_125 : if USE_125_MHZ = c_YES generate
-  clk_sys_internal <= CLK_GPLL_LEFT;
-  clk_raw_internal <= CLK_GPLL_LEFT;
-end generate; 
+--gen_125 : if USE_125_MHZ = c_YES generate
+--  clk_sys_internal <= CLK_GPLL_LEFT;
+--  clk_raw_internal <= CLK_GPLL_LEFT;
+--end generate; 
 
-gen_sync_clocks : if SYNC_MODE = c_YES generate
+--gen_sync_clocks : if SYNC_MODE = c_YES generate
        clk_soda_i      <= soda_rxup_clock_full;
-end generate;
+--end generate;
 
-gen_local_clocks : if SYNC_MODE = c_NO generate
-       clk_soda_i      <= clk_raw_internal;
-end generate;
+--gen_local_clocks : if SYNC_MODE = c_NO generate
+--     clk_soda_i      <= clk_raw_internal;
+--end generate;
 
 
 ---------------------------------------------------------------------------
@@ -463,6 +466,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
                TX_DLM_WORD                             => txup_dlm_word,
                TX_DLM_PREVIEW_IN               => txup_dlm_preview_S,                  --PL!
                LINK_PHASE_OUT                  =>      uplink_phase_S,         --PL!
+               LINK_READY_OUT                  =>      uplink_ready_S,         --PL!
                --SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting
                SD_RXD_P_IN                             => SERDES_ADDON_RX(4),
                SD_RXD_N_IN                             => SERDES_ADDON_RX(5),
@@ -529,7 +533,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
                );
 
 
-       
+               downlink_reset  <=      '1'     when (reset_i = '1' or uplink_ready_S = '0') else '0';
+               downlink_clear  <=      '1'     when (clear_i = '1' or uplink_ready_S = '0') else '0';
 
                
                THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down
@@ -538,11 +543,11 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
                                IS_SYNC_SLAVE           => c_NO
                                )
                        port map(
-                               OSCCLK                                                                                  => clk_raw_internal,
+                               OSC_CLK                                                                                 => clk_raw_internal,
                                TX_DATACLK                                                                              => clk_soda_i,  --clk_raw_internal, --clk_200_i,
                                SYSCLK                                                                                  => clk_sys_internal,    --clk_sys_i,
-                               RESET                                                                                           => reset_i,
-                               CLEAR                                                                                           => clear_i,
+                               RESET                                                                                           => downlink_reset,
+                               CLEAR                                                                                           => downlink_clear,
                                ---------------------------------------------------------------------------------------------------------------------------------------------------------
                                LINK_DISABLE_IN                                                         => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
                                ---------------------------------------------------------------------------------------------------------------------------------------------------------

diff --git a/code/trb3_periph_sodasource.vhd b/code/trb3_periph_sodasource.vhd
index 6499977103764ff0c69675aae7068a7603d425d2..6691f8486c6f704e39e439f23cb23e7ce1c81cc6 100644 (file)
--- a/code/trb3_periph_sodasource.vhd
+++ b/code/trb3_periph_sodasource.vhd
@@ -308,7 +308,7 @@ end generate;
 
 --gen_local_clocks : if SYNC_MODE = c_NO generate
 --  clk_sys_i <= clk_sys_internal;
---  clk_200_i <= clk_raw_internal;
+--  clk_200_ip <= clk_raw_internal;
 --end generate;
 
 

diff --git a/soda_client.ldf b/soda_client.ldf
index ab0653e6bb690e41ee4fddad0bd9ca499c4c166c..5b1056612828250a21c7c9f8e831cc1b25ce5603 100644 (file)
--- a/soda_client.ldf
+++ b/soda_client.ldf
@@ -4,7 +4,7 @@
         <Option name="HDL type" value="VHDL"/>
     </Options>
     <Implementation title="soda_client" dir="soda_client" description="soda_client" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
+        <Options def_top="spi_flash_and_fpga_reload" top="trb3_periph_sodaclient"/>
         <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>

diff --git a/soda_client.lpf b/soda_client.lpf
index e7b5264e8ab3cc2cdd7d0684b92d31cf226485c4..1c0a4fbb991732080b95424c1723f35b22dd1e93 100644 (file)
--- a/soda_client.lpf
+++ b/soda_client.lpf
@@ -1,3 +1,4 @@
+rvl_alias "clk_soda_i" "clk_soda_i";
 RVL_ALIAS "clk_soda_i" "clk_soda_i"; 
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;

diff --git a/soda_client_probe.rvl b/soda_client_probe.rvl
index fb81dcb9e942d08ee5ea2f560d02d74a040aeb63..21c9def568eef8cbe4ded5ae6e15eb3baaec1fb5 100644 (file)
--- a/soda_client_probe.rvl
+++ b/soda_client_probe.rvl
@@ -1,10 +1,10 @@
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-05-06">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-05-27">
     <IP Version="1_5_062609"/>
     <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_client"/>
-    <Core InsertDataset="0" Insert="1" Reveal_sig="2035069901" Name="trb3_periph_sodaclient_LA0" ID="0">
+    <Core InsertDataset="0" Insert="1" Reveal_sig="2037822697" Name="trb3_periph_sodaclient_LA0" ID="0">
         <Setting>
             <Clock SampleClk="clk_soda_i" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
-            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="1024"/>
+            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
             <Capture Mode="0" MinSamplesPerTrig="8"/>
             <Event CntEnable="0" MaxEventCnt="8"/>
             <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_client_LA0_net"/>
@@ -117,11 +117,10 @@
             </Trace>
             <Trigger>
                 <TU Serialbits="0" Type="0" ID="1" Sig="the_sync_link/watchdog_trigger,"/>
-                <TU Serialbits="0" Type="0" ID="2" Sig="the_sync_link/rx_error,"/>
+                <TU Serialbits="0" Type="0" ID="2" Sig="a_soda_client/start_of_superburst_s,"/>
                 <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/rx_cdr_lol,"/>
                 <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_link/rx_los_low,"/>
                 <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_sync_link/rx_fsm_state[3:0],"/>
-                <TU Serialbits="0" Type="0" ID="6" Sig="the_sync_link/tx_pll_lol,"/>
                 <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>

diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl
index eb571cc72fdb7dcb5347c557b96b56bebcf8af34..dd7e9b5c544c4eb7fbfe887eef7f99ca9580a2a5 100644 (file)
--- a/soda_hub_probe.rvl
+++ b/soda_hub_probe.rvl
@@ -1,9 +1,9 @@
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-05-22">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-06-19">
     <IP Version="1_5_062609"/>
     <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
-    <Core InsertDataset="0" Insert="1" Reveal_sig="2037156685" Name="trb3_periph_sodahub_LA0" ID="0">
+    <Core InsertDataset="0" Insert="1" Reveal_sig="2040983148" Name="trb3_periph_sodahub_LA0" ID="0">
         <Setting>
-            <Clock SampleClk="the_hub_sync_downlink/oscclk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+            <Clock SampleClk="the_hub_sync_downlink/clk_200_txdata" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
             <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
             <Capture Mode="0" MinSamplesPerTrig="8"/>
             <Event CntEnable="0" MaxEventCnt="8"/>
@@ -11,7 +11,10 @@
         </Setting>
         <Dataset Name="Base">
             <Trace>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
+                <Sig Type="SIG" Name="the_hub_sync_uplink/watchdog_trigger"/>
+                <Sig Type="SIG" Name="the_hub_sync_uplink/got_link_ready_i"/>
+                <Sig Type="SIG" Name="the_hub_sync_uplink/link_phase_out"/>
+                <Sig Type="SIG" Name="the_hub_sync_uplink/rst"/>
                 <Bus Name="the_hub_sync_uplink/rx_data">
                     <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:0"/>
                     <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:1"/>
@@ -22,62 +25,229 @@
                     <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:6"/>
                     <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:7"/>
                 </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/got_link_ready"/>
-                <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_k_in"/>
-                <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_k_in"/>
+                <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm"/>
+                <Bus Name="the_hub_sync_uplink/rx_dlm_word">
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:3"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:4"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:5"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:6"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:7"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
+                <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_preview_in"/>
+                <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm"/>
+                <Bus Name="the_hub_sync_uplink/tx_data">
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:3"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:4"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:5"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:6"/>
+                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:7"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_uplink/tx_k"/>
+                <Bus Name="the_hub_sync_downlink/got_link_ready_i">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:3"/>
+                </Bus>
+                <Bus Name="the_hub_sync_downlink/link_phase_out">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/link_phase_out:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/link_phase_out:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/link_phase_out:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/link_phase_out:3"/>
+                </Bus>
+                <Bus Name="the_hub_sync_downlink/lsm_status">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/lsm_status:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/lsm_status:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/lsm_status:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/lsm_status:3"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/rst_n:0"/>
+                <Bus Name="rx_data0">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:3"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:4"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:5"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:6"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:7"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:0"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:0"/>
+                <Bus Name="rx_dlm_word0">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:3"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:4"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:5"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:6"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:7"/>
+                </Bus>
+                <Bus Name="rx_fsm_state0">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_fsm_state:0:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_fsm_state:0:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_fsm_state:0:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_fsm_state:0:3"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow_q:0"/>
+                <Bus Name="tx_data0">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:3"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:4"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:5"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:6"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:7"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:0"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:0"/>
+                <Bus Name="tx_fsm_state0">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_fsm_state:0:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_fsm_state:0:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_fsm_state:0:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_fsm_state:0:3"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:0"/>
+                <Bus Name="the_hub_sync_downlink/sd_txdis_out">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:3"/>
+                </Bus>
+                <Bus Name="sfp_txdis">
+                    <Sig Type="SIG" Name="sfp_txdis:1"/>
+                    <Sig Type="SIG" Name="sfp_txdis:2"/>
+                    <Sig Type="SIG" Name="sfp_txdis:3"/>
+                    <Sig Type="SIG" Name="sfp_txdis:4"/>
+                    <Sig Type="SIG" Name="sfp_txdis:5"/>
+                    <Sig Type="SIG" Name="sfp_txdis:6"/>
+                </Bus>
+                <Bus Name="sfp_los">
+                    <Sig Type="SIG" Name="sfp_los:1"/>
+                    <Sig Type="SIG" Name="sfp_los:2"/>
+                    <Sig Type="SIG" Name="sfp_los:3"/>
+                    <Sig Type="SIG" Name="sfp_los:4"/>
+                    <Sig Type="SIG" Name="sfp_los:5"/>
+                    <Sig Type="SIG" Name="sfp_los:6"/>
+                </Bus>
+                <Bus Name="sfp_mod0">
+                    <Sig Type="SIG" Name="sfp_mod0:1"/>
+                    <Sig Type="SIG" Name="sfp_mod0:2"/>
+                    <Sig Type="SIG" Name="sfp_mod0:3"/>
+                    <Sig Type="SIG" Name="sfp_mod0:4"/>
+                    <Sig Type="SIG" Name="sfp_mod0:5"/>
+                    <Sig Type="SIG" Name="sfp_mod0:6"/>
+                </Bus>
                 <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/cs">
                     <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/cs:0"/>
                     <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/cs:1"/>
                     <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/cs:2"/>
                 </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/rx_cdr_lol_ch_s"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/rx_lol_los"/>
                 <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/rx_los_low_ch_s"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/rx_pcs_rst_ch_c"/>
                 <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/tx_pll_lol_qd_s"/>
-                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/rx_allow_qtx"/>
-                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_allow_qtx"/>
-                <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_k_out"/>
+                <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/wa_position">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/wa_position:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/wa_position:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/wa_position:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/wa_position:3"/>
+                </Bus>
+                <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/state_out">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/state_out:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/state_out:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/state_out:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/state_out:3"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/the_serdes/rst_qd_c"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/the_serdes/lsm_status_ch0_s"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/the_serdes/rx_cdr_lol_ch0_s"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/the_serdes/rx_cv_err_ch0"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/the_serdes/rx_half_clk_ch0"/>
+                <Sig Type="SIG" Name="uplink_ready_s"/>
+                <Sig Type="SIG" Name="downlink_clear"/>
+                <Sig Type="SIG" Name="downlink_reset"/>
+                <Sig Type="SIG" Name="dnlink_phase_s:0"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/rst_down_quad"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:1"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:2"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:3"/>
+                <Bus Name="the_hub_sync_downlink/rx_pcs_rst">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_pcs_rst:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_pcs_rst:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_pcs_rst:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_pcs_rst:3"/>
+                </Bus>
+                <Bus Name="the_hub_sync_downlink/rx_serdes_rst">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_serdes_rst:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_serdes_rst:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_serdes_rst:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_serdes_rst:3"/>
+                </Bus>
+                <Bus Name="the_hub_sync_downlink/serdes_rst_qd">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/serdes_rst_qd:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/serdes_rst_qd:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/serdes_rst_qd:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/serdes_rst_qd:3"/>
+                </Bus>
+                <Bus Name="the_hub_sync_downlink/rst_qd">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rst_qd:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rst_qd:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rst_qd:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rst_qd:3"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/serdes_rst_down_quad"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/tx_pll_lol_qd_s"/>
                 <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/cs">
                     <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/cs:0"/>
                     <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/cs:1"/>
                     <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/cs:2"/>
                 </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_downlink/lsm_status:0"/>
-                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/rst_n"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/tx_pcs_rst_ch_c"/>
+                <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/state_out">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/state_out:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/state_out:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/state_out:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/state_out:3"/>
+                </Bus>
+                <Bus Name="the_hub_sync_downlink/rst">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rst:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rst:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rst:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/rst:3"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/clear"/>
+                <Bus Name="the_hub_sync_downlink/sd_los_i">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_i:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_i:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_i:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_i:3"/>
+                </Bus>
+                <Bus Name="the_hub_sync_downlink/internal_make_link_reset_out">
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/internal_make_link_reset_out:0"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/internal_make_link_reset_out:1"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/internal_make_link_reset_out:2"/>
+                    <Sig Type="SIG" Name="the_hub_sync_downlink/internal_make_link_reset_out:3"/>
+                </Bus>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:1"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:2"/>
+                <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:3"/>
             </Trace>
             <Trigger>
                 <TU Serialbits="0" Type="0" ID="1" Sig="(BUS)the_hub_sync_uplink/rx_fsm_state[3:0],"/>
                 <TU Serialbits="0" Type="0" ID="2" Sig="the_hub_sync_uplink/watchdog_trigger,"/>
-                <TU Serialbits="0" Type="0" ID="3" Sig="a_soda_hub/start_of_superburst_s,"/>
-                <TU Serialbits="0" Type="0" ID="4" Sig="the_hub_sync_uplink/got_link_ready_i,"/>
+                <TU Serialbits="0" Type="0" ID="3" Sig="the_hub_sync_uplink/got_link_ready_i,"/>
+                <TU Serialbits="0" Type="0" ID="4" Sig="a_soda_hub/start_of_superburst_s,"/>
                 <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>

diff --git a/soda_source.lpf b/soda_source.lpf
index b2ee04ef841adad33d624591d8b227e13b92dece..771f0718d5dce1addf70f88c06893256c9f105c8 100644 (file)
--- a/soda_source.lpf
+++ b/soda_source.lpf
@@ -1,3 +1,4 @@
+rvl_alias "clk_raw_internal" "clk_raw_internal";
 RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
 RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
 BLOCK RESETPATHS ;

diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl
index 87566d149220210c9ae396025b4036e6e88eba17..843cf242dbf6037c20000c89ebed0daf45ce3b6b 100644 (file)
--- a/soda_source_probe.rvl
+++ b/soda_source_probe.rvl
@@ -1,7 +1,7 @@
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-05-22">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-05-26">
     <IP Version="1_5_062609"/>
     <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_source"/>
-    <Core InsertDataset="0" Insert="1" Reveal_sig="2037164429" Name="trb3_periph_sodasource_LA0" ID="0">
+    <Core InsertDataset="0" Insert="1" Reveal_sig="2037718156" Name="trb3_periph_sodasource_LA0" ID="0">
         <Setting>
             <Clock SampleClk="clk_raw_internal" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
             <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
@@ -11,6 +11,57 @@
         </Setting>
         <Dataset Name="Base">
             <Trace>
+                <Bus Name="the_sob_source/burst_counter_s">
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:0"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:1"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:2"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:3"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:4"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:5"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:6"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:7"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:8"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:9"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:10"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:11"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:12"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:13"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:14"/>
+                    <Sig Type="SIG" Name="the_sob_source/burst_counter_s:15"/>
+                </Bus>
+                <Bus Name="the_soda_source/super_burst_nr_s">
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:0"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:1"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:2"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:3"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:4"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:5"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:6"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:7"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:8"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:9"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:10"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:11"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:12"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:13"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:14"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:15"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:16"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:17"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:18"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:19"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:20"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:21"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:22"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:23"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:24"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:25"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:26"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:27"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:28"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:29"/>
+                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:30"/>
+                </Bus>
                 <Bus Name="the_sync_link/start_timer">
                     <Sig Type="SIG" Name="the_sync_link/start_timer:0"/>
                     <Sig Type="SIG" Name="the_sync_link/start_timer:1"/>
@@ -205,11 +256,13 @@
                 <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/rx_error,"/>
                 <TU Serialbits="0" Type="0" ID="4" Sig="the_soda_source/start_of_superburst_s,"/>
                 <TU Serialbits="0" Type="0" ID="5" Sig="the_soda_source/start_calibration_s,"/>
+                <TU Serialbits="0" Type="0" ID="6" Sig="the_sob_source/soda_burst_pulse_out,"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
             </Trigger>
         </Dataset>
     </Core>

diff --git a/trb3_soda_client.xcf b/trb3_soda_client.xcf
index ee24f3bd1111b980948ba9e87c8e31c217dada68..2f7c8a60376960b14e81aceffce1dca5143d1099 100644 (file)
--- a/trb3_soda_client.xcf
+++ b/trb3_soda_client.xcf
@@ -47,8 +47,8 @@
                                <BScanLen>1</BScanLen>
                                <BScanVal>0</BScanVal>
                        </Bypass>
-                       <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140522.bit</File>
-                       <FileTime>05/22/14 13:40:45</FileTime>
+                       <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140527.bit</File>
+                       <FileTime>05/27/14 11:25:29</FileTime>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>
@@ -139,8 +139,8 @@
                                <BScanLen>1</BScanLen>
                                <BScanVal>0</BScanVal>
                        </Bypass>
-                       <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140522.bit</File>
-                       <FileTime>05/22/14 10:56:23</FileTime>
+                       <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140526.bit</File>
+                       <FileTime>05/26/14 17:56:32</FileTime>
                        <JedecChecksum>N/A</JedecChecksum>
                        <Operation>Fast Program</Operation>
                        <Option>

diff --git a/trb3_soda_dual_client.xcf b/trb3_soda_dual_client.xcf
index afd3530497f9e9f0404ea02137f89a27ea55005b..19c245f7d4384fcc60126eaa72263c604c16bc2f 100644 (file)
--- a/trb3_soda_dual_client.xcf
+++ b/trb3_soda_dual_client.xcf
@@ -46,8 +46,9 @@
                                <BScanLen>1</BScanLen>
                                <BScanVal>0</BScanVal>
                        </Bypass>
-                       <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140513.bit</File>
-                       <FileTime>05/13/14 09:58:14</FileTime>
+                       <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140617.bit</File>
+                       <FileTime>06/17/14 15:26:56</FileTime>
+                       <JedecChecksum>N/A</JedecChecksum>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>
@@ -130,7 +131,6 @@
                        </Bypass>
                        <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140513.bit</File>
                        <FileTime>05/13/14 09:58:14</FileTime>
-                       <JedecChecksum>N/A</JedecChecksum>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>

diff --git a/trb3_soda_hub.xcf b/trb3_soda_hub.xcf
index 59bc73becbe0d1f33d7298991a7ffc2b5d51f715..517eed19bdb854c23d7009ec835385239d972650 100644 (file)
--- a/trb3_soda_hub.xcf
+++ b/trb3_soda_hub.xcf
@@ -45,8 +45,8 @@
                                <BScanLen>1</BScanLen>
                                <BScanVal>0</BScanVal>
                        </Bypass>
-                       <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140522.bit</File>
-                       <FileTime>05/22/14 14:50:45</FileTime>
+                       <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140619.bit</File>
+                       <FileTime>06/19/14 08:27:43</FileTime>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>
@@ -127,8 +127,8 @@
                                <BScanLen>1</BScanLen>
                                <BScanVal>0</BScanVal>
                        </Bypass>
-                       <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140522.bit</File>
-                       <FileTime>05/22/14 14:25:11</FileTime>
+                       <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140617.bit</File>
+                       <FileTime>06/17/14 15:29:03</FileTime>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>

diff --git a/trb3_soda_source.xcf b/trb3_soda_source.xcf
index 67959c07a5c0f14da6c31e4804c6e56ba3a2bb9c..0fbd435ea669de8acb0e437fea3285ec97846a62 100644 (file)
--- a/trb3_soda_source.xcf
+++ b/trb3_soda_source.xcf
@@ -47,8 +47,8 @@
                                <BScanLen>1</BScanLen>
                                <BScanVal>0</BScanVal>
                        </Bypass>
-                       <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140430.bit</File>
-                       <FileTime>04/30/14 15:40:52</FileTime>
+                       <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140617.bit</File>
+                       <FileTime>06/17/14 15:26:56</FileTime>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>
@@ -139,9 +139,8 @@
                                <BScanLen>1</BScanLen>
                                <BScanVal>0</BScanVal>
                        </Bypass>
-                       <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140514.bit</File>
-                       <FileTime>05/14/14 10:02:39</FileTime>
-                       <JedecChecksum>N/A</JedecChecksum>
+                       <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140617.bit</File>
+                       <FileTime>06/17/14 15:29:03</FileTime>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>