Startup fix for Online Calibration

diff --git a/combiner_calib/code_EBR/Cal_Limits_v2.vhd b/combiner_calib/code_EBR/Cal_Limits_v2.vhd
index 81d52994bd01962140b5c3f62354cd91c5d3cd30..8cffb61df79453a8d267caafbf7f29ec149f55d8 100644 (file)
--- a/combiner_calib/code_EBR/Cal_Limits_v2.vhd
+++ b/combiner_calib/code_EBR/Cal_Limits_v2.vhd
@@ -32,14 +32,14 @@ entity Cal_Limits_v2 is
     BUS_Flash_value    : in  std_logic_vector(27 downto 0);
     Flash_flag         : in  std_logic;
     DIN_info           : in  std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
-    write_curr         : out std_logic;
+    write_curr_out     : out std_logic;
     write_next         : out std_logic;
     min_next           : out std_logic_vector( 9 downto 0);
     max_next           : out std_logic_vector( 9 downto 0);
-    min_curr           : out std_logic_vector( 9 downto 0);
-    max_curr           : out std_logic_vector( 9 downto 0);
-    min_out            : out std_logic_vector( 9 downto 0);
-    max_out            : out std_logic_vector( 9 downto 0);
+    min_curr_out       : out std_logic_vector( 9 downto 0);
+    max_curr_out       : out std_logic_vector( 9 downto 0);
+    min_out_out        : out std_logic_vector( 9 downto 0);
+    max_out_out        : out std_logic_vector( 9 downto 0);
     Delta              : out std_logic_vector( 9 downto 0);
     FPGA_out           : out std_logic_vector( 3 downto 0);
     chnl_out           : out std_logic_vector( 6 downto 0);
@@ -58,7 +58,9 @@ entity Cal_Limits_v2 is
     cal_Limit_set      : out unsigned (19 downto 0);
     Debug_Data_min     : out std_logic_vector(31 downto 0);
     Debug_Data_max     : out std_logic_vector(31 downto 0);
-    DOUT_info          : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0)
+    DOUT_info          : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+    dflt_out           : out std_logic_vector(3 downto 0);
+    cnt_i_debug        : out unsigned (19 downto 0)
   );
 end Cal_Limits_v2;
 
@@ -68,11 +70,8 @@ architecture Behavioral of Cal_Limits_v2 is
   signal cnt_i       : unsigned(19 downto 0):="00000000000000000000";
   signal cal_Limit   : unsigned(19 downto 0):="00011000011010100000";--"00011000011010100000";
 
-  type array2D is array (1 downto 0, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
-  signal def_value   : array2D := (others => ("10000000010000000010","10000000100000000010","10000000110000000010","10000001000000000010",
-                                              "10000001010000000010","10000001100000000010","10000001110000000010","10000010000000000010",
-                                              "10000010010000000010","10000010100000000010","10000010110000000010","10000011000000000010",
-                                              "10000011010000000010","10000011100000000010", others => "11111000010000001111" ));
+  type array2D is array (0 to 15, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
+  signal def_value   : array2D := (others => (others => "10000000000000010011"));
   
   type bit_2D is array (16 downto 0, 63 downto 0) of std_logic; --(channel)
   signal dflt_i      : bit_2D := (others => (others => '1'));
@@ -95,6 +94,15 @@ architecture Behavioral of Cal_Limits_v2 is
   signal stop_Limits_r : std_logic;
   signal DIN_info_r    : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
   
+  signal max_default,min_default : std_logic_vector( 9 downto 0);
+  signal write_default : std_logic;
+  signal min_out       : std_logic_vector( 9 downto 0);
+  signal max_out       : std_logic_vector( 9 downto 0);
+  signal min_curr      : std_logic_vector( 9 downto 0);
+  signal max_curr      : std_logic_vector( 9 downto 0);
+  signal write_curr    : std_logic;
+  signal first_reset    : std_logic := '1';
+  
 begin
 
   Limit : process (CLK)
@@ -116,6 +124,11 @@ begin
   if rising_edge(CLK) then
     if (RESET = '1') then
        --Reset behaviour
+       if first_reset = '1' then
+         dflt_i      <= (others => (others => '1'));
+         first_reset <= '0';
+       end if; 
+
     else
       cnt_v := chnl_cnt_in;
 
@@ -161,7 +174,7 @@ begin
     Do_Cal_in_r       <= Do_Cal_in;
     stop_Limits_r     <= stop_Limits;
     DIN_info_r        <= DIN_info;
-      
+    cnt_i_debug       <= cnt_i; 
   end if;
   end process;
    
@@ -225,8 +238,8 @@ begin
             write_curr <= '0';
             EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & EBRCurr_Max_v & EBRCurr_Min_v;
           else 
-            min_out      <= EBRNext_Min_v;
-            max_out      <= EBRNext_Max_v;
+            min_out     <= EBRNext_Min_v;
+            max_out     <= EBRNext_Max_v;
             min_curr    <= EBRNext_Min_v;
             max_curr    <= EBRNext_Max_v;
             if (unsigned(EBRNext_Min_v) < unsigned(EBRNext_Max_v)) then
@@ -240,29 +253,25 @@ begin
         else -- no calibr
           write_curr  <= '0';
           write_next  <= '0';
-          --min_out      <= "1111111111";
-          --max_out      <= "0000000000";
-          --min_curr    <= "1111111111";
-          --max_curr    <= "0000000000";
           EBRbufNext(locBufDepth-1) <= x"00000000";
           EBRbufCurr(locBufDepth-1) <= x"00000000";
         end if;
       elsif dflt_i(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r))) = '1' then
       --FLASH
-        if Do_Cal_in_r = '1' then 
+        if Do_Cal_in_r = '1' then
           write_curr <= '1';
-          min_out    <= def_value(0,to_integer(unsigned(chnl_r)))( 9 downto  0);
-          max_out    <= def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10);
-          min_curr   <= def_value(0,to_integer(unsigned(chnl_r)))( 9 downto  0);
-          max_curr   <= def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10);
-          Delta_i    <= std_logic_vector(unsigned(def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10)) - unsigned(def_value(0,to_integer(unsigned(chnl_r)))(9 downto 0)));
-          EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10) & def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0);
+          min_out    <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))( 9 downto  0);
+          max_out    <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10);
+          min_curr   <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))( 9 downto  0);
+          max_curr   <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10);
+          Delta_i    <= std_logic_vector(unsigned(def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10)) - unsigned(def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(9 downto 0)));
+          EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10) & def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))( 9 downto 0);
         else
           write_curr <= '0';
           --min_out    <= b"0000000000";
           --max_out    <= b"0000000000";
-          min_curr   <= b"0000000000";
-          max_curr   <= b"0000000000";
+          --min_curr   <= b"0000000000";  --commented at 2019-04-09; may work still, bur without 0 at beginning in Monitoring
+          --max_curr   <= b"0000000000";  --commented at 2019-04-09; may work still, bur without 0 at beginning in Monitoring
           Delta_i    <= b"0000000000";
           EBRbufCurr(locBufDepth-1) <= x"00000000";
         end if;
@@ -274,6 +283,7 @@ begin
         max_curr   <= "1000000000";
         Delta_i    <= "0111111011";--"0111111110";
         if Do_Cal_in_r = '1' then
+          write_curr <= '1';
           EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & "1000000000" & "0000000100";
         else
           EBRbufCurr(locBufDepth-1) <= x"00000000";
@@ -320,17 +330,41 @@ begin
   proc_Flash_input : process (CLK)
   begin
   if rising_edge(CLK) then
-    --if RESET = '1' then
+    write_default <= '0';
+    if RESET = '1' then
       --RESET
-   --elsif (stop_Limits_r = '0') then 
+    else 
+    --IDEA:
+         -- Send Flash value of FOGA|channel to thsi location. If Flash_flag = 1 the value is written to RAM.
+         -- write_out is OR of this write and write from current. By default wrrite from here is 0.
       if Flash_flag = '1' then
-        def_value(0,to_integer(unsigned(BUS_Flash_value(27 downto 20))))( 19 downto  0) <= BUS_Flash_value(19 downto 0);
+        --def_value(0,to_integer(unsigned(BUS_Flash_value(27 downto 20))))( 19 downto  0) <= BUS_Flash_value(19 downto 0);
+        write_default <= '0';--'1';
+        --min_default <= "0000010011";--BUS_Flash_value( 9 downto  0);
+        --max_default <= "0111111110";--BUS_Flash_value(19 downto 10);
+        --fpga_default <= 
       end if;
-    --end if;  
+    end if;  
   end if;
   end process;
  
  
+--  write_curr_out <= write_curr or write_default;
+--  min_curr_out   <= min_default when write_default = '1' else
+--                    min_curr;
+--  min_out_out    <= min_default when write_default = '1' else
+--                    min_out;
+--  max_curr_out   <= max_default when write_default = '1' else
+--                    max_curr;
+--  max_out_out    <= max_default when write_default = '1' else
+--                    max_out;
+  write_curr_out <= write_curr;
+  min_curr_out   <= min_curr;
+  min_out_out    <= min_out;
+  max_curr_out   <= max_curr;
+  max_out_out    <= max_out;
+  dflt_out       <= dflt_i(0,3)&dflt_i(0,2)&dflt_i(0,1)&dflt_i(0,0);
+ 
   --synchronous output
   proc_slope : process (CLK)
   begin
@@ -343,7 +377,11 @@ begin
     chnl_out_write <= chnl_r;
     FPGA_out_write <= fpga_r;
     FPGA_out       <= fpga_r;
-    FPGA_out_curr  <= fpga_r;
+    if Flash_flag = '1' then 
+      FPGA_out_curr  <= fpga_r; -- fpga number from Flash
+    else 
+      FPGA_out_curr  <= fpga_r;
+    end if;
     
     chnl_out       <= chnl_r;
     chnl_out_curr  <= chnl_r;

diff --git a/combiner_calib/code_EBR/Calibration.vhd b/combiner_calib/code_EBR/Calibration.vhd
index 374ec30520266e6d5d97608b27dea3b1dd921819..bd789b5723a5244ddde08bf8918824c192cbf17c 100644 (file)
--- a/combiner_calib/code_EBR/Calibration.vhd
+++ b/combiner_calib/code_EBR/Calibration.vhd
@@ -80,17 +80,17 @@ architecture Behavioral of TDC_Calibration is
   signal FPGA_o_cnt          : std_logic_vector( 3 downto 0);
   signal chnl_read_cnt       : std_logic_vector( 6 downto 0);
   signal cal_cnt_in          : unsigned(19 downto 0);
-  signal cal_cnt_out         : unsigned(19 downto 0);   
+  signal cal_cnt_out         : unsigned(19 downto 0) := "00000000000000000000";   
   signal DIN_o_cnt_val       : std_logic_vector(31 downto 0);
   signal DIN_o_cnt_val_ready : std_logic;
   signal DIN_o_cnt_val_type  : std_logic_vector( 3 downto 0);
   signal DIN_MemCurr_data    : std_logic_vector(31 downto 0);
   signal DIN_MemCurr_ready   : std_logic;
   signal DIN_MemCurr_type    : std_logic_vector( 3 downto 0);
-  signal Do_Cal_read_cnt     : std_logic;
+  signal Do_Cal_read_cnt     : std_logic := '0';
   signal CHNL_out_Memory     : std_logic_vector( 6 downto 0);
   signal FPGA_out_Memory     : std_logic_vector( 3 downto 0);
-  signal Do_Cal_Memory       : std_logic;
+  signal Do_Cal_Memory       : std_logic := '0';
   signal write_chnl_cnt      : std_logic;
   signal chnl_out_write      : std_logic_vector( 6 downto 0);
   signal FPGA_out_write      : std_logic_vector( 3 downto 0);
@@ -166,6 +166,10 @@ architecture Behavioral of TDC_Calibration is
   signal DIN_info_CalcOut    : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
   signal DIN_info_ready      : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
   
+  signal ch0_onoff           : std_logic_vector(15 downto 0) := x"FFFF";
+  signal dflt_out            : std_logic_vector( 3 downto 0) := x"0";
+  signal cnt_i_debug         : unsigned(19 downto 0);
+  
   component RAM_pseudo_DP_wReg_36x1k is
     port (
       WrAddress : in  std_logic_vector( 9 downto 0); 
@@ -211,6 +215,8 @@ begin
                 Bus_FPGA        <= BUS_RX.data(3 downto 0);                -- set channel for Min/Max Output
         when x"003"   => 
                 Bus_Chnl        <= BUS_RX.data(6 downto 0);                -- set channel for Min/Max Output
+        when x"004"   => 
+                ch0_onoff       <= BUS_RX.data(15 downto 0);                -- set channel0 On/off
         when others   =>
                 BUS_TX.ack      <= '0';
                 BUS_TX.unknown  <= '1';
@@ -249,14 +255,16 @@ begin
                           BUS_TX.data(19 downto  0) <= std_logic_vector(cal_cnt_in);
         when x"A"      => BUS_TX.data <= Debug_Data_min;
         when x"B"      => BUS_TX.data <= Debug_Data_max;
-        when x"C"      => BUS_TX.data(31 downto 20) <= (others => '0');
-                          BUS_TX.data(19 downto  0) <= Max_Monitoring & Min_Monitoring;--MinMax_Monitor(0,16);
+        when x"C"      => BUS_TX.data(31 downto 22) <= (others => '0');
+                          BUS_TX.data(21 downto 12) <= Max_Monitoring;--MinMax_Monitor(0,16);
+                          BUS_TX.data(11 downto 10) <= (others => '0');
+                          BUS_TX.data( 9 downto  0) <= Min_Monitoring;
         when x"D"      => BUS_TX.data(31 downto 20) <= (others => '0');
-                          BUS_TX.data(19 downto  0) <= MinMax_Monitor(0,17);
-        when x"E"      => BUS_TX.data(31 downto 20) <= (others => '0');
-                          BUS_TX.data(19 downto  0) <= MinMax_Monitor(0,18);
-        when x"F"      => BUS_TX.data(31 downto 20) <= (others => '0');
-                          BUS_TX.data(19 downto  0) <= MinMax_Monitor(0,19);
+                          BUS_TX.data(19 downto  0) <= std_logic_vector(cnt_i_debug);--MinMax_Monitor(0,17);
+        when x"E"      => BUS_TX.data(31 downto  4) <= (others => '0');--BUS_TX.data(31 downto 20) <= (others => '0');
+                          BUS_TX.data( 3 downto  0) <= dflt_out;--BUS_TX.data(19 downto  0) <= MinMax_Monitor(0,18);
+        when x"F"      => BUS_TX.data(31 downto 16) <= (others => '0');
+                          BUS_TX.data(15 downto  0) <= ch0_onoff;
         when others   =>  BUS_TX.ack     <= '0';
                           BUS_TX.unknown <= '1';
       end case;
@@ -381,7 +389,8 @@ begin
       FPGA_mntr     => FPGA_mntr,
       stop_Limit    => stp_Lmt_read_cnt,
       DIN_info      => DIN_info_ready,
-      DOUT_info     => DIN_info_rc
+      DOUT_info     => DIN_info_rc,
+      ch0_onoff     => ch0_onoff
     );
 --   end generate read_COMBINER;
  
@@ -482,14 +491,14 @@ begin
       chnl_cnt_in        => cal_cnt_out,
       BUS_Flash_value    => BUS_Flash_value,
       Flash_flag         => Flash_flag,
-      write_curr         => write_curr,
+      write_curr_out     => write_curr,
       write_next         => write_next,
       min_next           => min_next_Lim,
       max_next           => max_next_Lim,
-      min_curr           => min_curr_Lim,
-      max_curr           => max_curr_Lim,
-      min_out            => min_out_Lim,
-      max_out            => max_out_Lim,
+      min_curr_out       => min_curr_Lim,
+      max_curr_out       => max_curr_Lim,
+      min_out_out        => min_out_Lim,
+      max_out_out        => max_out_Lim,
       Delta              => Delta_Lim,
       FPGA_out           => FPGA_Lim,
       chnl_out           => chnl_Lim,
@@ -509,7 +518,9 @@ begin
       Debug_Data_min     => Debug_Data_min,
       Debug_Data_max     => Debug_Data_max,
       DIN_info           => DIN_info_mem,
-      DOUT_info          => DIN_info_Lim
+      DOUT_info          => DIN_info_Lim,
+      dflt_out           => dflt_out,
+      cnt_i_debug        => cnt_i_debug
     );
 
 

diff --git a/combiner_calib/code_EBR/read_cnt.vhd b/combiner_calib/code_EBR/read_cnt.vhd
index 1d8a82e65b41e21caa8ce291e4211e24ae7bfa0b..1d459ec9efe0531559a0e47ab0324431807b11eb 100644 (file)
--- a/combiner_calib/code_EBR/read_cnt.vhd
+++ b/combiner_calib/code_EBR/read_cnt.vhd
@@ -30,7 +30,8 @@ entity read_cnt is
     FPGA_cnt_mntr : out std_logic_vector( 3 downto 0);
     FPGA_mntr     : out std_logic_vector(15 downto 0);
     stop_Limit    : out std_logic;
-    DOUT_info                  : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0)
+    DOUT_info                  : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+    ch0_onoff     : in std_logic_vector(15 downto 0)
   );
 end read_cnt;
 
@@ -61,7 +62,10 @@ begin
         Do_Cal  <= '1';
         if ((Trigger_type = BUS_Trig_type ) or (BUS_Trig_type = "0000")) then
           stop_Limit <= BUS_stp_Lmt;
-        end if;  
+        end if;
+        if (DIN(28 downto 22) = "0000000") and (ch0_onoff(FPGA_i) = '0') then
+          Do_Cal <= '0';
+        end if;
       else
         Do_Cal  <= '0';
       end if;