signal fifo_sel_i : integer range -1 to g_inputs - 1 := -1;
signal fifo_sel_reg : integer range 0 to g_inputs - 1 := 0;
+ signal request_i : std_logic_vector(g_inputs - 1 downto 0);
+ signal grant_i : std_logic_vector(g_inputs - 1 downto 0);
+
type t_mux_state is (idle, wait_fifo, write);
signal mux_fsm : t_mux_state := idle;
+ component RoundRobinArbiter
+ generic(g_num_channels : integer := 4);
+ port(
+ clk : in std_logic;
+ requests : in std_logic_vector(g_num_channels - 1 downto 0);
+ grant : out std_logic_vector(g_num_channels - 1 downto 0)
+ );
+ end component RoundRobinArbiter;
+
begin
- fifo_select_proc : process(fifo_empty, fifo_mask) is
+ request_i <= not fifo_empty and fifo_mask;
+
+ arbiter_1 : component RoundRobinArbiter
+ generic map(
+ g_num_channels => g_inputs
+ )
+ port map(
+ clk => clk,
+ requests => request_i,
+ grant => grant_i
+ );
+
+ fifo_select_proc : process(grant_i) is
variable sel : integer range -1 to g_inputs - 1;
begin
sel := -1;
for i in 0 to g_inputs - 1 loop
- if fifo_empty(i) = '0' and fifo_mask(i) = '1' then
+ if grant_i(i) = '1' then
sel := i;
end if;
end loop;
add_file -vhdl -lib "work" "sources/DataMux.vhd"
add_file -vhdl -lib "work" "sources/MupixDataLink.vhd"
add_file -vhdl -lib "work" "sources/TriggerHandler.vhd"
+add_file -vhdl -lib "work" "sources/Arbiter.vhd"