]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
add round robin arbiter to mupix 8 readout.
authorTobias Weber <toweber86@gmail.com>
Wed, 21 Feb 2018 14:01:08 +0000 (15:01 +0100)
committerTobias Weber <toweber86@gmail.com>
Wed, 21 Feb 2018 14:01:08 +0000 (15:01 +0100)
mupix/Mupix8/sources/DataMux.vhd
mupix/Mupix8/trb3_periph.prj

index f7fe6a12a4c655049fd0f78182e708fc134bd1d7..f4255e2791f9a3515828ba0b1306e7b2398c2930 100644 (file)
@@ -41,17 +41,41 @@ architecture RTL of FiFoDataMux is
        signal fifo_sel_i   : integer range -1 to g_inputs - 1 := -1;
        signal fifo_sel_reg : integer range 0  to g_inputs - 1 := 0;
        
+       signal request_i : std_logic_vector(g_inputs - 1 downto 0);
+       signal grant_i : std_logic_vector(g_inputs - 1 downto 0);
+       
        type t_mux_state is (idle, wait_fifo, write);
        signal mux_fsm : t_mux_state := idle;
        
+       component RoundRobinArbiter
+               generic(g_num_channels : integer := 4);
+               port(
+                       clk      : in  std_logic;
+                       requests : in  std_logic_vector(g_num_channels - 1 downto 0);
+                       grant    : out std_logic_vector(g_num_channels - 1 downto 0)
+               );
+       end component RoundRobinArbiter;
+       
 begin
        
-       fifo_select_proc : process(fifo_empty, fifo_mask) is
+       request_i  <= not fifo_empty and fifo_mask;
+       
+       arbiter_1 : component RoundRobinArbiter
+               generic map(
+                       g_num_channels => g_inputs
+               )
+               port map(
+                       clk      => clk,
+                       requests => request_i,
+                       grant    => grant_i
+               );
+       
+       fifo_select_proc : process(grant_i) is
                variable sel : integer range -1 to g_inputs - 1;
        begin
                sel        := -1;
                for i in 0 to g_inputs - 1 loop
-                       if fifo_empty(i) = '0' and fifo_mask(i) = '1' then
+                       if grant_i(i) = '1' then
                                sel := i;
                        end if;
                end loop;
index 67d44de04960b643ff3de03de20362a9c163dc67..5f0ff9401eb5e9320f6a7edce3c882c2be7580bf 100644 (file)
@@ -173,3 +173,4 @@ add_file -vhdl -lib "work" "sources/MupixTRBReadout.vhd"
 add_file -vhdl -lib "work" "sources/DataMux.vhd"
 add_file -vhdl -lib "work" "sources/MupixDataLink.vhd"
 add_file -vhdl -lib "work" "sources/TriggerHandler.vhd"
+add_file -vhdl -lib "work" "sources/Arbiter.vhd"