PLL regenerated

diff --git a/base/cores/pll_200_4.ipx b/base/cores/pll_200_4.ipx
index 278881d0a95baf8e40a1473ed1e38c0b2b77b861..5aedab1f8be161e9de014c37a3fa41494aa4bbeb 100644 (file)
--- a/base/cores/pll_200_4.ipx
+++ b/base/cores/pll_200_4.ipx
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_200_4" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 10 07 15:22:33.407" version="5.3" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="pll_200_4" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 07 03 18:18:13.851" version="5.4" type="Module" synthesis="" source_format="VHDL">
   <Package>
-               <File name="pll_200_4.lpc" type="lpc" modified="2014 10 07 15:22:29.000"/>
-               <File name="pll_200_4.vhd" type="top_level_vhdl" modified="2014 10 07 15:22:29.000"/>
-               <File name="pll_200_4_tmpl.vhd" type="template_vhdl" modified="2014 10 07 15:22:29.000"/>
+               <File name="pll_200_4.lpc" type="lpc" modified="2015 07 03 18:18:12.000"/>
+               <File name="pll_200_4.vhd" type="top_level_vhdl" modified="2015 07 03 18:18:12.000"/>
+               <File name="pll_200_4_tmpl.vhd" type="template_vhdl" modified="2015 07 03 18:18:12.000"/>
   </Package>
 </DiamondModule>

diff --git a/base/cores/pll_200_4.lpc b/base/cores/pll_200_4.lpc
index d9d8853ffe8ef67b990a74ed679179a94925f4e3..93246cab6cc1b5ea9ee1b78d8b959921d8fde033 100644 (file)
--- a/base/cores/pll_200_4.lpc
+++ b/base/cores/pll_200_4.lpc
@@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation
 CoreType=LPM
 CoreStatus=Demo
 CoreName=PLL
-CoreRevision=5.3
+CoreRevision=5.4
 ModuleName=pll_200_4
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=10/07/2014
-Time=15:22:29
+Date=07/03/2015
+Time=18:18:12
 
 [Parameters]
 Verilog=0
@@ -38,7 +38,7 @@ OP_Tol=0.0
 OFrq=4.000000
 DutyTrimP=Rising
 DelayMultP=0
-fb_mode=CLKOP
+fb_mode=Internal
 Mult=1
 Phase=0.0
 Duty=8

diff --git a/base/cores/pll_200_4.vhd b/base/cores/pll_200_4.vhd
index 6259145b5fca3df8f45342be8ef83d53b7c61f32..451db0a166b4ad3336eabb739745b7fc17f3a71e 100644 (file)
--- a/base/cores/pll_200_4.vhd
+++ b/base/cores/pll_200_4.vhd
@@ -1,8 +1,8 @@
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module  Version: 5.3
---/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_200_4 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 4 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw -e 
+-- VHDL netlist generated by SCUBA Diamond_3.0_Production (94)
+-- Module  Version: 5.4
+--/d/jspc29/lattice/diamond/3.0_x64/ispfpga/bin/lin64/scuba -w -n pll_200_4 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 4 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -use_rst -noclkok2 -bw -e 
 
--- Tue Oct  7 15:22:29 2014
+-- Fri Jul  3 18:18:12 2015
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -25,6 +25,7 @@ architecture Structure of pll_200_4 is
 
     -- internal signal declarations
     signal CLKOP_t: std_logic;
+    signal CLKFB_t: std_logic;
     signal scuba_vlo: std_logic;
 
     -- local component declarations
@@ -68,7 +69,7 @@ begin
         port map (Z=>scuba_vlo);
 
     PLLInst_0: EHXPLLF
-        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED", 
         CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
         CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
         CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
@@ -76,13 +77,13 @@ begin
         PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
         CLKOK_DIV=>  2, CLKOP_DIV=>  128, CLKFB_DIV=>  1, CLKI_DIV=>  50, 
         FIN=> "200.000000")
-        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo, 
+        port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>RESET, RSTK=>scuba_vlo, 
             WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, 
             DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, 
             DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, 
             FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, 
             FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, 
-            CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open);
+            CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>CLKFB_t);
 
     CLKOP <= CLKOP_t;
 end Structure;