--- /dev/null
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+use FileHandle;
+use Getopt::Long;
+
+###################################################################################
+#Settings for this project
+my $TOPNAME = "trb3_periph_padiwa"; #Name of top-level entity
+#my $lattice_path = '/opt/lattice/diamond/3.0_x64/';
+#my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed
+my $lattice_path = '/opt/lattice/diamond/2.01/';
+my $lattice_bin_path = "$lattice_path/bin/lin"; # note the lin/lin64 at the end, no isfgpa needed
+my $synplify_path = '/opt/synplicity/F-2012.03-SP1';
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
+###################################################################################
+
+###################################################################################
+#Options for the script
+my $help = "";
+my $isMultiPar = 0; # set it to zero for single par run on the local machine
+my $nrNodes = 0; # set it to one for single par run on the local machine
+my $all = 1;
+my $syn = 0;
+my $map = 0;
+my $par = 0;
+my $timing = 0;
+my $bitgen = 0;
+
+my $result = GetOptions (
+ "h|help" => \$help,
+ "m|mpar=i" => \$nrNodes,
+ "a|all" => \$all,
+ "s|syn" => \$syn,
+ "mp|map" => \$map,
+ "p|par" => \$par,
+ "t|timing" => \$timing,
+ "b|bitgen" => \$bitgen,
+ );
+
+if($help) {
+ print "Usage: compile_priph_gsi.de <OPTIONS><ARGUMENTS>\n\n";
+ print "-h --help\tPrints the usage manual.\n";
+ print "-a --all\tRun all compile script. By default the script is going to rung the whole process.\n";
+ print "-s --syn\tRun synthesis part of the compile script.\n";
+ print "-mp --map\tRun map part of the compile script.\n";
+ print "-p --par\tRun par part of the compile script.\n";
+ print "-t --timing\tRun timing analysis part of the compile script.\n";
+ print "-b --bitgen\tRun bit generation part of the compile script.\n";
+ print "-m --mpar\tSwitch for multi par. \"-m <number_of_nodes>\" (Default = off)\n";
+ print "\t\tThe node list file name has to be edited in the script. (Default = nodes_lxhadeb07.txt)\n";
+ print "\n";
+ exit;
+}
+
+if ($nrNodes!=0){
+ $isMultiPar=1;
+}
+if ($syn!=0 || $map!=0 || $par!=0 || $timing!=0 || $bitgen!=0){
+ $all=0;
+}
+###################################################################################
+
+
+
+# source the standard lattice environment
+$ENV{bindir}="$lattice_bin_path";
+open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env >& /dev/null; env'|" or
+ die "Can't fork: $!";
+while (<$SOURCE>) {
+ if (/^(.*)=(.*)/) {
+ $ENV{$1} = ${2} ;
+ }
+}
+close $SOURCE;
+
+
+$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA672";
+my $SPEEDGRADE="8";
+
+my $WORKDIR = "workdir";
+unless(-d $WORKDIR) {
+ mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!";
+}
+
+system("ln -sfT $lattice_path $WORKDIR/lattice-diamond");
+
+#create full lpf file
+system("cp ../base/trb3_periph_32PinAddOn.lpf workdir/$TOPNAME.lpf");
+system("cat currentRelease/trbnet_constraints.lpf >> workdir/$TOPNAME.lpf");
+system("cat currentRelease/tdc_constraints_2.lpf >> workdir/$TOPNAME.lpf");
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+my $c = "";
+my @a = ();
+my $tpmap = $TOPNAME . "_map" ;
+
+if($syn==1 || $all==1){
+ $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+ $r=execute($c, "do_not_exit" );
+}
+
+chdir $WORKDIR;
+
+if($syn==1 || $all==1){
+ $fh = new FileHandle("<$TOPNAME".".srr");
+ @a = <$fh>;
+ $fh -> close;
+
+ foreach (@a)
+ {
+ if(/\@E:/)
+ {
+ print "\n";
+ $c="cat $TOPNAME.srr | grep \"\@E\"";
+ system($c);
+ print "\n\n";
+ exit 129;
+ }
+ }
+}
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+if($map==1 || $all==1){
+ $c=qq| edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+ execute($c);
+
+ $c=qq|edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+ execute($c);
+
+ $c=qq|ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+ execute($c);
+
+ $c=qq|map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+ execute($c);
+
+ $fh = new FileHandle("$TOPNAME.mrp");
+ @a = <$fh>;
+ $fh -> close;
+ my $fileSize = @a;
+ my $isParError = 0;
+
+ open (DEBUG, '>debug.txt');
+ for (my $i=0; $i<$fileSize; )
+ {
+ my @line = split(' ', $a[$i]);
+ if (@line && ($line[0] eq "WARNING"))
+ {
+ my $warning = $a[$i];
+ chomp $warning;
+ my $k = 1;
+ my @nextLine = split(' ', $a[$i+$k]);
+ if(!@nextLine)
+ {
+ $k+=10;
+ @nextLine = split(' ', $a[$i+$k]);
+ }
+ while ($nextLine[0] ne "WARNING")
+ {
+ my $b = $a[$i+$k];
+ chomp $b;
+ $b =~ s/^\s+//;
+ $warning = join (' ', $warning, $b);
+ $k++;
+ @nextLine = split(' ', $a[$i+$k]);
+ if(!@nextLine)
+ {
+ $k+=10;
+ @nextLine = split(' ', $a[$i+$k]);
+ }
+ if ($k>20)
+ {
+ last;
+ }
+ }
+ #open my $keywords, '<', '../keywords.txt' or die "Can't open keywords: $!";
+ if ($warning =~ /FC_|hit_|ff_en_/)
+ {
+ print DEBUG $warning."\n\n";
+ $isParError = 1;
+ }
+ }
+ $i++;
+ }
+ close (DEBUG);
+
+ if ($isParError)
+ {
+ print "\n\n";
+ print "#################################################\n";
+ print "# !!!Possible Placement Errors!!! #\n";
+ print "#################################################\n\n";
+
+ my $c="egrep \"FC_|hit_|ff_en_\" debug.txt";
+ system($c);
+ }
+}
+
+
+if($par==1 || $all==1){
+ system("rm $TOPNAME.ncd");
+ #$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
+ #$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+ if ($isMultiPar)
+ {
+ $c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parDisablePgroup=0:parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|;
+ execute($c);
+ # find and copy the .ncd file which has met the timing constraints
+ $fh = new FileHandle("<$TOPNAME".".par");
+ my @a = <$fh>;
+ my $isSuccess = 0;
+ $fh -> close;
+ foreach (@a)
+ {
+ my @line = split(' ', $_);
+ if($line[3]==0)
+ {
+ print "Copying $line[0].ncd file to workdir\n";
+ my $c="cp trb3_periph_32PinAddOn.dir/$line[0].ncd trb3_periph_32PinAddOn.ncd";
+ system($c);
+ print "\n\n";
+ $isSuccess = 1;
+ last;
+ }
+ }
+
+ if (!$isSuccess){
+ print "\n\n";
+ print "#################################################\n";
+ print "# !!!PAR not succesfull!!! #\n";
+ print "#################################################\n\n";
+ exit 129;
+ }
+ }
+ else
+ {
+ $c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|;
+ execute($c);
+ my $c="cp trb3_periph_32PinAddOn.dir/5_1.ncd trb3_periph_32PinAddOn.ncd";
+ system($c);
+ }
+ my $c="cat trb3_periph_32PinAddOn.par";
+ system($c);
+}
+
+
+if($timing==1 || $all==1){
+ # IOR IO Timing Report
+ $c=qq|iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+ execute($c);
+
+ # TWR Timing Report
+ $c=qq|trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+ execute($c);
+
+ $c=qq|trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+ execute($c);
+
+ $c=qq|ltxt2ptxt $TOPNAME.ncd|;
+ execute($c);
+
+ my $c="cat trb3_periph_32PinAddOn.par";
+ system($c);
+}
+
+if($bitgen==1 || $all==1){
+ $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+ # $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+ execute($c);
+}
+
+chdir "..";
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+ return $r;
+}
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+--Include GbE logic
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65;
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons
+ constant USE_DOUBLE_EDGE : integer := c_YES;
+ --constant ADDON_TYPE : integer := 0; -- ADA v1
+ --constant ADDON_TYPE : integer := 1; -- ADA v2
+ --constant ADDON_TYPE : integer := 2; -- Multitest
+ --constant ADDON_TYPE : integer := 3; -- SFP
+ constant ADDON_TYPE : integer := 4; -- Padiwa
+ --constant ADDON_TYPE : integer := 5; -- GPIN
+ --constant ADDON_TYPE : integer := 6; -- Nxyter
+ --constant ADDON_TYPE : integer := 7; -- 32PinAddon
+
+--Include SPI on AddOn connector
+ constant INCLUDE_SPI : integer := c_YES;
+
+--Add logic to generate configurable trigger signal from input signals.
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
+
+--Run wih 125 MHz instead of 100 MHz
+ constant USE_125_MHZ : integer := c_NO; --not implemented yet!
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO; --not implemented yet!
+
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F306";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"48";
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"91007000";
+ constant HW_INFO_SPI : hw_info_t := (x"00000000",x"00000400", others => x"00000000");
+ constant HW_INFO_DOUBLE_EDGE : hw_info_t := (x"00000000",x"00000800", others => x"00000000");
+ constant HW_INFO_NUM_CHANS : hw_info_t := (x"00000000",x"00000010",x"00000020",x"00000030",
+ x"00000040",x"00000050",x"00000060",x"00000070", others => x"00000000");
+ constant HW_INFO_ADDON : hw_info_t := (x"00000000",x"00001000",x"00002000",x"00003000",
+ x"00004000",x"00005000",x"00006000",x"00007000", others => x"00000000");
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,125, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,125, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ HW_INFO_BASE + HW_INFO_SPI(INCLUDE_SPI) + HW_INFO_DOUBLE_EDGE(USE_DOUBLE_EDGE) +
+ HW_INFO_NUM_CHANS(NUM_TDC_CHANNELS_POWER2) + HW_INFO_ADDON(ADDON_TYPE));
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
+
+end package body;
#add_file options
add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "config.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
add_file -vhdl -lib "work" "../base/trb3_components.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
###############
#Change path to tdc release also in compile script!
###############
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Adder_304.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/bit_sync.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/BusHandler.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel_200.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/FIFO_32x32_OutReg.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Readout.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel_200.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_encoder_3.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_FIFO.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/TDC.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/up_counter.vhd"
+
+#add_file -vhdl -lib "work" "currentRelease/Adder_304.vhd"
+add_file -vhdl -lib "work" "currentRelease/bit_sync.vhd"
+add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd"
+add_file -vhdl -lib "work" "currentRelease/Channel.vhd"
+add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd"
+add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd"
+add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd"
+add_file -vhdl -lib "work" "currentRelease/Readout.vhd"
+add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd"
+add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd"
+add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib "work" "currentRelease/TDC.vhd"
+add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd"
+add_file -vhdl -lib "work" "currentRelease/up_counter.vhd"
+add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd"
+add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd"
+add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd"
+
add_file -vhdl -lib "work" "trb3_periph_padiwa.vhd"
use work.trb_net_std.all;
use work.trb_net_components.all;
use work.trb3_components.all;
+use work.config.all;
use work.version.all;
--Clock / Reset
signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal clk_125_i : std_logic; -- 125 MHz, via Clock Manager and bypassed PLL
- signal clk_20_i : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL
+ signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
signal clear_i : std_logic;
signal reset_i : std_logic;
signal tdc_ctrl_addr : std_logic_vector(2 downto 0);
signal tdc_ctrl_data_in : std_logic_vector(31 downto 0);
signal tdc_ctrl_data_out : std_logic_vector(31 downto 0);
- signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0);
+ signal tdc_ctrl_reg : std_logic_vector(6*32-1 downto 0);
signal spi_bram_addr : std_logic_vector(7 downto 0);
signal spi_bram_wr_d : std_logic_vector(7 downto 0);
signal padiwa_sdi : std_logic;
signal padiwa_sdo : std_logic;
+ signal trig_out : std_logic_vector(3 downto 0);
+ signal trig_din : std_logic_vector(31 downto 0);
+ signal trig_dout : std_logic_vector(31 downto 0);
+ signal trig_write : std_logic := '0';
+ signal trig_read : std_logic := '0';
+ signal trig_ack : std_logic := '0';
+ signal trig_nack : std_logic := '0';
+ signal trig_addr : std_logic_vector(15 downto 0) := (others => '0');
+
--TDC
signal hit_in_i : std_logic_vector(64 downto 1);
LOCK => pll_lock
);
- -- generates hits for calibration uncorrelated with tdc clk
- THE_CALIBRATION_PLL : pll_in125_out20
+ -- internal oscillator with frequency of 2.5MHz for tdc calibration
+ OSCInst0 : OSCF
port map (
- CLK => CLK_GPLL_LEFT,
- CLKOP => clk_20_i,
- CLKOK => clk_125_i,
- LOCK => open);
+ OSC => osc_int);
gen_sync_clocks : if SYNC_MODE = c_YES generate
clk_100_i <= rx_clock_100;
---------------------------------------------------------------------------
-- Endpoint
---------------------------------------------------------------------------
- --regio_hardware_version_i <= x"9100" & addOn_type_i & edge_type_i & tdc_channel_no_i & x"0";
-
- --addOn_type_i <= x"0"; -- x"0" - ADA AddOn version 1
- -- -- x"1" - ADA AddOn version 2
- -- -- x"2" - multi purpose test AddOn
- -- -- x"3" - SFP hub AddOn
- -- -- x"4" - Wasa AddOn
- --edge_type_i <= x"0"; -- x"0" - single edge
- -- -- x"1" - double edge
- -- -- x"8" - double edge on consecutive channels
- --tdc_channel_no_i <= x"6"; -- 2^n channels
THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
generic map(
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,
ADDRESS_MASK => x"FFFF",
BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"48",
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"91004860",
- REGIO_INIT_ADDRESS => x"f306",
+ REGIO_HARDWARE_VERSION => HARDWARE_INFO,
+ REGIO_INIT_ADDRESS => INIT_ADDRESS,
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => 100,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 1,
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 9,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"b000", 8 => x"c800", others => x"0000"),
- PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 9, 8 => 3, others => 0)
+ PORT_NUMBER => 10,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"b000", 8 => x"c800", 9 => x"a000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 9, 8 => 3, 9 => 6, others => 0)
)
port map(
CLK => clk_100_i,
BUS_NO_MORE_DATA_IN(8) => '0',
BUS_UNKNOWN_ADDR_IN(8) => '0',
+ --Trigger logic registers
+ BUS_READ_ENABLE_OUT(9) => trig_read,
+ BUS_WRITE_ENABLE_OUT(9) => trig_write,
+ BUS_DATA_OUT(9*32+31 downto 9*32) => trig_din,
+ BUS_ADDR_OUT(9*16+15 downto 9*16) => trig_addr,
+ BUS_TIMEOUT_OUT(9) => open,
+ BUS_DATA_IN(9*32+31 downto 9*32) => trig_dout,
+ BUS_DATAREADY_IN(9) => trig_ack,
+ BUS_WRITE_ACK_IN(9) => trig_ack,
+ BUS_NO_MORE_DATA_IN(9) => '0',
+ BUS_UNKNOWN_ADDR_IN(9) => trig_nack,
+
STAT_DEBUG => open
);
---------------------------------------------------------------------------
-- DAC
---------------------------------------------------------------------------
- THE_DAC_SPI : spi_ltc2600
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_ADDR_IN => dac_addr,
- BUS_READ_IN => dac_read_en,
- BUS_WRITE_IN => dac_write_en,
- BUS_ACK_OUT => dac_ack,
- BUS_BUSY_OUT => dac_busy,
- BUS_DATA_IN => dac_data_in,
- BUS_DATA_OUT => dac_data_out,
- -- SPI connections
- SPI_CS_OUT(3 downto 0) => padiwa_cs,
- SPI_SDI_IN => padiwa_sdi,
- SPI_SDO_OUT => padiwa_sdo,
- SPI_SCK_OUT => padiwa_sck
- );
-
+ gen_SPI : if INCLUDE_SPI = 1 generate
+ THE_DAC_SPI : spi_ltc2600
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => dac_addr,
+ BUS_READ_IN => dac_read_en,
+ BUS_WRITE_IN => dac_write_en,
+ BUS_ACK_OUT => dac_ack,
+ BUS_BUSY_OUT => dac_busy,
+ BUS_DATA_IN => dac_data_in,
+ BUS_DATA_OUT => dac_data_out,
+ -- SPI connections
+ SPI_CS_OUT(3 downto 0) => padiwa_cs,
+ SPI_SDI_IN => padiwa_sdi,
+ SPI_SDO_OUT => padiwa_sdo,
+ SPI_SCK_OUT => padiwa_sck
+ );
+ OUT_CS <= padiwa_cs(3 downto 0);
+ OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck;
+ OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo;
+ padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
+ end generate;
- OUT_CS <= padiwa_cs(3 downto 0);
- OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck;
- OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo;
- padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
+---------------------------------------------------------------------------
+-- Trigger logic
+---------------------------------------------------------------------------
+ gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
+ THE_TRIG_LOGIC : input_to_trigger_logic
+ generic map(
+ INPUTS => 32,
+ OUTPUTS => 4
+ )
+ port map(
+ CLK => clk_100_i,
+
+ INPUT => INP(32 downto 1),
+ OUTPUT => trig_out,
+
+ DATA_IN => trig_din,
+ DATA_OUT => trig_dout,
+ WRITE_IN => trig_write,
+ READ_IN => trig_read,
+ ACK_OUT => trig_ack,
+ NACK_OUT => trig_nack,
+ ADDR_IN => trig_addr
+ );
+ FPGA5_COMM(10 downto 7) <= trig_out;
+ end generate;
---------------------------------------------------------------------------
-- Reboot FPGA
-------------------------------------------------------------------------------
THE_TDC : TDC
generic map (
- CHANNEL_NUMBER => 65, -- Number of TDC channels
- CONTROL_REG_NR => 5, -- Number of control regs - higher than 8 check tdc_ctrl_addr
- TDC_VERSION => "001" & x"51") -- TDC version number
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels
+ STATUS_REG_NR => 20, -- Number of status regs
+ CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr
+ TDC_VERSION => x"160", -- TDC version number
+ DEBUG => c_YES,
+ SIMULATION => c_NO)
port map (
RESET => reset_i,
CLK_TDC => clk_tdc, -- Clock used for the time measurement
CLK_READOUT => clk_100_i, -- Clock for the readout
- REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => hit_in_i(64 downto 1), -- Channel start signals
- HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC
+ REFERENCE_TIME => timing_trg_received_i, -- Reference time input
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+ HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC
TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
--
LOGIC_ANALYSER_OUT => TEST_LINE,
CONTROL_REG_IN => tdc_ctrl_reg);
-
- ---- For single edge measurements
- --hit_in_i <= INP;
+ -- For single edge measurements
+ gen_single : if USE_DOUBLE_EDGE = 0 generate
+ hit_in_i <= INP;
+ end generate;
-- For ToT Measurements
- Gen_Hit_In_Signals : for i in 1 to 32 generate
- hit_in_i(i*2-1) <= INP(i-1);
- hit_in_i(i*2) <= not INP(i-1);
- end generate Gen_Hit_In_Signals;
-
- -- !!!!! IMPORTANT !!!!! Don't forget to set the REGIO_HARDWARE_VERSION !!!!!
-
+ gen_double : if USE_DOUBLE_EDGE = 1 generate
+ Gen_Hit_In_Signals : for i in 1 to 32 generate
+ hit_in_i(i*2-1) <= INP(i-1);
+ hit_in_i(i*2) <= not INP(i-1);
+ end generate Gen_Hit_In_Signals;
+ end generate;
end architecture;
jspc29 / trb3.git / commitdiff