cleanup in mac control, reset changes in med_fifo

diff --git a/gbe_trb/base/trb_net16_gbe_mac_control.vhd b/gbe_trb/base/trb_net16_gbe_mac_control.vhd
index 978387f5855afbf7969a1b99c0ae6e2b47a8f1f4..e575600ce3fe1608a778fd02f44313ab1175e489 100644 (file)
--- a/gbe_trb/base/trb_net16_gbe_mac_control.vhd
+++ b/gbe_trb/base/trb_net16_gbe_mac_control.vhd
@@ -20,10 +20,10 @@ entity trb_net16_gbe_mac_control is
   -- signals to/from main controller
     MC_TSMAC_READY_OUT  : out std_logic;
     MC_RECONF_IN        : in  std_logic;
-    MC_GBE_EN_IN        : in  std_logic;
-    MC_RX_DISCARD_FCS   : in  std_logic;
-    MC_PROMISC_IN       : in  std_logic;
-    MC_MAC_ADDR_IN      : in  std_logic_vector(47 downto 0);
+    MC_GBE_EN_IN        : in  std_logic; -- fixed to '1'
+--    MC_RX_DISCARD_FCS   : in  std_logic;
+    MC_PROMISC_IN       : in  std_logic; -- fixed to '1'
+--    MC_MAC_ADDR_IN      : in  std_logic_vector(47 downto 0);
   -- signal to/from Host interface of TriSpeed MAC
     TSM_HADDR_OUT       : out std_logic_vector(7 downto 0);
     TSM_HDATA_OUT       : out std_logic_vector(7 downto 0);
@@ -49,11 +49,6 @@ attribute syn_encoding of mac_conf_current_state : signal is "onehot";
 signal tsmac_ready                          : std_logic;
 signal reg_mode                             : std_logic_vector(7 downto 0);
 signal reg_tx_rx_ctrl1, reg_tx_rx_ctrl2     : std_logic_vector(7 downto 0);
-signal reg_max_pkt_size                     : std_logic_vector(15 downto 0);
-signal reg_ipg                              : std_logic_vector(15 downto 0);
-signal reg_mac0                             : std_logic_vector(15 downto 0);
-signal reg_mac1                             : std_logic_vector(15 downto 0);
-signal reg_mac2                             : std_logic_vector(15 downto 0);
 
 signal haddr                                : std_logic_vector(7 downto 0);
 signal hcs_n                                : std_logic;

diff --git a/gbe_trb_ecp3/media/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd
index 84ca503459e85584d9549722da702f6b41f4c3a2..6de563ba6f964acaefae96ed34a5d9dfca9b48e0 100644 (file)
--- a/gbe_trb_ecp3/media/gbe_med_fifo.vhd
+++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd
@@ -538,32 +538,6 @@ begin
     
     CHANNEL_ACTIVE_GEN : if ((LINK_MODE(i) = c_IS_SLAVE) or (LINK_MODE(i) = c_IS_MASTER)) generate
 
---      THE_TX_PARSER: entity parser
---      port map(
---        CLK           => MASTER_CLK_IN,
---        RESET         => CLEAR,
---        --
---        PHY_D_IN      => sd_tx_data_src(i * 8 + 7 downto i * 8),
---        PHY_K_IN      => sd_tx_kcntl_src(i),
---        --
---        UNKNOWN_OUT   => unknown_tx_int(i),
---        IDLE_OUT      => idle_tx_int(i),
---        CFG_OUT       => cfg_tx_int(i)
---      );
---
---      THE_RX_PARSER: entity parser
---      port map(
---        CLK           => sd_rx_clk(i),
---        RESET         => CLEAR,
---        --
---        PHY_D_IN      => sd_rx_data_dst(i * 8 + 7 downto i * 8),
---        PHY_K_IN      => sd_rx_kcntl_dst(i),
---        --
---        UNKNOWN_OUT   => unknown_rx_int(i),
---        IDLE_OUT      => idle_rx_int(i),
---        CFG_OUT       => cfg_rx_int(i)
---      );
-
       -- Debug signals, MSB to LSB
       DEBUG_OUT(i * 32 + 31) <= '0'; -- (31)
       DEBUG_OUT(i * 32 + 30) <= '0'; -- (30)
@@ -620,8 +594,6 @@ begin
         STATE_OUT         => main_rx_state(i * 4 + 3 downto i * 4) --open
       );
 
-      -- BUG, WAP_REQUESTED_IN to be replaced by wap_requested_i()
---      is_wap_zero(i) <= '1' when (wa_position_i(i * 4 + 3 downto i * 4) = WAP_REQUESTED_IN) else '0';
       is_wap_zero(i) <= '1' when (wa_position_i(i * 4 + 3 downto i * 4) = wap_requested_i(i * 4 + 3 downto i * 4)) else '0';
 
       -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
@@ -691,7 +663,7 @@ begin
       -- SGMII core
       SGMII_GBE_PCS : sgmii_gbe_pcs42
       port map(
-        rst_n                   => RESET_N,
+        rst_n                   => CLEAR_N, --RESET_N, -- CHECKIFWORKS
         signal_detect           => serdes_active(i),
         gbe_mode                => '1',
         sgmii_mode              => '0',
@@ -735,7 +707,7 @@ begin
         mr_an_complete          => mr_an_complete_i(i), --open,
         mr_page_rx              => mr_page_rx_i(i), --open,
         mr_lp_adv_ability       => open,
-        mr_main_reset           => RESET, --CLEAR,
+        mr_main_reset           => CLEAR, --RESET, -- CHECKIFWORKS
         mr_an_enable            => serdes_active(i), --link_rx_ready(i), --'1',
         mr_restart_an           => an_restart_i(i), --'0',
         mr_adv_ability          => x"0020"
@@ -748,7 +720,7 @@ begin
         hclk            => MASTER_CLK_IN,
         txmac_clk       => MASTER_CLK_IN,
         rxmac_clk       => MASTER_CLK_IN,
-        reset_n         => RESET_N,
+        reset_n         => CLEAR_N, --RESET_N, -- CHECKIFWORKS
       ------------------- Input signals to the GMII ----------------
         rxd             => pcs_rxd(i * 8 + 7 downto i * 8),
         rx_dv           => pcs_rx_en(i),
@@ -800,14 +772,14 @@ begin
       TSMAC_CONTROLLER : trb_net16_gbe_mac_control
       port map(
         CLK                 => MASTER_CLK_IN,
-        RESET               => RESET, 
+        RESET               => CLEAR, --RESET, -- CHECKIFWORKS 
       -- signals to/from main controller
         MC_TSMAC_READY_OUT  => mac_ready_conf(i),
         MC_RECONF_IN        => mac_reconf(i),
         MC_GBE_EN_IN        => '1',
-        MC_RX_DISCARD_FCS   => '0',
+--        MC_RX_DISCARD_FCS   => '0',
         MC_PROMISC_IN       => '1',
-        MC_MAC_ADDR_IN      => (others => '0'),
+--        MC_MAC_ADDR_IN      => (others => '0'),
       -- signal to/from Host interface of TriSpeed MAC
         TSM_HADDR_OUT       => tsm_haddr(i * 8 + 7 downto i * 8),
         TSM_HDATA_OUT       => tsm_hdata(i * 8 + 7 downto i * 8),
@@ -824,7 +796,7 @@ begin
       THE_FW_GBE_LSM: entity gbe_lsm
       port map(
         CLK                  => MASTER_CLK_IN,
-        RESET                => RESET,
+        RESET                => CLEAR, --RESET, -- CHECKIFWORKS
         SERDES_ACTIVE_IN     => serdes_active(i),
         AN_COMPLETE_IN       => an_link_ok_i(i),
         MAC_READY_CONF_IN    => mac_ready_conf(i),
@@ -838,7 +810,7 @@ begin
       THE_FW_RB: entity rx_rb 
       port map(
         CLK                 => MASTER_CLK_IN,
-        RESET               => RESET,
+        RESET               => CLEAR, --RESET, -- CHECKIFWORKS
         -- MAC interface (RX)
         MAC_RX_DATA_IN      => mac_rx_data(i * 8 + 7 downto i * 8),
         MAC_RX_WR_IN        => mac_rx_wr(i),
@@ -859,7 +831,7 @@ begin
       THE_FW_FIFO: entity tx_fifo
       port map(
         CLK               => MASTER_CLK_IN,
-        RESET             => RESET,
+        RESET             => CLEAR, --RESET, -- CHECKIFWORKS
         -- MAC interface
         MAC_TX_DATA_OUT   => mac_tx_data(i * 8 + 7 downto i * 8),
         MAC_TX_READ_IN    => mac_tx_read(i),