added timeout counter for cfg flash

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index 65fd8dd7f096745bb28d0f073bcf776adfd1fc42..fcb1a46ef7b163f835b702ccb39caf7c0240e091 100644 (file)
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -53,7 +53,8 @@ use work.trb_net_std.all;
 entity generic_flash_ctrl is
   generic (MASTER_STARTPAGE : std_logic_vector(12 downto 0) := "1" & x"C00";
            USE_OLD_13BIT_MODE : integer := c_NO;
-           DATA_BUS_WIDTH   : integer := 16
+           DATA_BUS_WIDTH   : integer := 16;
+           CFG_FLASH_DISABLE_COUNTER_WIDTH   : integer := 32 --42sec@100MHz
            );
   port(
     CLK_l : in  std_logic; --local clock
@@ -144,6 +145,7 @@ architecture arch of generic_flash_ctrl is
   signal spi_ram_addr_i  : std_logic_vector(3 downto 0);
   
   signal enable_cfg_flash : std_logic_vector(2 downto 0);
+  signal cfg_flash_disable_counter : std_logic_vector(CFG_FLASH_DISABLE_COUNTER_WIDTH downto 0);
   signal testreg : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
   signal memreg  : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
   signal burst_counter : std_logic_vector(3 downto 0);
@@ -307,6 +309,19 @@ PROC_SELECTOR : process begin
   if (clean_master_start_reg = '1') then
     master_start_reg <= '0';
   end if;
+
+  if enable_cfg_flash(2 downto 0) = "000" then
+    cfg_flash_disable_counter <= (others => '0');
+  elsif enable_cfg_flash(2 downto 0) = "001" and cfg_flash_disable_counter(CFG_FLASH_DISABLE_COUNTER_WIDTH) = '1' then
+    --timeout
+    enable_cfg_flash(2 downto 0) <= "000";
+  elsif enable_cfg_flash(2 downto 0) = "001" then
+    cfg_flash_disable_counter <= std_logic_vector(unsigned(cfg_flash_disable_counter)+1);
+  end if;
+
+  if master_start_reg = '1' and master_readback = '1' then
+    enable_cfg_flash(2 downto 0) <= "000";
+  end if;
   
   if (SPI_WRITE_IN = '1') then
     if (SPI_ADDR_IN(7 downto 4) = x"4") then
@@ -314,6 +329,7 @@ PROC_SELECTOR : process begin
       spi_ram_write_i <= '1';
       spi_ram_data_i  <= SPI_DATA_IN(7 downto 0);
       spi_ram_addr_i  <= SPI_ADDR_IN(3 downto 0);
+      cfg_flash_disable_counter <= (others => '0');
     elsif (SPI_ADDR_IN(7 downto 0) = x"5B") then
       master_start_reg <= SPI_DATA_IN(0);
       master_readback  <= SPI_DATA_IN(1);
@@ -454,6 +470,7 @@ PROC_SELECTOR : process begin
   
   if (SPI_READ_IN = '1') then    
     if (SPI_ADDR_IN(7 downto 4) = x"4" and burst_counter = "0000" and out_delay = "000") then
+      cfg_flash_disable_counter <= (others => '0');
       reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');
       out_delay <= "001";
       reg_LOC_READ_OUT  <= '0';