tdcv_1.5.1 additions

diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index ea899e3407b7893914b881d0adeb5967f330d3d1..6f45278c903c5b45afff204bd785516726eab5bf 100644 (file)
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -55,7 +55,8 @@ package trb3_components is
   component TDC is
     generic (
       CHANNEL_NUMBER : integer range 2 to 65;
-      CONTROL_REG_NR : integer range 0 to 6);
+      CONTROL_REG_NR : integer range 0 to 6;
+      TDC_VERSION    : std_logic_vector(10 downto 0));
     port (
       RESET                 : in  std_logic;
       CLK_TDC               : in  std_logic;
@@ -227,7 +228,8 @@ package trb3_components is
 
   component Readout is
     generic (
-      CHANNEL_NUMBER : integer range 2 to 65);
+      CHANNEL_NUMBER : integer range 2 to 65;
+      TDC_VERSION    : std_logic_vector(10 downto 0));
     port (
       CLK_200                  : in  std_logic;
       RESET_200                : in  std_logic;
@@ -269,6 +271,26 @@ package trb3_components is
       READOUT_DEBUG            : out std_logic_vector(31 downto 0));
   end component Readout;
 
+  component TriggerHandler is
+    generic (
+      TRIGGER_NUM            : integer;
+      PHYSICAL_EVENT_TRG_NUM : integer);
+    port (
+      CLK_TRG                 : in  std_logic;
+      CLK_RDO                 : in  std_logic;
+      CLK_TDC                 : in  std_logic;
+      RESET_TRG               : in  std_logic;
+      RESET_RDO               : in  std_logic;
+      RESET_TDC               : in  std_logic;
+      TRIGGER_IN              : in  std_logic_vector(TRIGGER_NUM-1 downto 0);
+      TRIGGER_RDO_OUT         : out std_logic_vector(TRIGGER_NUM-1 downto 0);
+      TRIGGER_TDC_OUT         : out std_logic_vector(TRIGGER_NUM-1 downto 0);
+      TRIGGER_WIN_EN_IN       : in  std_logic;
+      TRIGGER_WIN_POST_IN     : in  unsigned(10 downto 0);
+      TRIGGER_WIN_END_RDO_OUT : out std_logic;
+      TRIGGER_WIN_END_TDC_OUT : out std_logic);
+  end component TriggerHandler;
+  
   component LogicAnalyser
     generic (
       CHANNEL_NUMBER : integer range 2 to 65);

diff --git a/tdc_releases/ReleaseNotes.txt b/tdc_releases/ReleaseNotes.txt
index 152edd84a3aae973a6f3fb3f2a22869f775e0773..b93a86670a96c2d76b3ba707fcd9e9db2d9657ae 100644 (file)
--- a/tdc_releases/ReleaseNotes.txt
+++ b/tdc_releases/ReleaseNotes.txt
@@ -9,7 +9,8 @@ tdc_v1.5.2*     06.05.2013      Epoch counter bug fix (data word - epoch word
 
 tdc_v1.5.1     20.06.2013      Efficiency bug fix (epoch counter update - hit
                                at the same time). Hit level bit bug fix for
-                               the web server.
+                               the web server. Reference Channel coarse
+                               counter alignmet fix.
 
 tdc_v1.5       03.05.2013      TDC calibration trigger is implemented in
                                order to shoot every channel with sufficient #

diff --git a/tdc_releases/tdc_v1.5.1/Readout.vhd b/tdc_releases/tdc_v1.5.1/Readout.vhd
index c2dfbd65de711326c494db56cb34f702cae78e9e..561be5c2d03e29b09ba37377779c16dda1654b9e 100644 (file)
--- a/tdc_releases/tdc_v1.5.1/Readout.vhd
+++ b/tdc_releases/tdc_v1.5.1/Readout.vhd
@@ -5,7 +5,7 @@
 -- File       : Readout.vhd
 -- Author     : cugur@gsi.de
 -- Created    : 2012-10-25
--- Last update: 2013-06-27
+-- Last update: 2013-07-03
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -23,7 +23,8 @@ use work.trb3_components.all;
 
 entity Readout is
   generic (
-    CHANNEL_NUMBER : integer range 2 to 65);
+    CHANNEL_NUMBER : integer range 2 to 65;
+    TDC_VERSION    : std_logic_vector(10 downto 0));
 
   port (
     CLK_200           : in std_logic;
@@ -925,8 +926,9 @@ begin  -- behavioral
   STATUS_REGISTERS_BUS_OUT(0)(7 downto 4)    <= wr_fsm_debug;
   STATUS_REGISTERS_BUS_OUT(0)(15 downto 8)   <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8));
   STATUS_REGISTERS_BUS_OUT(0)(16)            <= REFERENCE_TIME when rising_edge(CLK_100);
-  STATUS_REGISTERS_BUS_OUT(0)(27 downto 17)  <= (others => '0');
+  STATUS_REGISTERS_BUS_OUT(0)(27 downto 17)  <= TDC_VERSION;
   STATUS_REGISTERS_BUS_OUT(0)(31 downto 28)  <= TRG_TYPE_IN    when rising_edge(CLK_100);
+  
   STATUS_REGISTERS_BUS_OUT(1)                <= slow_control_ch_empty_i(31 downto 0);
   STATUS_REGISTERS_BUS_OUT(2)                <= slow_control_ch_empty_i(63 downto 32);
   STATUS_REGISTERS_BUS_OUT(3)(10 downto 0)   <= TRG_WIN_PRE;

diff --git a/tdc_releases/tdc_v1.5.1/TDC.vhd b/tdc_releases/tdc_v1.5.1/TDC.vhd
index 304329009687ca49c34fe4533ce2f6c36fe166ee..260e3402226924b5ffb0b5f4c3320fdd0a09f33b 100644 (file)
--- a/tdc_releases/tdc_v1.5.1/TDC.vhd
+++ b/tdc_releases/tdc_v1.5.1/TDC.vhd
@@ -12,7 +12,8 @@ use work.version.all;
 entity TDC is
   generic (
     CHANNEL_NUMBER : integer range 2 to 65;
-    CONTROL_REG_NR : integer range 0 to 6);
+    CONTROL_REG_NR : integer range 0 to 6;
+    TDC_VERSION    : std_logic_vector(10 downto 0));
   port (
     RESET                 : in  std_logic;
     CLK_TDC               : in  std_logic;
@@ -266,7 +267,8 @@ begin
   -- Readout
   TheReadout : Readout
     generic map (
-      CHANNEL_NUMBER => CHANNEL_NUMBER)
+      CHANNEL_NUMBER => CHANNEL_NUMBER,
+      TDC_VERSION    => TDC_VERSION)
     port map (
       CLK_200                  => CLK_TDC,
       RESET_200                => reset_tdc,

diff --git a/tdc_releases/tdc_v1.5.1/trb3_periph.vhd b/tdc_releases/tdc_v1.5.1/trb3_periph.vhd
index 3d7e3bc136ed80bf5ac496b39dfcbf9419330876..442a26df7b16b9e7dceae0035ed2e601f1e83d3c 100644 (file)
--- a/tdc_releases/tdc_v1.5.1/trb3_periph.vhd
+++ b/tdc_releases/tdc_v1.5.1/trb3_periph.vhd
@@ -720,14 +720,15 @@ begin
 
   THE_TDC : TDC
     generic map (
-      CHANNEL_NUMBER => 5,              -- Number of TDC channels
-      CONTROL_REG_NR => 5)  -- Number of control regs - higher than 8 check tdc_ctrl_addr
+      CHANNEL_NUMBER => 65,             -- Number of TDC channels
+      CONTROL_REG_NR => 5,  -- Number of control regs - higher than 8 check tdc_ctrl_addr
+      TDC_VERSION    => "001" & x"51")  -- TDC version number
     port map (
       RESET                 => reset_i,
       CLK_TDC               => CLK_PCLK_LEFT,  -- Clock used for the time measurement
       CLK_READOUT           => clk_100_i,   -- Clock for the readout
-      REFERENCE_TIME        => timing_trg_received_i,   -- Reference time input
-      HIT_IN                => hit_in_i(4 downto 1),  -- Channel start signals
+      REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
+      HIT_IN                => hit_in_i(64 downto 1),  -- Channel start signals
       HIT_CALIBRATION       => clk_20_i,    -- Hits for calibrating the TDC
       TRG_WIN_PRE           => tdc_ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST          => tdc_ctrl_reg(58 downto 48),  -- Post-Trigger window width
@@ -794,8 +795,8 @@ begin
       CONTROL_REG_IN        => tdc_ctrl_reg);
 
   -- For single edge measurements
-  --hit_in_i <= INP;
-  hit_in_i <= (others => timing_trg_received_i);
+  hit_in_i <= INP;    
+  --hit_in_i <= (others => timing_trg_received_i);
 
   ---- For ToT Measurements
   --Gen_Hit_In_Signals : for i in 1 to 32 generate