component TDC is
generic (
CHANNEL_NUMBER : integer range 2 to 65;
- CONTROL_REG_NR : integer range 0 to 6);
+ CONTROL_REG_NR : integer range 0 to 6;
+ TDC_VERSION : std_logic_vector(10 downto 0));
port (
RESET : in std_logic;
CLK_TDC : in std_logic;
component Readout is
generic (
- CHANNEL_NUMBER : integer range 2 to 65);
+ CHANNEL_NUMBER : integer range 2 to 65;
+ TDC_VERSION : std_logic_vector(10 downto 0));
port (
CLK_200 : in std_logic;
RESET_200 : in std_logic;
READOUT_DEBUG : out std_logic_vector(31 downto 0));
end component Readout;
+ component TriggerHandler is
+ generic (
+ TRIGGER_NUM : integer;
+ PHYSICAL_EVENT_TRG_NUM : integer);
+ port (
+ CLK_TRG : in std_logic;
+ CLK_RDO : in std_logic;
+ CLK_TDC : in std_logic;
+ RESET_TRG : in std_logic;
+ RESET_RDO : in std_logic;
+ RESET_TDC : in std_logic;
+ TRIGGER_IN : in std_logic_vector(TRIGGER_NUM-1 downto 0);
+ TRIGGER_RDO_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0);
+ TRIGGER_TDC_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0);
+ TRIGGER_WIN_EN_IN : in std_logic;
+ TRIGGER_WIN_POST_IN : in unsigned(10 downto 0);
+ TRIGGER_WIN_END_RDO_OUT : out std_logic;
+ TRIGGER_WIN_END_TDC_OUT : out std_logic);
+ end component TriggerHandler;
+
component LogicAnalyser
generic (
CHANNEL_NUMBER : integer range 2 to 65);
tdc_v1.5.1 20.06.2013 Efficiency bug fix (epoch counter update - hit
at the same time). Hit level bit bug fix for
- the web server.
+ the web server. Reference Channel coarse
+ counter alignmet fix.
tdc_v1.5 03.05.2013 TDC calibration trigger is implemented in
order to shoot every channel with sufficient #
-- File : Readout.vhd
-- Author : cugur@gsi.de
-- Created : 2012-10-25
--- Last update: 2013-06-27
+-- Last update: 2013-07-03
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
entity Readout is
generic (
- CHANNEL_NUMBER : integer range 2 to 65);
+ CHANNEL_NUMBER : integer range 2 to 65;
+ TDC_VERSION : std_logic_vector(10 downto 0));
port (
CLK_200 : in std_logic;
STATUS_REGISTERS_BUS_OUT(0)(7 downto 4) <= wr_fsm_debug;
STATUS_REGISTERS_BUS_OUT(0)(15 downto 8) <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8));
STATUS_REGISTERS_BUS_OUT(0)(16) <= REFERENCE_TIME when rising_edge(CLK_100);
- STATUS_REGISTERS_BUS_OUT(0)(27 downto 17) <= (others => '0');
+ STATUS_REGISTERS_BUS_OUT(0)(27 downto 17) <= TDC_VERSION;
STATUS_REGISTERS_BUS_OUT(0)(31 downto 28) <= TRG_TYPE_IN when rising_edge(CLK_100);
+
STATUS_REGISTERS_BUS_OUT(1) <= slow_control_ch_empty_i(31 downto 0);
STATUS_REGISTERS_BUS_OUT(2) <= slow_control_ch_empty_i(63 downto 32);
STATUS_REGISTERS_BUS_OUT(3)(10 downto 0) <= TRG_WIN_PRE;
entity TDC is
generic (
CHANNEL_NUMBER : integer range 2 to 65;
- CONTROL_REG_NR : integer range 0 to 6);
+ CONTROL_REG_NR : integer range 0 to 6;
+ TDC_VERSION : std_logic_vector(10 downto 0));
port (
RESET : in std_logic;
CLK_TDC : in std_logic;
-- Readout
TheReadout : Readout
generic map (
- CHANNEL_NUMBER => CHANNEL_NUMBER)
+ CHANNEL_NUMBER => CHANNEL_NUMBER,
+ TDC_VERSION => TDC_VERSION)
port map (
CLK_200 => CLK_TDC,
RESET_200 => reset_tdc,
THE_TDC : TDC
generic map (
- CHANNEL_NUMBER => 5, -- Number of TDC channels
- CONTROL_REG_NR => 5) -- Number of control regs - higher than 8 check tdc_ctrl_addr
+ CHANNEL_NUMBER => 65, -- Number of TDC channels
+ CONTROL_REG_NR => 5, -- Number of control regs - higher than 8 check tdc_ctrl_addr
+ TDC_VERSION => "001" & x"51") -- TDC version number
port map (
RESET => reset_i,
CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement
CLK_READOUT => clk_100_i, -- Clock for the readout
- REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => hit_in_i(4 downto 1), -- Channel start signals
+ REFERENCE_TIME => timing_trg_received_i, -- Reference time input
+ HIT_IN => hit_in_i(64 downto 1), -- Channel start signals
HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC
TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
CONTROL_REG_IN => tdc_ctrl_reg);
-- For single edge measurements
- --hit_in_i <= INP;
- hit_in_i <= (others => timing_trg_received_i);
+ hit_in_i <= INP;
+ --hit_in_i <= (others => timing_trg_received_i);
---- For ToT Measurements
--Gen_Hit_In_Signals : for i in 1 to 32 generate