--- /dev/null
+LOCATE COMP "THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_4_DOWN2/THE_SERDES/PCSD_INST" SITE "PCSC" ;
+
+REGION "MEDIA_DOWN1" "R102C40D" 13 100;
+LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_DOWN1" ;
+
+LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
+
+
+
+MULTICYCLE TO CELL "THE_MEDIA_4_DOW*/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_MEDIA_4_DOW*/sci*" 20 ns;
+MULTICYCLE TO CELL "THE_MEDIA_4_DOW*/PROC_SCI_CTRL.wa*" 20 ns;
+BLOCK PATH TO CLKNET "THE_MEDIA_4_DOW*/sci_write_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOW*/sci_write_i";
+BLOCK PATH TO CLKNET "THE_MEDIA_4_DOW*/sci_read_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOW*/sci_read_i";
+MULTICYCLE TO CLKNET "THE_MEDIA_4_DOW*/sci_read_i" 15 ns;
+MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOW*/sci_read_i" 15 ns;
+MULTICYCLE TO CLKNET "THE_MEDIA_4_DOW*/sci_write_i" 15 ns;
+MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOW*/sci_write_i" 15 ns;
+
+
+
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns;
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns;
+BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
+BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
+MULTICYCLE TO CLKNET "THE_MEDIA_INTERFACE/sci_read_i" 15 ns;
+MULTICYCLE FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i" 15 ns;
+MULTICYCLE TO CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns;
+MULTICYCLE FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns;
+
+MULTICYCLE TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
+MAXDELAY TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
+
+#
+# #GbE Part
+# UGROUP "tsmac"
+# BLKNAME GBE/imp_gen.MAC
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SGMII_GBE_PCS
+# BLKNAME GBE/rx_enable_gen.FRAME_RECEIVER
+# BLKNAME GBE/FRAME_TRANSMITTER;
+# UGROUP "controllers"
+# BLKNAME GBE/main_gen.MAIN_CONTROL
+# BLKNAME GBE/rx_enable_gen.RECEIVE_CONTROLLER
+# BLKNAME GBE/transmit_gen.TRANSMIT_CONTROLLER;
+# UGROUP "gbe_rx_tx"
+# BLKNAME GBE/FRAME_CONSTRUCTOR
+# BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG
+# BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR
+# BLKNAME GBE/setup_imp_gen.SETUP;
+#
+# #REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE;
+# #REGION "MED0" "R81C30D" 34 40 DEVSIZE;
+# #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;
+# #REGION "GBE_MAIN_REGION" "R50C64C" 65 64 DEVSIZE;
+# #LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;
+# #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ;
+#
+# UGROUP "sd_tx_to_pcs"
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[0]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[1]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[2]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[3]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[4]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[5]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[6]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[7]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q;
+# UGROUP "sd_rx_to_pcs"
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[0]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[1]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[2]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[3]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[4]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[5]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[6]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[7]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q;
+# UGROUP "pcs_tx_to_mac"
+# BLKNAME GBE/pcs_tx_en_q
+# BLKNAME GBE/pcs_tx_en_qq
+# BLKNAME GBE/pcs_tx_er_q
+# BLKNAME GBE/pcs_tx_er_qq
+# BLKNAME GBE/pcs_txd_q[0]
+# BLKNAME GBE/pcs_txd_q[1]
+# BLKNAME GBE/pcs_txd_q[2]
+# BLKNAME GBE/pcs_txd_q[3]
+# BLKNAME GBE/pcs_txd_q[4]
+# BLKNAME GBE/pcs_txd_q[5]
+# BLKNAME GBE/pcs_txd_q[6]
+# BLKNAME GBE/pcs_txd_q[7]
+# BLKNAME GBE/pcs_txd_qq[0]
+# BLKNAME GBE/pcs_txd_qq[1]
+# BLKNAME GBE/pcs_txd_qq[2]
+# BLKNAME GBE/pcs_txd_qq[3]
+# BLKNAME GBE/pcs_txd_qq[4]
+# BLKNAME GBE/pcs_txd_qq[5]
+# BLKNAME GBE/pcs_txd_qq[6]
+# BLKNAME GBE/pcs_txd_qq[7];
+# UGROUP "pcs_rx_to_mac"
+# BLKNAME GBE/pcs_rx_en_q
+# BLKNAME GBE/pcs_rx_en_qq
+# BLKNAME GBE/pcs_rx_er_q
+# BLKNAME GBE/pcs_rx_er_qq
+# BLKNAME GBE/pcs_rxd_q[0]
+# BLKNAME GBE/pcs_rxd_q[1]
+# BLKNAME GBE/pcs_rxd_q[2]
+# BLKNAME GBE/pcs_rxd_q[3]
+# BLKNAME GBE/pcs_rxd_q[4]
+# BLKNAME GBE/pcs_rxd_q[5]
+# BLKNAME GBE/pcs_rxd_q[6]
+# BLKNAME GBE/pcs_rxd_q[7]
+# BLKNAME GBE/pcs_rxd_qq[0]
+# BLKNAME GBE/pcs_rxd_qq[1]
+# BLKNAME GBE/pcs_rxd_qq[2]
+# BLKNAME GBE/pcs_rxd_qq[3]
+# BLKNAME GBE/pcs_rxd_qq[4]
+# BLKNAME GBE/pcs_rxd_qq[5]
+# BLKNAME GBE/pcs_rxd_qq[6]
+# BLKNAME GBE/pcs_rxd_qq[7];
+#
+# UGROUP "GBE_SERDES_group" BBOX 10 67
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES;
+# LOCATE UGROUP "GBE_SERDES_group" SITE "R105C17D" ;
+#
+# MAXDELAY NET "GBE/pcs_rx_e?_q" 1.500000 nS ;
+# MAXDELAY NET "GBE/pcs_rxd_q[?]" 1.500000 nS ;
+#
+# DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q"
+# "GBE/pcs_rx_er_q"
+# "GBE/pcs_rxd_q*";
+# INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ;
+#
+# PRIORITIZE NET "GBE/pcs_rx_en_q" 100 ;
+# PRIORITIZE NET "GBE/pcs_rx_er_q" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[1]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[2]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[3]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[4]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[5]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
+# PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ;
\ No newline at end of file
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN1156C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "combiner"
+set_option -resource_sharing false
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/combiner.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
+add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4_slave3.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd"
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+#Hub
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
+
+#
+##GbE
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+#
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd"
+#
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+
+
+
+add_file -vhdl -lib work "./combiner.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.trb_net16_hub_func.all;
+use work.trb_net_gbe_components.all;
+use work.med_sync_define.all;
+
+entity combiner is
+ port(
+ CLOCK_PCLK : in std_logic;
+ CLOCK_PLL : in std_logic;
+
+ TRIGGER_IN : in std_logic;
+ TRIGGER_OUT : out std_logic;
+ TRIGGER_TO_CTS : out std_logic;
+
+ --Additional IO
+ HDR_IO : inout std_logic_vector(10 downto 1);
+ RJ_CLOCK : inout std_logic_vector( 3 downto 0); --1 not available here
+ RJ_TRIG : inout std_logic_vector( 2 downto 1); --0,3 not available here
+ POWER_BOARD_IO : inout std_logic_vector( 3 downto 0);
+
+ --Lines to slaves
+ BACK_MASTER_READY : out std_logic_vector(11 downto 0); --sig_1
+ BACK_SLAVE_READY : in std_logic_vector(11 downto 0); --sig_2
+ BACK_TRIG1 : in std_logic_vector(11 downto 0); --sig_3
+ BACK_TRIG2 : in std_logic_vector(11 downto 0); --sig_4
+ BACK_LDO_EN : out std_logic_vector(11 downto 0); --en_ldo
+ BACK_SPARE : inout std_logic_vector(11 downto 0); --sig_5
+
+ --LED
+ LED_GREEN : out std_logic;
+ LED_YELLOW : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_RJ_GREEN : out std_logic_vector( 1 downto 0); --0: clock, 1:trigger
+ LED_RJ_RED : out std_logic_vector( 1 downto 0);
+ LED_SFP_GREEN : out std_logic;
+ LED_SFP_RED : out std_logic;
+
+ --SFP
+ SFP_LOS : in std_logic;
+ SFP_MOD0 : in std_logic;
+ SFP_MOD1 : inout std_logic := 'Z';
+ SFP_MOD2 : inout std_logic := 'Z';
+ SFP_TX_DIS : out std_logic := '0';
+
+ --Switch
+ CLOCK_SELECT_IN : in std_logic;
+ TRIGG_SEL_OUT : out std_logic_vector( 1 downto 0);
+
+ --ADC
+ ADC_CLK : out std_logic;
+ ADC_CS : out std_logic;
+ ADC_DIN : out std_logic;
+ ADC_DOUT : in std_logic;
+
+ --Flash, 1-wire, Reload
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_IN : out std_logic;
+ FLASH_OUT : in std_logic;
+ PROGRAMN : out std_logic;
+ TEMPSENS : inout std_logic;
+ POWER_GOOD : in std_logic;
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(32 downto 0)
+ );
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_IN : signal is true;
+ attribute syn_useioff of FLASH_OUT : signal is true;
+
+end entity;
+
+architecture arch of combiner is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ signal clk_sys, clk_full, clk_full_osc : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal clear_i : std_logic;
+
+ signal time_counter : unsigned(31 downto 0) := (others => '0');
+ signal led : std_logic_vector(1 downto 0);
+ signal debug_clock_reset : std_logic_vector(31 downto 0);
+
+ --Media Interface
+ signal med2int : med2int_array_t(0 to INTERFACE_NUM-1);
+ signal int2med : int2med_array_t(0 to INTERFACE_NUM-1);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+
+ signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in : CTRLBUS_TX;
+
+ signal bussci_tx : ctrlbus_tx_array_t(0 to 3);
+ signal bussci_rx : ctrlbus_rx_array_t(0 to 3);
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal sed_error_i : std_logic;
+ signal bus_master_active : std_logic;
+
+ signal uart_tx, uart_rx : std_logic;
+
+ signal timer : TIMERS;
+ signal lcd_data : std_logic_vector(511 downto 0);
+
+ signal trig_gen_out_i : std_logic_vector(1 downto 0);
+ signal monitor_inputs_i : std_logic_vector(25 downto 0);
+
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+
+ signal med_dataready_out : std_logic_vector (INTERFACE_NUM-1 downto 0);
+ signal med_data_out : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0);
+ signal med_read_in : std_logic_vector (INTERFACE_NUM-1 downto 0);
+ signal med_dataready_in : std_logic_vector (INTERFACE_NUM-1 downto 0);
+ signal med_data_in : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0);
+ signal med_read_out : std_logic_vector (INTERFACE_NUM-1 downto 0);
+ signal med_stat_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0);
+ signal rdack, wrack : std_logic;
+
+
+begin
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+THE_CLOCK_RESET : entity work.clock_reset_handler
+ port map(
+ INT_CLK_IN => CLOCK_PCLK,
+ EXT_CLK_IN => '0',
+ NET_CLK_FULL_IN => med2int(0).clk_full,
+ NET_CLK_HALF_IN => med2int(0).clk_half,
+ RESET_FROM_NET => med2int(0).stat_op(13),
+
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+
+ RESET_OUT => reset_i,
+ CLEAR_OUT => clear_i,
+ GSR_OUT => GSR_N,
+
+ FULL_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ REF_CLK_OUT => clk_full_osc,
+
+ ENPIRION_CLOCK => open,
+ LED_RED_OUT => open,
+ LED_GREEN_OUT => open,
+ DEBUG_OUT => debug_clock_reset
+ );
+
+---------------------------------------------------------------------------
+-- TrbNet Uplink
+---------------------------------------------------------------------------
+
+THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
+ generic map(
+ SERDES_NUM => 0,
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ CLK_REF_FULL => med2int(0).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN => SFP_MOD0,
+ SD_LOS_IN => SFP_LOS,
+ SD_TXDIS_OUT => SFP_TX_DIS,
+ --Control Interface
+ BUS_RX => bussci_rx(0),
+ BUS_TX => bussci_tx(0),
+ -- Status and control port
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- TrbNet Downlink
+---------------------------------------------------------------------------
+
+gen_media_interfaces : for i in 0 to 2 generate
+ THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4
+ generic map(
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES,c_YES,c_YES,c_YES)
+ )
+ port map(
+ CLK_REF_FULL => med2int(0).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+
+ --Internal Connection
+ MEDIA_MED2INT => med2int(i*4+1 to i*4+4),
+ MEDIA_INT2MED => int2med(i*4+1 to i*4+4),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN => BACK_SLAVE_READY(i*4+3 downto i*4),
+ SD_LOS_IN => BACK_SLAVE_READY(i*4+3 downto i*4),
+ SD_TXDIS_OUT => BACK_MASTER_READY(i*4+3 downto i*4),
+
+ --Control Interface
+ BUS_RX => bussci_rx(i+1),
+ BUS_TX => bussci_tx(i+1),
+
+ -- Status and control port
+ STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+end generate;
+
+---------------------------------------------------------------------------
+-- Hub
+---------------------------------------------------------------------------
+
+THE_HUB : trb_net16_hub_base
+ generic map (
+ HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),
+ IBUF_SECURE_MODE => c_YES,
+ MII_NUMBER => INTERFACE_NUM,
+ MII_IS_UPLINK => MII_IS_UPLINK,
+ MII_IS_DOWNLINK => MII_IS_DOWNLINK,
+ MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY,
+ INT_NUMBER => 0,
+ USE_ONEWIRE => c_YES,
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+ HARDWARE_VERSION => HARDWARE_INFO,
+ INIT_ENDPOINT_ID => x"0000",
+ INIT_ADDRESS => INIT_ADDRESS,
+ USE_VAR_ENDPOINT_ID => c_NO,
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
+ )
+ port map (
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ --Media interfacces
+ MED_DATAREADY_OUT(13*1-1 downto 0) => med_dataready_out,
+ MED_DATA_OUT(13*16-1 downto 0) => med_data_out,
+ MED_PACKET_NUM_OUT(13*3-1 downto 0) => med_packet_num_out,
+ MED_READ_IN(13*1-1 downto 0) => med_read_in,
+ MED_DATAREADY_IN(13*1-1 downto 0) => med_dataready_in,
+ MED_DATA_IN(13*16-1 downto 0) => med_data_in,
+ MED_PACKET_NUM_IN(13*3-1 downto 0) => med_packet_num_in,
+ MED_READ_OUT(13*1-1 downto 0) => med_read_out,
+ MED_STAT_OP(13*16-1 downto 0) => med_stat_op,
+ MED_CTRL_OP(13*16-1 downto 0) => med_ctrl_op,
+
+ COMMON_STAT_REGS => common_stat_reg,
+ COMMON_CTRL_REGS => common_ctrl_reg,
+ MY_ADDRESS_OUT => timer.network_address,
+ UNIQUE_ID_OUT => timer.uid,
+ TEMPERATURE_OUT => timer.temperature,
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT => ctrlbus_rx.addr,
+ REGIO_READ_ENABLE_OUT => ctrlbus_rx.read,
+ REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write,
+ REGIO_DATA_OUT => ctrlbus_rx.data,
+ REGIO_DATA_IN => ctrlbus_tx.data,
+ REGIO_DATAREADY_IN => rdack,
+ REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack,
+ REGIO_WRITE_ACK_IN => wrack,
+ REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown,
+ REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout,
+
+ TIMER_TICKS_OUT(0) => timer.tick_us,
+ TIMER_TICKS_OUT(1) => timer.tick_ms,
+ ONEWIRE => TEMPSENS,
+ --Status ports (for debugging)
+ MPLEX_CTRL => (others => '0'),
+ CTRL_DEBUG => (others => '0'),
+ STAT_DEBUG => open
+ );
+
+
+gen_media_record : for i in 0 to INTERFACE_NUM-1 generate
+ med_data_in(i*16+15 downto i*16) <= med2int(i).data;
+ med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num;
+ med_dataready_in(i) <= med2int(i).dataready;
+ med_read_in(i) <= med2int(i).tx_read;
+ med_stat_op(i*16+15 downto i*16) <= med2int(i).stat_op;
+
+ int2med(i).data <= med_data_out(i*16+15 downto i*16);
+ int2med(i).packet_num <= med_packet_num_out(i*3+2 downto i*3);
+ int2med(i).dataready <= med_dataready_out(i);
+ int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16);
+end generate;
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 6,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ REGIO_RX => handlerbus_rx,
+ REGIO_TX => ctrlbus_tx,
+
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bustc_rx, --Clock switch
+ BUS_RX(2) => bussci_rx(0), --SCI Serdes
+ BUS_RX(3) => bussci_rx(1),
+ BUS_RX(4) => bussci_rx(2),
+ BUS_RX(5) => bussci_rx(3),
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bustc_tx,
+ BUS_TX(2) => bussci_tx(0),
+ BUS_TX(3) => bussci_tx(1),
+ BUS_TX(4) => bussci_tx(2),
+ BUS_TX(5) => bussci_tx(3),
+ STAT_DEBUG => open
+ );
+
+ handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;
+
+---------------------------------------------------------------------------
+-- Control Tools
+---------------------------------------------------------------------------
+ THE_TOOLS: entity work.trb3sc_tools
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ --Flash & Reload
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_OUT,
+ FLASH_OUT => FLASH_IN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+ SPI_CS_OUT => open,
+ SPI_MOSI_OUT=> open,
+ SPI_MISO_IN => open,
+ SPI_CLK_OUT => open,
+ --Header
+ HEADER_IO => HDR_IO,
+ --LCD
+ LCD_DATA_IN => lcd_data,
+ --ADC
+ ADC_CS => ADC_CS,
+ ADC_MOSI => ADC_DIN,
+ ADC_MISO => ADC_DOUT,
+ ADC_CLK => ADC_CLK,
+ --Trigger & Monitor
+ MONITOR_INPUTS => monitor_inputs_i(25 downto 0),
+ TRIG_GEN_INPUTS => monitor_inputs_i(23 downto 0),
+ TRIG_GEN_OUTPUTS => trig_gen_out_i,
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => ctrlbus_tx,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
+ );
+
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
+ LED_GREEN <= debug_clock_reset(0);
+ LED_ORANGE <= debug_clock_reset(1);
+ LED_RED <= not sed_error_i;
+ LED_YELLOW <= debug_clock_reset(2);
+
+ LED_SFP_GREEN <= not med2int(0).stat_op(9); --SFP Link Status
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); --SFP RX/TX
+
+ LED_RJ_GREEN <= CLOCK_SELECT_IN & TRIGG_SEL_OUT(0);
+ LED_RJ_RED <= reset_i & TRIGG_SEL_OUT(1);
+
+---------------------------------------------------------------------------
+-- LCD Data to display
+---------------------------------------------------------------------------
+ lcd_data(15 downto 0) <= timer.network_address;
+ lcd_data(47 downto 16) <= timer.microsecond;
+ lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32));
+ lcd_data(91 downto 80) <= timer.temperature;
+ lcd_data(95 downto 92) <= x"0";
+ lcd_data(159 downto 96) <= timer.uid;
+ lcd_data(511 downto 160) <= (others => '0');
+
+---------------------------------------------------------------------------
+-- Monitoring & Trigger
+---------------------------------------------------------------------------
+
+ TRIGGER_OUT <= trig_gen_out_i(0);
+
+ monitor_inputs_i(11 downto 0) <= BACK_TRIG1;
+ monitor_inputs_i(23 downto 12) <= BACK_TRIG2;
+ monitor_inputs_i(25 downto 24) <= trig_gen_out_i(1 downto 0);
+
+
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ process begin
+ wait until rising_edge(clk_sys);
+ time_counter <= time_counter + 1;
+ if reset_i = '1' then
+ time_counter <= (others => '0');
+ end if;
+ end process;
+
+
+-- TEST_LINE <= med_stat_debug(15 downto 0);
+
+end architecture;
+
+
+
--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+ constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
+ constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)?
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F3DC";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"52";
+
+
+ constant INCLUDE_UART : integer := c_YES;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_LCD : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_YES;
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
+ constant INCLUDE_STATISTICS : integer := c_YES;
+ constant TRIG_GEN_INPUT_NUM : integer := 24;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 2;
+ constant MONITOR_INPUT_NUM : integer := 26;
+
+ constant INCLUDE_GBE : integer := c_NO;
+
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (
+ x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+ x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+
+ x"54", x"72", x"62", x"33", x"73", x"63", x"0a",
+ x"0a",
+ x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a",
+ x"55", x"49", x"44", x"20", x"20", x"89", x"88", x"87", x"86", x"0a",
+ x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a",
+ x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a",
+ x"54", x"65", x"6d", x"70", x"65", x"72", x"61", x"74", x"75", x"72", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"85", x"0a",
+ others => x"00");
+
+
+
+
+ constant INTERFACE_NUM : integer := 13;
+ constant MII_IS_UPLINK : hub_mii_config_t := (1, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0);
+ constant MII_IS_DOWNLINK : hub_mii_config_t := (0, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0);
+ constant MII_IS_UPLINK_ONLY : hub_mii_config_t := (1, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0);
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"97000000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+-- t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1));
+ t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE
+ t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
+ t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet
+ t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+TOPNAME => "combiner",
+lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@jspc29",
+lattice_path => '/d/jspc29/lattice/diamond/3.6_x64',
+synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
+synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+
+nodelist_file => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+#pinout_file => '', #name of pin-out file, if not equal TOPNAME
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+
--- /dev/null
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 28
+-c 1
+-e 2
+#-g guidefile.ncd
+#-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
TOPNAME => "dirich",
-lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
-lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@jspc29",
lattice_path => '/d/jspc29/lattice/diamond/3.6_x64',
synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
#Report settings
firefox_open => 0,
twr_number_of_errors => 20,
-
+no_ltxt2ptxt => 1, #if there is no serdes being used
<BaliProject version="3.2" title="dirich" device="LFE5UM-85F-8BG381C" default_implementation="project">
<Options/>
<Implementation title="project" dir="project" description="project" synthesis="synplify" default_strategy="Strategy1">
- <Options def_top="lattice_ecp3_fifo_18x16_dualport_oreg" top="dirich"/>
+ <Options def_top="med_ecp5_sfp_sync" top="dirich"/>
<Source name="../workdir/version.vhd" type="VHDL" type_short="VHDL">
<Options lib="work"/>
</Source>
<Source name="../../code/pwm_generator.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/med_sync_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/sci_reader.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/tx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../workdir/dirich.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0_softlogic.v"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
PWM : out std_logic_vector(32 downto 1);
--Additional IO
- SIG : inout std_logic_vector( 6 downto 1);
+ SIG : inout std_logic_vector( 5 downto 1);
+ --1:master ready, 2: slave ready, 3-4 trigger, 5 spare
--LED
LED_GREEN : out std_logic;
LED_YELLOW : out std_logic;
signal timer : TIMERS;
signal lcd_data : std_logic_vector(511 downto 0);
signal hdr_io : std_logic_vector(9 downto 0);
+ signal led_off : std_logic;
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
-- TrbNet Uplink
---------------------------------------------------------------------------
--- THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync
--- generic map(
--- SERDES_NUM => 0,
--- IS_SYNC_SLAVE => c_YES
--- )
--- port map(
--- CLK_REF_FULL => med2int(0).clk_full,
--- CLK_INTERNAL_FULL => clk_full_osc,
--- SYSCLK => clk_sys,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- --Internal Connection
--- MEDIA_MED2INT => med2int(0),
--- MEDIA_INT2MED => int2med(0),
---
--- --Sync operation
--- RX_DLM => open,
--- RX_DLM_WORD => open,
--- TX_DLM => open,
--- TX_DLM_WORD => open,
---
--- --SFP Connection
--- SD_PRSNT_N_IN => link_stat_in,
--- SD_LOS_IN => link_stat_in,
--- SD_TXDIS_OUT => link_stat_out,
--- --Control Interface
--- BUS_RX => bussci_rx,
--- BUS_TX => bussci_tx,
--- -- Status and control port
--- STAT_DEBUG => med_stat_debug(63 downto 0),
--- CTRL_DEBUG => open
--- );
-
-SIG(2) <= '0' when link_stat_out = '1' else 'Z';
+ THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync
+ generic map(
+ SERDES_NUM => 0,
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ CLK_REF_FULL => med2int(0).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN => link_stat_in,
+ SD_LOS_IN => link_stat_in,
+ SD_TXDIS_OUT => link_stat_out,
+ --Control Interface
+ BUS_RX => bussci_rx,
+ BUS_TX => bussci_tx,
+ -- Status and control port
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+SIG(2) <= '1' when link_stat_out = '1' else '0';
link_stat_in <= SIG(1);
---------------------------------------------------------------------------
SPI_CLK_OUT => open,
--Header
HEADER_IO => hdr_io,
+ LED_DISABLE => led_off,
--LCD
LCD_DATA_IN => lcd_data,
--ADC
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
- LED_GREEN <= '0';
- LED_ORANGE <= '0';
- LED_RED <= '0';
- LED_YELLOW <= '0';
+ LED_GREEN <= '0' or led_off;
+ LED_ORANGE <= '0' or led_off;
+ LED_RED <= '0' or led_off;
+ LED_YELLOW <= '0' or led_off;
---------------------------------------------------------------------------
-- Test Circuits
jspc29 / dirich.git / commitdiff