Commenting duplicate declaration of FIFO_DC_36x32_OutReg/FIFO_DC_36x16_OutReg

diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index 5631286b4d2ad2f9769e966517a48f25f3e1629e..f77ea693cd780b725a218bff16aebb6338c9c20d 100644 (file)
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -521,8 +521,8 @@ package trb3_components is
       Empty      : out std_logic;
       Full       : out std_logic;
       AlmostFull : out std_logic);
-  end component FIFO_DC_36x32_OutReg;
-
+  end component;
+  
   component FIFO_DC_36x16_OutReg is
     port (
       Data       : in  std_logic_vector(35 downto 0);
@@ -536,7 +536,7 @@ package trb3_components is
       Empty      : out std_logic;
       Full       : out std_logic;
       AlmostFull : out std_logic);
-  end component FIFO_DC_36x16_OutReg;
+  end component;  
 
   component FIFO_36x128_OutReg_Counter is
     port (
@@ -553,35 +553,35 @@ package trb3_components is
       Full    : out std_logic);
   end component FIFO_36x128_OutReg_Counter;
 
-  component FIFO_DC_36x32_OutReg is
-    port (
-      Data       : in  std_logic_vector(35 downto 0);
-      WrClock    : in  std_logic;
-      RdClock    : in  std_logic;
-      WrEn       : in  std_logic;
-      RdEn       : in  std_logic;
-      Reset      : in  std_logic;
-      RPReset    : in  std_logic;
-      Q          : out std_logic_vector(35 downto 0);
-      Empty      : out std_logic;
-      Full       : out std_logic;
-      AlmostFull : out std_logic);
-  end component;
-  
-  component FIFO_DC_36x16_OutReg is
-    port (
-      Data       : in  std_logic_vector(35 downto 0);
-      WrClock    : in  std_logic;
-      RdClock    : in  std_logic;
-      WrEn       : in  std_logic;
-      RdEn       : in  std_logic;
-      Reset      : in  std_logic;
-      RPReset    : in  std_logic;
-      Q          : out std_logic_vector(35 downto 0);
-      Empty      : out std_logic;
-      Full       : out std_logic;
-      AlmostFull : out std_logic);
-  end component;  
+--  component FIFO_DC_36x32_OutReg is
+--    port (
+--      Data       : in  std_logic_vector(35 downto 0);
+--      WrClock    : in  std_logic;
+--      RdClock    : in  std_logic;
+--      WrEn       : in  std_logic;
+--      RdEn       : in  std_logic;
+--      Reset      : in  std_logic;
+--      RPReset    : in  std_logic;
+--      Q          : out std_logic_vector(35 downto 0);
+--      Empty      : out std_logic;
+--      Full       : out std_logic;
+--      AlmostFull : out std_logic);
+--  end component;
+--  
+--  component FIFO_DC_36x16_OutReg is
+--    port (
+--      Data       : in  std_logic_vector(35 downto 0);
+--      WrClock    : in  std_logic;
+--      RdClock    : in  std_logic;
+--      WrEn       : in  std_logic;
+--      RdEn       : in  std_logic;
+--      Reset      : in  std_logic;
+--      RPReset    : in  std_logic;
+--      Q          : out std_logic_vector(35 downto 0);
+--      Empty      : out std_logic;
+--      Full       : out std_logic;
+--      AlmostFull : out std_logic);
+--  end component;  
   
   --component FIFO_24x2_OutReg
   --  port (