update to TRB3sc files

diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd
index 2e63d232a1ae893c18474e8fa4633bd36750b337..4f504b27f990ae28b86d06e02882222e7a9bf7f0 100644 (file)
--- a/code/clock_reset_handler.vhd
+++ b/code/clock_reset_handler.vhd
@@ -27,6 +27,7 @@ entity clock_reset_handler is
     SYS_CLK_OUT     : out std_logic;  -- 100/120 MHz for FPGA fabric
     REF_CLK_OUT     : out std_logic;  -- 200/240 internal reference clock
     
+    ENPIRION_CLOCK  : out std_logic;
     LED_RED_OUT     : out std_logic_vector( 1 downto 0);
     LED_GREEN_OUT   : out std_logic_vector( 1 downto 0);
     DEBUG_OUT       : out std_logic_vector(31 downto 0)
@@ -98,7 +99,7 @@ end generate;
 ---------------------------------------------------------------------------
 gen_norecov_clock : if USE_RXCLOCK = c_NO generate
 
-  clk_selected_ref <= clk_selected_full;
+  clk_selected_ref <= clk_selected_full; --clk_int_full; --
   
   ---------------------------------------------------------------------------
   -- Make internal clock 200 MHz if required
@@ -107,17 +108,19 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate
     THE_INT_PLL : entity work.pll_in240_out200
       port map(
         CLK    => INT_CLK_IN,
-        CLKOP  => clk_int_full,
-        CLKOK  => clk_int_half,
+        CLKOP  => open,         --200
+        CLKOS  => clk_int_full, --same as OP, but for DCS
+        CLKOK  => clk_int_half, --100
         LOCK   => pll_int_lock
         );
 
-    THE_EXT_PLL : pll_in200_out100
+    THE_EXT_PLL : entity work.pll_in200_out100
       port map(
         CLK    => EXT_CLK_IN,
         RESET  => '0',
-        CLKOP  => clk_ext_half,
-        CLKOK  => clk_ext_full,
+        CLKOP  => open,         --100
+        CLKOS  => clk_ext_half, --same as OP, but for DCS
+        CLKOK  => clk_ext_full, --200, bypassed
         LOCK   => pll_ext_lock
         );        
   end generate;
@@ -201,12 +204,31 @@ THE_RESET_HANDLER : trb_net_reset_handler
     DEBUG_OUT       => open
   );  
 
+  
+  
+---------------------------------------------------------------------------
+-- Slow clock for DCDC converters
+---------------------------------------------------------------------------  
+  PLL_ENPIRION : entity work.pll_200_4
+    port map(
+      CLK   => clk_selected_ref,
+      RESET => reset_i,
+      CLKOP => ENPIRION_CLOCK,
+      LOCK  => open
+      );  
+  
 
 DEBUG_OUT(0)  <= pll_int_lock;
 DEBUG_OUT(1)  <= pll_ext_lock;
 DEBUG_OUT(2)  <= clock_select;
 DEBUG_OUT(3)  <= clear_n_i;
 DEBUG_OUT(31 downto 4) <= (others => '0');
+
+BUS_TX.data <= (others => '0');
+BUS_TX.unknown <= '1';
+BUS_TX.ack <= '0';
+BUS_TX.nack <= '0';
+
   
 
 end architecture;
\ No newline at end of file

diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd
index 67dd1afeb6060db790d74526994ebb78fb41b770..981e11dd4d5c683aebe771e602e5fd7320d3b529 100644 (file)
--- a/code/trb3sc_tools.vhd
+++ b/code/trb3sc_tools.vhd
@@ -39,7 +39,7 @@ entity trb3sc_tools is
     
     --SED
     SED_ERROR_OUT : out std_logic;
-    
+   
     --Slowcontrol
     BUS_RX     : in  CTRLBUS_RX;
     BUS_TX     : out CTRLBUS_TX;
@@ -129,6 +129,11 @@ begin
 ---------------------------------------------------------------------------
 -- ADC
 ---------------------------------------------------------------------------      
+  busadc_tx.unknown <= '1';
+  busadc_tx.nack    <= '0';
+  busadc_tx.ack     <= '0';
+  busadc_tx.data    <= (others => '0');
+
 
 
 ---------------------------------------------------------------------------
@@ -158,6 +163,7 @@ begin
     SPI_MOSI_OUT <= (others => spi_sdo);
     spi_sdi      <= or_all(SPI_MISO_IN and not spi_cs);
   end generate;
+  busspi_tx.unknown <= '0';
 
 ---------------------------------------------------------------------------
 -- UART

diff --git a/cores/pll_in200_out100.ipx b/cores/pll_in200_out100.ipx
new file mode 100644 (file)
index 0000000..ac5b6bb
--- /dev/null
+++ b/cores/pll_in200_out100.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in200_out100" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 06 22 13:35:48.176" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+               <File name="pll_in200_out100.lpc" type="lpc" modified="2015 06 22 13:35:46.000"/>
+               <File name="pll_in200_out100.vhd" type="top_level_vhdl" modified="2015 06 22 13:35:46.000"/>
+               <File name="pll_in200_out100_tmpl.vhd" type="template_vhdl" modified="2015 06 22 13:35:46.000"/>
+  </Package>
+</DiamondModule>

diff --git a/cores/pll_in200_out100.lpc b/cores/pll_in200_out100.lpc
new file mode 100644 (file)
index 0000000..45875bb
--- /dev/null
+++ b/cores/pll_in200_out100.lpc
@@ -0,0 +1,69 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.7
+ModuleName=pll_in200_out100
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=06/22/2015
+Time=13:35:46
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=2
+ClkOPBp=0
+Post=8
+U_OFrq=100
+OP_Tol=0.0
+OFrq=100.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=Internal
+Mult=1
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=200.000000
+ClkRst=0
+PCDR=1
+FINDELA=0
+VcoRate=
+Bandwidth=1.485393
+;DelayControl=No
+EnCLKOS=1
+ClkOSBp=0
+EnCLKOK=1
+ClkOKBp=1
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in200_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypassk -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -fclkok 200 -fclkok_tol 0.0 -use_rst -noclkok2 -bw

diff --git a/cores/pll_in200_out100.vhd b/cores/pll_in200_out100.vhd
new file mode 100644 (file)
index 0000000..6b13e2f
--- /dev/null
+++ b/cores/pll_in200_out100.vhd
@@ -0,0 +1,108 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.7
+--/d/jspc29/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypassk -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -fclkok 200 -fclkok_tol 0.0 -use_rst -noclkok2 -bw 
+
+-- Mon Jun 22 13:35:46 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in200_out100 is
+    port (
+        CLK: in std_logic; 
+        RESET: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOS: out std_logic; 
+        CLKOK: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in200_out100 : entity is true;
+end pll_in200_out100;
+
+architecture Structure of pll_in200_out100 is
+
+    -- internal signal declarations
+    signal CLKOS_t: std_logic;
+    signal CLKOP_t: std_logic;
+    signal CLKFB_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOK : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000";
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "100.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "200.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "ENABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  8, CLKFB_DIV=>  1, CLKI_DIV=>  2, 
+        FIN=> "200.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>RESET, RSTK=>scuba_vlo, 
+            WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, 
+            DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, 
+            DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, 
+            FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, 
+            FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, 
+            CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>CLKFB_t);
+
+    CLKOS <= CLKOS_t;
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in200_out100 is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on

diff --git a/cores/pll_in240_out200.ipx b/cores/pll_in240_out200.ipx
index db362ae68f079aedd80246ded32f73aa3f6c4f15..364fb634ddf7c73043eccbfb3248ab3cdb11d406 100644 (file)
--- a/cores/pll_in240_out200.ipx
+++ b/cores/pll_in240_out200.ipx
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_in240_out200" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 05 28 17:38:00.123" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="pll_in240_out200" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 06 22 13:33:31.162" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-               <File name="pll_in240_out200.lpc" type="lpc" modified="2015 05 28 17:37:56.000"/>
-               <File name="pll_in240_out200.vhd" type="top_level_vhdl" modified="2015 05 28 17:37:56.000"/>
-               <File name="pll_in240_out200_tmpl.vhd" type="template_vhdl" modified="2015 05 28 17:37:56.000"/>
+               <File name="pll_in240_out200.lpc" type="lpc" modified="2015 06 22 13:33:26.000"/>
+               <File name="pll_in240_out200.vhd" type="top_level_vhdl" modified="2015 06 22 13:33:26.000"/>
+               <File name="pll_in240_out200_tmpl.vhd" type="template_vhdl" modified="2015 06 22 13:33:26.000"/>
   </Package>
 </DiamondModule>

diff --git a/cores/pll_in240_out200.lpc b/cores/pll_in240_out200.lpc
index 6bc1647f2c336449ae52c4fd28eb4352d2c40a5a..038692f00c282aff4af3a34b541222a3f77bed82 100644 (file)
--- a/cores/pll_in240_out200.lpc
+++ b/cores/pll_in240_out200.lpc
@@ -16,8 +16,8 @@ CoreRevision=5.7
 ModuleName=pll_in240_out200
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=05/28/2015
-Time=17:37:56
+Date=06/22/2015
+Time=13:33:26
 
 [Parameters]
 Verilog=0
@@ -59,11 +59,11 @@ FINDELA=0
 VcoRate=
 Bandwidth=1.753251
 ;DelayControl=No
-EnCLKOS=0
+EnCLKOS=1
 ClkOSBp=0
 EnCLKOK=1
 ClkOKBp=0
 enClkOK2=0
 
 [Command]
-cmd_line= -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw
+cmd_line= -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw

diff --git a/cores/pll_in240_out200.vhd b/cores/pll_in240_out200.vhd
index f765bca8a231bc711d257ca400b393167171b367..b848e19681f44918848063aa827b06ef223605aa 100644 (file)
--- a/cores/pll_in240_out200.vhd
+++ b/cores/pll_in240_out200.vhd
@@ -1,8 +1,8 @@
 -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
 -- Module  Version: 5.7
---/d/jspc29/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw 
+--/d/jspc29/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw 
 
--- Thu May 28 17:37:56 2015
+-- Mon Jun 22 13:33:26 2015
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -15,6 +15,7 @@ entity pll_in240_out200 is
     port (
         CLK: in std_logic; 
         CLKOP: out std_logic; 
+        CLKOS: out std_logic; 
         CLKOK: out std_logic; 
         LOCK: out std_logic);
  attribute dont_touch : boolean;
@@ -24,6 +25,7 @@ end pll_in240_out200;
 architecture Structure of pll_in240_out200 is
 
     -- internal signal declarations
+    signal CLKOS_t: std_logic;
     signal CLKOP_t: std_logic;
     signal scuba_vlo: std_logic;
 
@@ -53,9 +55,11 @@ architecture Structure of pll_in240_out200 is
         port (Z: out std_logic);
     end component;
     attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
     attribute FREQUENCY_PIN_CLKI : string; 
     attribute FREQUENCY_PIN_CLKOK : string; 
     attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
     attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "240.000000";
     attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "100.000000";
     attribute syn_keep : boolean;
@@ -84,9 +88,10 @@ begin
             DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
             DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
             FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
-            CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, 
+            CLKOS=>CLKOS_t, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, 
             CLKINTFB=>open);
 
+    CLKOS <= CLKOS_t;
     CLKOP <= CLKOP_t;
 end Structure;
 

diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf
index 671f71a2cb9ea9b7cb5c04dedf06adb0e3e12052..2973a224e25498557168214480a070cc8190e386 100644 (file)
--- a/pinout/basic_constraints.lpf
+++ b/pinout/basic_constraints.lpf
@@ -33,12 +33,31 @@ GSR_NET NET "GSR_N";
 
 MULTICYCLE TO CELL   "THE_MEDIA_INTERFACE/sci*" 20 ns;
 MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns;
-MULTICYCLE TO CELL   "THE_MEDIA_INTERFACE/SCI_DATA_OUT*" 20 ns;
 MULTICYCLE TO CELL   "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET   "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.sci_write_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.sci_write_i";
+BLOCK PATH TO   CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
+BLOCK PATH TO   CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
+
+# PROHIBIT PRIMARY   NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
+PROHIBIT PRIMARY   NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
+PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
+FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps 
+FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps 
+
+REGION "REGION_SPI" "R19C150D" 20 20 DEVSIZE;
+LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
+LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
 
 LOCATE COMP          "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ;
-REGION               "MEDIA_UPLINK" "R102C95D" 13 25;
+REGION               "MEDIA_UPLINK" "R102C55D" 13 50;
 LOCATE UGROUP        "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_UPLINK" ;
 
+BLOCK PATH TO   PORT "LED*";
+BLOCK PATH TO   PORT "SFP*";
+BLOCK PATH FROM PORT "SFP*";
+BLOCK PATH TO   PORT "PROGRAMN";
+BLOCK PATH TO   PORT "TEMPSENS";
+BLOCK PATH FROM PORT "TEMPSENS";
+BLOCK PATH TO   PORT "TESTLINE";

diff --git a/pinout/trb3sc_basic.lpf b/pinout/trb3sc_basic.lpf
index 970f47f2884e8ea293589497aa5746c13952976c..2f5c5e3670b3a44a051e2906a61c1c6b39e71f31 100644 (file)
--- a/pinout/trb3sc_basic.lpf
+++ b/pinout/trb3sc_basic.lpf
@@ -62,184 +62,184 @@ IOBUF GROUP  "BACK_3V3_group" IO_TYPE=LVTTL33 PULLMODE=DOWN;
 #################################################################\r
 # AddOn Connector\r
 #################################################################\r
-# LOCATE COMP "DQLL0_0_N"                      SITE "AA1";\r
-# LOCATE COMP "DQLL0_1_N"                      SITE "AB1";\r
-# LOCATE COMP "DQLL0_2_N"                      SITE "AA3";\r
-# LOCATE COMP "DQLL0_3_N"                      SITE "AB5";\r
-# LOCATE COMP "DQLL0_4_N"                      SITE "AA7";\r
-# LOCATE COMP "DQLL1_0_N"                      SITE "Y1";\r
-# LOCATE COMP "DQLL1_1_N"                      SITE "W3";\r
-# LOCATE COMP "DQLL1_2_N"                      SITE "W1";\r
-# LOCATE COMP "DQLL1_3_N"                      SITE "W9";\r
-# LOCATE COMP "DQLL1_4_N"                      SITE "AA8";\r
-# LOCATE COMP "DQLL2_0_N"                      SITE "AC4";\r
-# LOCATE COMP "DQLL2_1_N"                      SITE "AC1";\r
-# LOCATE COMP "DQLL2_2_N"                      SITE "AB3";\r
-# LOCATE COMP "DQLL2_3_N"                      SITE "AB8";\r
-# LOCATE COMP "DQLL2_4_N"                      SITE "AB6";\r
-# LOCATE COMP "DQLL3_0_N"                      SITE "AE3";\r
-# LOCATE COMP "DQLL3_1_N"                      SITE "AC10"\r
-# LOCATE COMP "DQLL3_2_N"                      SITE "AE1";\r
-# LOCATE COMP "DQLL3_3_N"                      SITE "AD3";\r
-# LOCATE COMP "DQLL3_4_N"                      SITE "AC8";\r
-# LOCATE COMP "DQLR0_0_N"                      SITE "AB33"\r
-# LOCATE COMP "DQLR0_1_N"                      SITE "AA26"\r
-# LOCATE COMP "DQLR0_2_N"                      SITE "AC33"\r
-# LOCATE COMP "DQLR0_3_N"                      SITE "AA30"\r
-# LOCATE COMP "DQLR0_4_N"                      SITE "AA27"\r
-# LOCATE COMP "DQLR1_0_N"                      SITE "AD30"\r
-# LOCATE COMP "DQLR1_1_N"                      SITE "AB31"\r
-# LOCATE COMP "DQLR1_2_N"                      SITE "AE33"\r
-# LOCATE COMP "DQLR1_3_N"                      SITE "AD34"\r
-# LOCATE COMP "DQLR1_4_N"                      SITE "AG34"\r
-# LOCATE COMP "DQLR2_0_N"                      SITE "W29";\r
-# LOCATE COMP "DQLR2_1_N"                      SITE "W26";\r
-# LOCATE COMP "DQLR2_2_N"                      SITE "W33";;\r
-# LOCATE COMP "DQLR2_3_N"                      SITE "Y33";;\r
-# LOCATE COMP "DQLR2_4_N"                      SITE "Y25";\r
-# LOCATE COMP "DQSLL0_C"                       SITE "AB9";\r
-# LOCATE COMP "DQSLL1_C"                       SITE "Y6";\r
-# LOCATE COMP "DQSLL2_C"                       SITE "AE5";\r
-# LOCATE COMP "DQSLL3_C"                       SITE "AK1";\r
-# LOCATE COMP "DQSLR0_C"                       SITE "AC30"\r
-# LOCATE COMP "DQSLR1_C"                       SITE "AB25";\r
-# LOCATE COMP "DQSLR2_C"                       SITE "AA29";\r
-# LOCATE COMP "DQSUL0_C"                       SITE "M9";;\r
-# LOCATE COMP "DQSUL1_C"                       SITE "L9";;\r
-# LOCATE COMP "DQSUL2_C"                       SITE "H3";;\r
-# LOCATE COMP "DQSUL3_C"                       SITE "N10";;\r
-# LOCATE COMP "DQSUR0_C"                       SITE "M27";;\r
-# LOCATE COMP "DQSUR1_C"                       SITE "N28";;\r
-# LOCATE COMP "DQSUR2_C"                       SITE "U30";;\r
-# LOCATE COMP "DQUL0_0_N"                      SITE "L4";;\r
-# LOCATE COMP "DQUL0_1_N"                      SITE "M3";;\r
-# LOCATE COMP "DQUL0_2_N"                      SITE "K5";;\r
-# LOCATE COMP "DQUL0_3_N"                      SITE "M1";;\r
-# LOCATE COMP "DQUL0_4_N"                      SITE "L6";;\r
-# LOCATE COMP "DQUL1_0_N"                      SITE "L1";;\r
-# LOCATE COMP "DQUL1_1_N"                      SITE "K1";;\r
-# LOCATE COMP "DQUL1_2_N"                      SITE "K3";;\r
-# LOCATE COMP "DQUL1_3_N"                      SITE "L7";;\r
-# LOCATE COMP "DQUL1_4_N"                      SITE "J6";;\r
-# LOCATE COMP "DQUL2_0_N"                      SITE "F1";;\r
-# LOCATE COMP "DQUL2_1_N"                      SITE "E3";\r
-# LOCATE COMP "DQUL2_2_N"                      SITE "G1";\r
-# LOCATE COMP "DQUL2_3_N"                      SITE "J1";\r
-# LOCATE COMP "DQUL2_4_N"                      SITE "H2";\r
-# LOCATE COMP "DQUL3_0_N"                      SITE "N3";\r
-# LOCATE COMP "DQUL3_1_N"                      SITE "N1";\r
-# LOCATE COMP "DQUL3_2_N"                      SITE "N5";\r
-# LOCATE COMP "DQUL3_3_N"                      SITE "P4";\r
-# LOCATE COMP "DQUL3_4_N"                      SITE "P8";\r
-# LOCATE COMP "DQUR0_0_N"                      SITE "M25";\r
-# LOCATE COMP "DQUR0_1_N"                      SITE "L31";\r
-# LOCATE COMP "DQUR0_2_N"                      SITE "L33";;\r
-# LOCATE COMP "DQUR0_3_N"                      SITE "K30";\r
-# LOCATE COMP "DQUR0_4_N"                      SITE "K33";\r
-# LOCATE COMP "DQUR1_0_N"                      SITE "N29";\r
-# LOCATE COMP "DQUR1_1_N"                      SITE "P26";\r
-# LOCATE COMP "DQUR1_2_N"                      SITE "N31";\r
-# LOCATE COMP "DQUR1_3_N"                      SITE "N33";\r
-# LOCATE COMP "DQUR1_4_N"                      SITE "P27";;\r
-# LOCATE COMP "DQUR2_0_N"                      SITE "T31";;\r
-# LOCATE COMP "DQUR2_1_N"                      SITE "T27";;\r
-# LOCATE COMP "DQUR2_2_N"                      SITE "U31";;\r
-# LOCATE COMP "DQUR2_3_N"                      SITE "T33";;\r
-# LOCATE COMP "DQUR2_4_N"                      SITE "U27";\r
-\r
-LOCATE COMP "DQLL0_0"                      SITE "AA2";    #was "DQLL0_0_P" 1\r
-LOCATE COMP "DQLL0_1"                      SITE "AB2";    #was "DQLL0_1_P" 5\r
-LOCATE COMP "DQLL0_2"                      SITE "AA4";    #was "DQLL0_2_P" 9\r
-LOCATE COMP "DQSLL0"                       SITE "AA10";   #was "DQSLL0_T"  13\r
-LOCATE COMP "DQLL0_3"                      SITE "AA5";    #was "DQLL0_3_P" 17\r
-LOCATE COMP "DQLL0_4"                      SITE "Y7";     #was "DQLL0_4_P" 21\r
-LOCATE COMP "DQLL2_0"                      SITE "AC5";    #was "DQLL2_0_P" 25\r
-LOCATE COMP "DQLL2_1"                      SITE "AC2";    #was "DQLL2_1_P" 29\r
-LOCATE COMP "DQLL2_2"                      SITE "AB4";    #was "DQLL2_2_P" 33\r
-LOCATE COMP "DQSLL2"                       SITE "AD5";    #was "DQSLL2_T"  37\r
-LOCATE COMP "DQLL2_3"                      SITE "AA9";    #was "DQLL2_3_P" 41\r
-LOCATE COMP "DQLL2_4"                      SITE "AB7";    #was "DQLL2_4_P" 45\r
-LOCATE COMP "DQUL3_0"                      SITE "N4";     #was "DQUL3_0_P" 49\r
-LOCATE COMP "DQUL3_1"                      SITE "N2";     #was "DQUL3_1_P" 53\r
-LOCATE COMP "DQUL3_2"                      SITE "M5";     #was "DQUL3_2_P" 57\r
-LOCATE COMP "DQSUL3"                       SITE "M10";    #was "DQSUL3_T"  61\r
-LOCATE COMP "DQUL3_3"                      SITE "P5";     #was "DQUL3_3_P" 65\r
-LOCATE COMP "DQUL3_4"                      SITE "N8";     #was "DQUL3_4_P" 69\r
-LOCATE COMP "DQUL1_0"                      SITE "L2";     #was "DQUL1_0_P" 73\r
-LOCATE COMP "DQUL1_1"                      SITE "K2";     #was "DQUL1_1_P" 77\r
-LOCATE COMP "DQUL1_2"                      SITE "K4";     #was "DQUL1_2_P" 81\r
-LOCATE COMP "DQSUL1"                       SITE "L10";    #was "DQSUL1_T"  85\r
-LOCATE COMP "DQUL1_3"                      SITE "M8";     #was "DQUL1_3_P" 89\r
-LOCATE COMP "DQUL1_4"                      SITE "K7";     #was "DQUL1_4_P" 93\r
-\r
-LOCATE COMP "DQUR0_0"                      SITE "L26";    #was "DQUR0_0_P" 105\r
-LOCATE COMP "DQUR0_1"                      SITE "L32";    #was "DQUR0_1_P" 109\r
-LOCATE COMP "DQSUR0"                       SITE "M26";    #was "DQSUR0_T"  113\r
-LOCATE COMP "DQUR0_2"                      SITE "L34";    #was "DQUR0_2_P" 117\r
-LOCATE COMP "DQUR0_3"                      SITE "K29";    #was "DQUR0_3_P" 121\r
-LOCATE COMP "DQUR0_4"                      SITE "K34";    #was "DQUR0_4_P" 125\r
-LOCATE COMP "DQLR0_0"                      SITE "AB34";   #was "DQLR0_0_P" 129\r
-LOCATE COMP "DQLR0_1"                      SITE "AA25";   #was "DQLR0_1_P" 133\r
-LOCATE COMP "DQLR0_2"                      SITE "AC34";   #was "DQLR0_2_P" 137\r
-LOCATE COMP "DQSLR0"                       SITE "AB30";   #was "DQSLR0_T"  141\r
-LOCATE COMP "DQLR0_3"                      SITE "AA31";   #was "DQLR0_3_P" 145\r
-LOCATE COMP "DQLR0_4"                      SITE "AA28";   #was "DQLR0_4_P" 149\r
-\r
-LOCATE COMP "DQLR1_0"                      SITE "AD31";   #was "DQLR1_0_P" 169\r
-LOCATE COMP "DQLR1_1"                      SITE "AB32";   #was "DQLR1_1_P" 173\r
-LOCATE COMP "DQLR1_2"                      SITE "AE34";   #was "DQLR1_2_P" 177\r
-LOCATE COMP "DQSLR1"                       SITE "AB26";   #was "DQSLR1_T"  181\r
-LOCATE COMP "DQLR1_3"                      SITE "AD33";   #was "DQLR1_3_P" 185\r
-LOCATE COMP "DQLR1_4"                      SITE "AF34";   #was "DQLR1_4_P" 189\r
-\r
-\r
-LOCATE COMP "DQLL3_0"                      SITE "AE4";    #was "DQLL3_0_P" 2\r
-LOCATE COMP "DQLL3_1"                      SITE "AB10";   #was "DQLL3_1_P" 6\r
-LOCATE COMP "DQLL3_2"                      SITE "AE2";    #was "DQLL3_2_P" 10\r
-LOCATE COMP "DQSLL3"                       SITE "AJ1";    #was "DQSLL3_T"  14\r
-LOCATE COMP "DQLL3_3"                      SITE "AD4";    #was "DQLL3_3_P" 18\r
-LOCATE COMP "DQLL3_4"                      SITE "AC9";    #was "DQLL3_4_P" 22\r
-LOCATE COMP "DQLL1_0"                      SITE "Y2";     #was "DQLL1_0_P" 26\r
-LOCATE COMP "DQLL1_1"                      SITE "W4";     #was "DQLL1_1_P" 30\r
-LOCATE COMP "DQLL1_2"                      SITE "W2";     #was "DQLL1_2_P" 34\r
-LOCATE COMP "DQSLL1"                       SITE "W6";     #was "DQSLL1_T"  38\r
-LOCATE COMP "DQLL1_3"                      SITE "W8";     #was "DQLL1_3_P" 42\r
-LOCATE COMP "DQLL1_4"                      SITE "Y8";     #was "DQLL1_4_P" 46\r
-LOCATE COMP "DQUL2_0"                      SITE "F2";     #was "DQUL2_0_P" 50\r
-LOCATE COMP "DQUL2_1"                      SITE "F3";     #was "DQUL2_1_P" 54\r
-LOCATE COMP "DQUL2_2"                      SITE "G2";     #was "DQUL2_2_P" 58\r
-LOCATE COMP "DQSUL2"                       SITE "G3";     #was "DQSUL2_T"  62\r
-LOCATE COMP "DQUL2_3"                      SITE "H1";     #was "DQUL2_3_P" 66\r
-LOCATE COMP "DQUL2_4"                      SITE "J3";     #was "DQUL2_4_P" 70\r
-LOCATE COMP "DQUL0_0"                      SITE "L5";     #was "DQUL0_0_P" 74\r
-LOCATE COMP "DQUL0_1"                      SITE "M4";     #was "DQUL0_1_P" 78\r
-LOCATE COMP "DQUL0_2"                      SITE "K6";     #was "DQUL0_2_P" 82\r
-LOCATE COMP "DQSUL0"                       SITE "N9";     #was "DQSUL0_T"  86\r
-LOCATE COMP "DQUL0_3"                      SITE "M2";     #was "DQUL0_3_P" 90\r
-LOCATE COMP "DQUL0_4"                      SITE "M7";     #was "DQUL0_4_P" 94\r
-\r
-LOCATE COMP "DQUR1_0"                      SITE "N30";    #was "DQUR1_0_P" 106\r
-LOCATE COMP "DQUR1_1"                      SITE "N26";    #was "DQUR1_1_P" 110\r
-LOCATE COMP "DQUR1_2"                      SITE "N32";    #was "DQUR1_2_P" 114\r
-LOCATE COMP "DQSUR1"                       SITE "N27";    #was "DQSUR1_T"  118\r
-LOCATE COMP "DQUR1_3"                      SITE "N34";    #was "DQUR1_3_P" 122\r
-LOCATE COMP "DQUR1_4"                      SITE "P28";    #was "DQUR1_4_P" 126\r
-LOCATE COMP "DQUR2_0"                      SITE "T32";    #was "DQUR2_0_P" 130\r
-LOCATE COMP "DQUR2_1"                      SITE "T26";    #was "DQUR2_1_P" 134\r
-LOCATE COMP "DQUR2_2"                      SITE "U32";    #was "DQUR2_2_P" 138\r
-LOCATE COMP "DQSUR2"                       SITE "T30";    #was "DQSUR2_T"  142\r
-LOCATE COMP "DQUR2_3"                      SITE "T34";    #was "DQUR2_3_P" 146\r
-LOCATE COMP "DQUR2_4"                      SITE "U26";    #was "DQUR2_4_P" 150\r
-\r
-LOCATE COMP "DQLR2_0"                      SITE "W30";    #was "DQLR2_0_P" 170\r
-LOCATE COMP "DQLR2_1"                      SITE "W27";    #was "DQLR2_1_P" 174\r
-LOCATE COMP "DQLR2_2"                      SITE "W34";    #was "DQLR2_2_P" 178\r
-LOCATE COMP "DQSLR2"                       SITE "Y30";    #was "DQSLR2_T"  182\r
-LOCATE COMP "DQLR2_3"                      SITE "Y34";    #was "DQLR2_3_P" 186\r
-LOCATE COMP "DQLR2_4"                      SITE "Y26";    #was "DQLR2_4_P" 190\r
-\r
-DEFINE PORT GROUP "DQ_group" "DQ*" ;\r
-IOBUF GROUP  "DQ_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; \r
+# # LOCATE COMP "DQLL0_0_N"                      SITE "AA1";\r
+# # LOCATE COMP "DQLL0_1_N"                      SITE "AB1";\r
+# # LOCATE COMP "DQLL0_2_N"                      SITE "AA3";\r
+# # LOCATE COMP "DQLL0_3_N"                      SITE "AB5";\r
+# # LOCATE COMP "DQLL0_4_N"                      SITE "AA7";\r
+# # LOCATE COMP "DQLL1_0_N"                      SITE "Y1";\r
+# # LOCATE COMP "DQLL1_1_N"                      SITE "W3";\r
+# # LOCATE COMP "DQLL1_2_N"                      SITE "W1";\r
+# # LOCATE COMP "DQLL1_3_N"                      SITE "W9";\r
+# # LOCATE COMP "DQLL1_4_N"                      SITE "AA8";\r
+# # LOCATE COMP "DQLL2_0_N"                      SITE "AC4";\r
+# # LOCATE COMP "DQLL2_1_N"                      SITE "AC1";\r
+# # LOCATE COMP "DQLL2_2_N"                      SITE "AB3";\r
+# # LOCATE COMP "DQLL2_3_N"                      SITE "AB8";\r
+# # LOCATE COMP "DQLL2_4_N"                      SITE "AB6";\r
+# # LOCATE COMP "DQLL3_0_N"                      SITE "AE3";\r
+# # LOCATE COMP "DQLL3_1_N"                      SITE "AC10"\r
+# # LOCATE COMP "DQLL3_2_N"                      SITE "AE1";\r
+# # LOCATE COMP "DQLL3_3_N"                      SITE "AD3";\r
+# # LOCATE COMP "DQLL3_4_N"                      SITE "AC8";\r
+# # LOCATE COMP "DQLR0_0_N"                      SITE "AB33"\r
+# # LOCATE COMP "DQLR0_1_N"                      SITE "AA26"\r
+# # LOCATE COMP "DQLR0_2_N"                      SITE "AC33"\r
+# # LOCATE COMP "DQLR0_3_N"                      SITE "AA30"\r
+# # LOCATE COMP "DQLR0_4_N"                      SITE "AA27"\r
+# # LOCATE COMP "DQLR1_0_N"                      SITE "AD30"\r
+# # LOCATE COMP "DQLR1_1_N"                      SITE "AB31"\r
+# # LOCATE COMP "DQLR1_2_N"                      SITE "AE33"\r
+# # LOCATE COMP "DQLR1_3_N"                      SITE "AD34"\r
+# # LOCATE COMP "DQLR1_4_N"                      SITE "AG34"\r
+# # LOCATE COMP "DQLR2_0_N"                      SITE "W29";\r
+# # LOCATE COMP "DQLR2_1_N"                      SITE "W26";\r
+# # LOCATE COMP "DQLR2_2_N"                      SITE "W33";;\r
+# # LOCATE COMP "DQLR2_3_N"                      SITE "Y33";;\r
+# # LOCATE COMP "DQLR2_4_N"                      SITE "Y25";\r
+# # LOCATE COMP "DQSLL0_C"                       SITE "AB9";\r
+# # LOCATE COMP "DQSLL1_C"                       SITE "Y6";\r
+# # LOCATE COMP "DQSLL2_C"                       SITE "AE5";\r
+# # LOCATE COMP "DQSLL3_C"                       SITE "AK1";\r
+# # LOCATE COMP "DQSLR0_C"                       SITE "AC30"\r
+# # LOCATE COMP "DQSLR1_C"                       SITE "AB25";\r
+# # LOCATE COMP "DQSLR2_C"                       SITE "AA29";\r
+# # LOCATE COMP "DQSUL0_C"                       SITE "M9";;\r
+# # LOCATE COMP "DQSUL1_C"                       SITE "L9";;\r
+# # LOCATE COMP "DQSUL2_C"                       SITE "H3";;\r
+# # LOCATE COMP "DQSUL3_C"                       SITE "N10";;\r
+# # LOCATE COMP "DQSUR0_C"                       SITE "M27";;\r
+# # LOCATE COMP "DQSUR1_C"                       SITE "N28";;\r
+# # LOCATE COMP "DQSUR2_C"                       SITE "U30";;\r
+# # LOCATE COMP "DQUL0_0_N"                      SITE "L4";;\r
+# # LOCATE COMP "DQUL0_1_N"                      SITE "M3";;\r
+# # LOCATE COMP "DQUL0_2_N"                      SITE "K5";;\r
+# # LOCATE COMP "DQUL0_3_N"                      SITE "M1";;\r
+# # LOCATE COMP "DQUL0_4_N"                      SITE "L6";;\r
+# # LOCATE COMP "DQUL1_0_N"                      SITE "L1";;\r
+# # LOCATE COMP "DQUL1_1_N"                      SITE "K1";;\r
+# # LOCATE COMP "DQUL1_2_N"                      SITE "K3";;\r
+# # LOCATE COMP "DQUL1_3_N"                      SITE "L7";;\r
+# # LOCATE COMP "DQUL1_4_N"                      SITE "J6";;\r
+# # LOCATE COMP "DQUL2_0_N"                      SITE "F1";;\r
+# # LOCATE COMP "DQUL2_1_N"                      SITE "E3";\r
+# # LOCATE COMP "DQUL2_2_N"                      SITE "G1";\r
+# # LOCATE COMP "DQUL2_3_N"                      SITE "J1";\r
+# # LOCATE COMP "DQUL2_4_N"                      SITE "H2";\r
+# # LOCATE COMP "DQUL3_0_N"                      SITE "N3";\r
+# # LOCATE COMP "DQUL3_1_N"                      SITE "N1";\r
+# # LOCATE COMP "DQUL3_2_N"                      SITE "N5";\r
+# # LOCATE COMP "DQUL3_3_N"                      SITE "P4";\r
+# # LOCATE COMP "DQUL3_4_N"                      SITE "P8";\r
+# # LOCATE COMP "DQUR0_0_N"                      SITE "M25";\r
+# # LOCATE COMP "DQUR0_1_N"                      SITE "L31";\r
+# # LOCATE COMP "DQUR0_2_N"                      SITE "L33";;\r
+# # LOCATE COMP "DQUR0_3_N"                      SITE "K30";\r
+# # LOCATE COMP "DQUR0_4_N"                      SITE "K33";\r
+# # LOCATE COMP "DQUR1_0_N"                      SITE "N29";\r
+# # LOCATE COMP "DQUR1_1_N"                      SITE "P26";\r
+# # LOCATE COMP "DQUR1_2_N"                      SITE "N31";\r
+# # LOCATE COMP "DQUR1_3_N"                      SITE "N33";\r
+# # LOCATE COMP "DQUR1_4_N"                      SITE "P27";;\r
+# # LOCATE COMP "DQUR2_0_N"                      SITE "T31";;\r
+# # LOCATE COMP "DQUR2_1_N"                      SITE "T27";;\r
+# # LOCATE COMP "DQUR2_2_N"                      SITE "U31";;\r
+# # LOCATE COMP "DQUR2_3_N"                      SITE "T33";;\r
+# # LOCATE COMP "DQUR2_4_N"                      SITE "U27";\r
+# \r
+# LOCATE COMP "DQLL0_0"                      SITE "AA2";    #was "DQLL0_0_P" 1\r
+# LOCATE COMP "DQLL0_1"                      SITE "AB2";    #was "DQLL0_1_P" 5\r
+# LOCATE COMP "DQLL0_2"                      SITE "AA4";    #was "DQLL0_2_P" 9\r
+# LOCATE COMP "DQSLL0"                       SITE "AA10";   #was "DQSLL0_T"  13\r
+# LOCATE COMP "DQLL0_3"                      SITE "AA5";    #was "DQLL0_3_P" 17\r
+# LOCATE COMP "DQLL0_4"                      SITE "Y7";     #was "DQLL0_4_P" 21\r
+# LOCATE COMP "DQLL2_0"                      SITE "AC5";    #was "DQLL2_0_P" 25\r
+# LOCATE COMP "DQLL2_1"                      SITE "AC2";    #was "DQLL2_1_P" 29\r
+# LOCATE COMP "DQLL2_2"                      SITE "AB4";    #was "DQLL2_2_P" 33\r
+# LOCATE COMP "DQSLL2"                       SITE "AD5";    #was "DQSLL2_T"  37\r
+# LOCATE COMP "DQLL2_3"                      SITE "AA9";    #was "DQLL2_3_P" 41\r
+# LOCATE COMP "DQLL2_4"                      SITE "AB7";    #was "DQLL2_4_P" 45\r
+# LOCATE COMP "DQUL3_0"                      SITE "N4";     #was "DQUL3_0_P" 49\r
+# LOCATE COMP "DQUL3_1"                      SITE "N2";     #was "DQUL3_1_P" 53\r
+# LOCATE COMP "DQUL3_2"                      SITE "M5";     #was "DQUL3_2_P" 57\r
+# LOCATE COMP "DQSUL3"                       SITE "M10";    #was "DQSUL3_T"  61\r
+# LOCATE COMP "DQUL3_3"                      SITE "P5";     #was "DQUL3_3_P" 65\r
+# LOCATE COMP "DQUL3_4"                      SITE "N8";     #was "DQUL3_4_P" 69\r
+# LOCATE COMP "DQUL1_0"                      SITE "L2";     #was "DQUL1_0_P" 73\r
+# LOCATE COMP "DQUL1_1"                      SITE "K2";     #was "DQUL1_1_P" 77\r
+# LOCATE COMP "DQUL1_2"                      SITE "K4";     #was "DQUL1_2_P" 81\r
+# LOCATE COMP "DQSUL1"                       SITE "L10";    #was "DQSUL1_T"  85\r
+# LOCATE COMP "DQUL1_3"                      SITE "M8";     #was "DQUL1_3_P" 89\r
+# LOCATE COMP "DQUL1_4"                      SITE "K7";     #was "DQUL1_4_P" 93\r
+# \r
+# LOCATE COMP "DQUR0_0"                      SITE "L26";    #was "DQUR0_0_P" 105\r
+# LOCATE COMP "DQUR0_1"                      SITE "L32";    #was "DQUR0_1_P" 109\r
+# LOCATE COMP "DQSUR0"                       SITE "M26";    #was "DQSUR0_T"  113\r
+# LOCATE COMP "DQUR0_2"                      SITE "L34";    #was "DQUR0_2_P" 117\r
+# LOCATE COMP "DQUR0_3"                      SITE "K29";    #was "DQUR0_3_P" 121\r
+# LOCATE COMP "DQUR0_4"                      SITE "K34";    #was "DQUR0_4_P" 125\r
+# LOCATE COMP "DQLR0_0"                      SITE "AB34";   #was "DQLR0_0_P" 129\r
+# LOCATE COMP "DQLR0_1"                      SITE "AA25";   #was "DQLR0_1_P" 133\r
+# LOCATE COMP "DQLR0_2"                      SITE "AC34";   #was "DQLR0_2_P" 137\r
+# LOCATE COMP "DQSLR0"                       SITE "AB30";   #was "DQSLR0_T"  141\r
+# LOCATE COMP "DQLR0_3"                      SITE "AA31";   #was "DQLR0_3_P" 145\r
+# LOCATE COMP "DQLR0_4"                      SITE "AA28";   #was "DQLR0_4_P" 149\r
+# \r
+# LOCATE COMP "DQLR1_0"                      SITE "AD31";   #was "DQLR1_0_P" 169\r
+# LOCATE COMP "DQLR1_1"                      SITE "AB32";   #was "DQLR1_1_P" 173\r
+# LOCATE COMP "DQLR1_2"                      SITE "AE34";   #was "DQLR1_2_P" 177\r
+# LOCATE COMP "DQSLR1"                       SITE "AB26";   #was "DQSLR1_T"  181\r
+# LOCATE COMP "DQLR1_3"                      SITE "AD33";   #was "DQLR1_3_P" 185\r
+# LOCATE COMP "DQLR1_4"                      SITE "AF34";   #was "DQLR1_4_P" 189\r
+# \r
+# \r
+# LOCATE COMP "DQLL3_0"                      SITE "AE4";    #was "DQLL3_0_P" 2\r
+# LOCATE COMP "DQLL3_1"                      SITE "AB10";   #was "DQLL3_1_P" 6\r
+# LOCATE COMP "DQLL3_2"                      SITE "AE2";    #was "DQLL3_2_P" 10\r
+# LOCATE COMP "DQSLL3"                       SITE "AJ1";    #was "DQSLL3_T"  14\r
+# LOCATE COMP "DQLL3_3"                      SITE "AD4";    #was "DQLL3_3_P" 18\r
+# LOCATE COMP "DQLL3_4"                      SITE "AC9";    #was "DQLL3_4_P" 22\r
+# LOCATE COMP "DQLL1_0"                      SITE "Y2";     #was "DQLL1_0_P" 26\r
+# LOCATE COMP "DQLL1_1"                      SITE "W4";     #was "DQLL1_1_P" 30\r
+# LOCATE COMP "DQLL1_2"                      SITE "W2";     #was "DQLL1_2_P" 34\r
+# LOCATE COMP "DQSLL1"                       SITE "W6";     #was "DQSLL1_T"  38\r
+# LOCATE COMP "DQLL1_3"                      SITE "W8";     #was "DQLL1_3_P" 42\r
+# LOCATE COMP "DQLL1_4"                      SITE "Y8";     #was "DQLL1_4_P" 46\r
+# LOCATE COMP "DQUL2_0"                      SITE "F2";     #was "DQUL2_0_P" 50\r
+# LOCATE COMP "DQUL2_1"                      SITE "F3";     #was "DQUL2_1_P" 54\r
+# LOCATE COMP "DQUL2_2"                      SITE "G2";     #was "DQUL2_2_P" 58\r
+# LOCATE COMP "DQSUL2"                       SITE "G3";     #was "DQSUL2_T"  62\r
+# LOCATE COMP "DQUL2_3"                      SITE "H1";     #was "DQUL2_3_P" 66\r
+# LOCATE COMP "DQUL2_4"                      SITE "J3";     #was "DQUL2_4_P" 70\r
+# LOCATE COMP "DQUL0_0"                      SITE "L5";     #was "DQUL0_0_P" 74\r
+# LOCATE COMP "DQUL0_1"                      SITE "M4";     #was "DQUL0_1_P" 78\r
+# LOCATE COMP "DQUL0_2"                      SITE "K6";     #was "DQUL0_2_P" 82\r
+# LOCATE COMP "DQSUL0"                       SITE "N9";     #was "DQSUL0_T"  86\r
+# LOCATE COMP "DQUL0_3"                      SITE "M2";     #was "DQUL0_3_P" 90\r
+# LOCATE COMP "DQUL0_4"                      SITE "M7";     #was "DQUL0_4_P" 94\r
+# \r
+# LOCATE COMP "DQUR1_0"                      SITE "N30";    #was "DQUR1_0_P" 106\r
+# LOCATE COMP "DQUR1_1"                      SITE "N26";    #was "DQUR1_1_P" 110\r
+# LOCATE COMP "DQUR1_2"                      SITE "N32";    #was "DQUR1_2_P" 114\r
+# LOCATE COMP "DQSUR1"                       SITE "N27";    #was "DQSUR1_T"  118\r
+# LOCATE COMP "DQUR1_3"                      SITE "N34";    #was "DQUR1_3_P" 122\r
+# LOCATE COMP "DQUR1_4"                      SITE "P28";    #was "DQUR1_4_P" 126\r
+# LOCATE COMP "DQUR2_0"                      SITE "T32";    #was "DQUR2_0_P" 130\r
+# LOCATE COMP "DQUR2_1"                      SITE "T26";    #was "DQUR2_1_P" 134\r
+# LOCATE COMP "DQUR2_2"                      SITE "U32";    #was "DQUR2_2_P" 138\r
+# LOCATE COMP "DQSUR2"                       SITE "T30";    #was "DQSUR2_T"  142\r
+# LOCATE COMP "DQUR2_3"                      SITE "T34";    #was "DQUR2_3_P" 146\r
+# LOCATE COMP "DQUR2_4"                      SITE "U26";    #was "DQUR2_4_P" 150\r
+# \r
+# LOCATE COMP "DQLR2_0"                      SITE "W30";    #was "DQLR2_0_P" 170\r
+# LOCATE COMP "DQLR2_1"                      SITE "W27";    #was "DQLR2_1_P" 174\r
+# LOCATE COMP "DQLR2_2"                      SITE "W34";    #was "DQLR2_2_P" 178\r
+# LOCATE COMP "DQSLR2"                       SITE "Y30";    #was "DQSLR2_T"  182\r
+# LOCATE COMP "DQLR2_3"                      SITE "Y34";    #was "DQLR2_3_P" 186\r
+# LOCATE COMP "DQLR2_4"                      SITE "Y26";    #was "DQLR2_4_P" 190\r
+# \r
+# DEFINE PORT GROUP "DQ_group" "DQ*" ;\r
+# IOBUF GROUP  "DQ_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; \r
 \r
 \r
 \r
@@ -263,88 +263,88 @@ IOBUF GROUP  "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ;
 #################################################################\r
 # KEL Connector\r
 #################################################################\r
-#LOCATE COMP "KEL1_N"                         SITE "AP6";\r
-#LOCATE COMP "KEL2_N"                         SITE "AP3";\r
-#LOCATE COMP "KEL3_N"                         SITE "AN2";\r
-#LOCATE COMP "KEL4_N"                         SITE "AM3";\r
-#LOCATE COMP "KEL5_N"                         SITE "AM5";\r
-#LOCATE COMP "KEL6_N"                         SITE "AN6";\r
-#LOCATE COMP "KEL7_N"                         SITE "AM4";\r
-#LOCATE COMP "KEL8_N"                         SITE "AJ6";\r
-#LOCATE COMP "KEL9_N"                         SITE "AJ3";\r
-#LOCATE COMP "KEL10_N"                        SITE "AK3";\r
-#LOCATE COMP "KEL11_N"                        SITE "AD8";\r
-#LOCATE COMP "KEL12_N"                        SITE "AK4";\r
-#LOCATE COMP "KEL13_N"                        SITE "V3";\r
-#LOCATE COMP "KEL14_N"                        SITE "W5";\r
-#LOCATE COMP "KEL15_N"                        SITE "T8";\r
-#LOCATE COMP "KEL16_N"                        SITE "T1";\r
-#LOCATE COMP "KEL17_N"                        SITE "P6";\r
-#LOCATE COMP "KEL18_N"                        SITE "T7";\r
-#LOCATE COMP "KEL19_N"                        SITE "R1";\r
-#LOCATE COMP "KEL20_N"                        SITE "P10";\r
-#LOCATE COMP "KEL21_N"                        SITE "AP30";\r
-#LOCATE COMP "KEL22_N"                        SITE "AP32";\r
-#LOCATE COMP "KEL23_N"                        SITE "AN33";\r
-#LOCATE COMP "KEL24_N"                        SITE "AN31";\r
-#LOCATE COMP "KEL25_N"                        SITE "AM32";\r
-#LOCATE COMP "KEL26_N"                        SITE "AN29";\r
-#LOCATE COMP "KEL27_N"                        SITE "AM31";\r
-#LOCATE COMP "KEL28_N"                        SITE "AM30";\r
-#LOCATE COMP "KEL29_N"                        SITE "AL33";\r
-#LOCATE COMP "KEL30_N"                        SITE "AK31";\r
-#LOCATE COMP "KEL31_N"                        SITE "AJ33";\r
-#LOCATE COMP "KEL32_N"                        SITE "AK32";\r
-#LOCATE COMP "KEL33_N"                        SITE "AF31";\r
-#LOCATE COMP "KEL34_N"                        SITE "AE31";\r
-#LOCATE COMP "KEL35_N"                        SITE "AE29";\r
-#LOCATE COMP "KEL36_N"                        SITE "AD25";\r
-#LOCATE COMP "KEL37_N"                        SITE "L30";\r
-#LOCATE COMP "KEL38_N"                        SITE "AB27";\r
-#LOCATE COMP "KEL39_N"                        SITE "M33";\r
-#LOCATE COMP "KEL40_N"                        SITE "M28";\r
-LOCATE COMP "KEL_1"                         SITE "AP5";\r
-LOCATE COMP "KEL_2"                         SITE "AP2";\r
-LOCATE COMP "KEL_3"                         SITE "AN1";\r
-LOCATE COMP "KEL_4"                         SITE "AN3";\r
-LOCATE COMP "KEL_5"                         SITE "AL5";\r
-LOCATE COMP "KEL_6"                         SITE "AM6";\r
-LOCATE COMP "KEL_7"                         SITE "AL4";\r
-LOCATE COMP "KEL_8"                         SITE "AJ5";\r
-LOCATE COMP "KEL_9"                         SITE "AJ2";\r
-LOCATE COMP "KEL_10"                        SITE "AL3";\r
-LOCATE COMP "KEL_11"                        SITE "AD9";\r
-LOCATE COMP "KEL_12"                        SITE "AJ4";\r
-LOCATE COMP "KEL_13"                        SITE "V4";\r
-LOCATE COMP "KEL_14"                        SITE "V5";\r
-LOCATE COMP "KEL_15"                        SITE "T9";\r
-LOCATE COMP "KEL_16"                        SITE "T2";\r
-LOCATE COMP "KEL_17"                        SITE "P7";\r
-LOCATE COMP "KEL_18"                        SITE "R8";\r
-LOCATE COMP "KEL_19"                        SITE "R2";\r
-LOCATE COMP "KEL_20"                        SITE "P9";\r
-LOCATE COMP "KEL_21"                        SITE "AP29";\r
-LOCATE COMP "KEL_22"                        SITE "AP33";\r
-LOCATE COMP "KEL_23"                        SITE "AN34";\r
-LOCATE COMP "KEL_24"                        SITE "AP31";\r
-LOCATE COMP "KEL_25"                        SITE "AN32";\r
-LOCATE COMP "KEL_26"                        SITE "AM29";\r
-LOCATE COMP "KEL_27"                        SITE "AL31";\r
-LOCATE COMP "KEL_28"                        SITE "AL30";\r
-LOCATE COMP "KEL_29"                        SITE "AL34";\r
-LOCATE COMP "KEL_30"                        SITE "AJ31";\r
-LOCATE COMP "KEL_31"                        SITE "AH33";\r
-LOCATE COMP "KEL_32"                        SITE "AL32";\r
-LOCATE COMP "KEL_33"                        SITE "AF32";\r
-LOCATE COMP "KEL_34"                        SITE "AE32";\r
-LOCATE COMP "KEL_35"                        SITE "AE30";\r
-LOCATE COMP "KEL_36"                        SITE "AD26";\r
-LOCATE COMP "KEL_37"                        SITE "M29";\r
-LOCATE COMP "KEL_38"                        SITE "AC28";\r
-LOCATE COMP "KEL_39"                        SITE "M34";\r
-LOCATE COMP "KEL_40"                        SITE "L28";\r
-DEFINE PORT GROUP "KEL_group" "KEL*" ;\r
-IOBUF GROUP  "KEL_group" IO_TYPE=LVDS25 ;\r
+# # LOCATE COMP "KEL1_N"                         SITE "AP6";\r
+# # LOCATE COMP "KEL2_N"                         SITE "AP3";\r
+# # LOCATE COMP "KEL3_N"                         SITE "AN2";\r
+# # LOCATE COMP "KEL4_N"                         SITE "AM3";\r
+# # LOCATE COMP "KEL5_N"                         SITE "AM5";\r
+# # LOCATE COMP "KEL6_N"                         SITE "AN6";\r
+# # LOCATE COMP "KEL7_N"                         SITE "AM4";\r
+# # LOCATE COMP "KEL8_N"                         SITE "AJ6";\r
+# # LOCATE COMP "KEL9_N"                         SITE "AJ3";\r
+# # LOCATE COMP "KEL10_N"                        SITE "AK3";\r
+# # LOCATE COMP "KEL11_N"                        SITE "AD8";\r
+# # LOCATE COMP "KEL12_N"                        SITE "AK4";\r
+# # LOCATE COMP "KEL13_N"                        SITE "V3";\r
+# # LOCATE COMP "KEL14_N"                        SITE "W5";\r
+# # LOCATE COMP "KEL15_N"                        SITE "T8";\r
+# # LOCATE COMP "KEL16_N"                        SITE "T1";\r
+# # LOCATE COMP "KEL17_N"                        SITE "P6";\r
+# # LOCATE COMP "KEL18_N"                        SITE "T7";\r
+# # LOCATE COMP "KEL19_N"                        SITE "R1";\r
+# # LOCATE COMP "KEL20_N"                        SITE "P10";\r
+# # LOCATE COMP "KEL21_N"                        SITE "AP30";\r
+# # LOCATE COMP "KEL22_N"                        SITE "AP32";\r
+# # LOCATE COMP "KEL23_N"                        SITE "AN33";\r
+# # LOCATE COMP "KEL24_N"                        SITE "AN31";\r
+# # LOCATE COMP "KEL25_N"                        SITE "AM32";\r
+# # LOCATE COMP "KEL26_N"                        SITE "AN29";\r
+# # LOCATE COMP "KEL27_N"                        SITE "AM31";\r
+# # LOCATE COMP "KEL28_N"                        SITE "AM30";\r
+# # LOCATE COMP "KEL29_N"                        SITE "AL33";\r
+# # LOCATE COMP "KEL30_N"                        SITE "AK31";\r
+# # LOCATE COMP "KEL31_N"                        SITE "AJ33";\r
+# # LOCATE COMP "KEL32_N"                        SITE "AK32";\r
+# # LOCATE COMP "KEL33_N"                        SITE "AF31";\r
+# # LOCATE COMP "KEL34_N"                        SITE "AE31";\r
+# # LOCATE COMP "KEL35_N"                        SITE "AE29";\r
+# # LOCATE COMP "KEL36_N"                        SITE "AD25";\r
+# # LOCATE COMP "KEL37_N"                        SITE "L30";\r
+# # LOCATE COMP "KEL38_N"                        SITE "AB27";\r
+# # LOCATE COMP "KEL39_N"                        SITE "M33";\r
+# # LOCATE COMP "KEL40_N"                        SITE "M28";\r
+# LOCATE COMP "KEL_1"                         SITE "AP5";\r
+# LOCATE COMP "KEL_2"                         SITE "AP2";\r
+# LOCATE COMP "KEL_3"                         SITE "AN1";\r
+# LOCATE COMP "KEL_4"                         SITE "AN3";\r
+# LOCATE COMP "KEL_5"                         SITE "AL5";\r
+# LOCATE COMP "KEL_6"                         SITE "AM6";\r
+# LOCATE COMP "KEL_7"                         SITE "AL4";\r
+# LOCATE COMP "KEL_8"                         SITE "AJ5";\r
+# LOCATE COMP "KEL_9"                         SITE "AJ2";\r
+# LOCATE COMP "KEL_10"                        SITE "AL3";\r
+# LOCATE COMP "KEL_11"                        SITE "AD9";\r
+# LOCATE COMP "KEL_12"                        SITE "AJ4";\r
+# LOCATE COMP "KEL_13"                        SITE "V4";\r
+# LOCATE COMP "KEL_14"                        SITE "V5";\r
+# LOCATE COMP "KEL_15"                        SITE "T9";\r
+# LOCATE COMP "KEL_16"                        SITE "T2";\r
+# LOCATE COMP "KEL_17"                        SITE "P7";\r
+# LOCATE COMP "KEL_18"                        SITE "R8";\r
+# LOCATE COMP "KEL_19"                        SITE "R2";\r
+# LOCATE COMP "KEL_20"                        SITE "P9";\r
+# LOCATE COMP "KEL_21"                        SITE "AP29";\r
+# LOCATE COMP "KEL_22"                        SITE "AP33";\r
+# LOCATE COMP "KEL_23"                        SITE "AN34";\r
+# LOCATE COMP "KEL_24"                        SITE "AP31";\r
+# LOCATE COMP "KEL_25"                        SITE "AN32";\r
+# LOCATE COMP "KEL_26"                        SITE "AM29";\r
+# LOCATE COMP "KEL_27"                        SITE "AL31";\r
+# LOCATE COMP "KEL_28"                        SITE "AL30";\r
+# LOCATE COMP "KEL_29"                        SITE "AL34";\r
+# LOCATE COMP "KEL_30"                        SITE "AJ31";\r
+# LOCATE COMP "KEL_31"                        SITE "AH33";\r
+# LOCATE COMP "KEL_32"                        SITE "AL32";\r
+# LOCATE COMP "KEL_33"                        SITE "AF32";\r
+# LOCATE COMP "KEL_34"                        SITE "AE32";\r
+# LOCATE COMP "KEL_35"                        SITE "AE30";\r
+# LOCATE COMP "KEL_36"                        SITE "AD26";\r
+# LOCATE COMP "KEL_37"                        SITE "M29";\r
+# LOCATE COMP "KEL_38"                        SITE "AC28";\r
+# LOCATE COMP "KEL_39"                        SITE "M34";\r
+# LOCATE COMP "KEL_40"                        SITE "L28";\r
+# DEFINE PORT GROUP "KEL_group" "KEL*" ;\r
+# IOBUF GROUP  "KEL_group" IO_TYPE=LVDS25 ;\r
 \r
 #################################################################\r
 # Many LED\r
@@ -373,8 +373,8 @@ LOCATE COMP "LED_SFP_RED_1"                  SITE "A8";
 DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ;\r
 IOBUF GROUP  "LED_SFP_group" IO_TYPE=LVTTL33 ;\r
 \r
-LOCATE COMP "LED_WHITE_1"                    SITE "A32";\r
-LOCATE COMP "LED_WHITE_2"                    SITE "A33";\r
+LOCATE COMP "LED_WHITE_0"                    SITE "A32";\r
+LOCATE COMP "LED_WHITE_1"                    SITE "A33";\r
 DEFINE PORT GROUP "LED_WHITE_group" "LED_WHITE*" ;\r
 IOBUF GROUP  "LED_WHITE_group" IO_TYPE=LVTTL33 ;\r
 \r
@@ -389,12 +389,12 @@ LOCATE COMP "SFP_MOD1_0"                     SITE "B7";
 LOCATE COMP "SFP_MOD1_1"                     SITE "J11";\r
 LOCATE COMP "SFP_MOD2_0"                     SITE "A7";\r
 LOCATE COMP "SFP_MOD2_1"                     SITE "D9";\r
-LOCATE COMP "SFP_RATE_SEL_0"                 SITE "A4";\r
-LOCATE COMP "SFP_RATE_SEL_1"                 SITE "C8";\r
+# LOCATE COMP "SFP_RATE_SEL_0"                 SITE "A4";\r
+# LOCATE COMP "SFP_RATE_SEL_1"                 SITE "C8";\r
 LOCATE COMP "SFP_TX_DIS_0"                   SITE "D6";\r
 LOCATE COMP "SFP_TX_DIS_1"                   SITE "A9";\r
-LOCATE COMP "SFP_TX_FAULT_0"                 SITE "C5";\r
-LOCATE COMP "SFP_TX_FAULT_1"                 SITE "B8";\r
+# LOCATE COMP "SFP_TX_FAULT_0"                 SITE "C5";\r
+# LOCATE COMP "SFP_TX_FAULT_1"                 SITE "B8";\r
 DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
 IOBUF GROUP  "SFP_group" IO_TYPE=LVTTL33 ;\r
 \r

diff --git a/scripts/compile.pl b/scripts/compile.pl
index bcdf1f007e7e3ea7b69ea47fffa954cd26703406..028f37f6f6e17616109be44995f637ebb4c6cc53 100755 (executable)
--- a/scripts/compile.pl
+++ b/scripts/compile.pl
@@ -22,7 +22,7 @@ my $lattice_bin_path             = "$lattice_path/bin/lin64"; # note the lin/lin
 my $include_TDC                  = $config{include_TDC} || 0;
 my $include_GBE                  = $config{include_GBE} || 0;
 my $twr_number_of_errors         = $config{twr_number_of_errors} || 10;
-
+my $pinout_file                  = $config{pinout_file} || $TOPNAME;
 
 ###################################################################################
 #Settings for this project
@@ -111,8 +111,8 @@ system("ln -sfT $lattice_path $WORKDIR/lattice-diamond");
 
 #create full lpf file
 print GREEN, "Generating constraints file...\n\n", RESET;
-system("cp ../pinout/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf");
-
+system("cp ../pinout/$pinout_file.lpf $WORKDIR/$TOPNAME.lpf");
+system("cat ../pinout/trb3sc_basic.lpf >> $WORKDIR/$TOPNAME.lpf");
 system("cat ../pinout/basic_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
 
 if($include_TDC) {

diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl
index 28137a72c9a52525165417df89b563d68ef63198..7eaea2c0a228a6c2493c4ceb826b6b32349479a4 100644 (file)
--- a/template/config_compile_frankfurt.pl
+++ b/template/config_compile_frankfurt.pl
@@ -8,6 +8,7 @@ synplify_command             => "/d/jspc29/lattice/diamond/3.4_x64/bin/lin64/syn
 
 
 #Include only necessary lpf files
+#pinout_file                  => '', #name of pin-out file, if not equal TOPNAME
 include_TDC                  => 0,
 include_GBE                  => 0,
 

diff --git a/template/synplify.fdc b/template/synplify.fdc
new file mode 100644 (file)
index 0000000..1a8f9d8
--- /dev/null
+++ b/template/synplify.fdc
@@ -0,0 +1,51 @@
+###==== BEGIN Header
+
+# Synopsys, Inc. constraint file
+# /d/jspc22/trb/git/trb3sc/template/synplify.fdc
+# Written on Thu Jun 18 11:51:05 2015
+# by Synplify Pro, I-2014.03L-SP1  FDC Constraint Editor
+
+# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
+# These sections are generated from SCOPE spreadsheet tabs.
+
+###==== END Header
+
+###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
+###==== END Collections
+
+###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
+create_clock  -name {clk240} {p:CLK_CORE_PCLK} -period {4.16}
+create_clock  -name {clksys} {n:THE_CLOCK_RESET.SYS_CLK_OUT} -period {10}
+create_clock  -name {clktxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.tx_full_clk_ch3} -period {5}
+create_clock  -name {clkrxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.rx_full_clk_ch3} -period {5}
+create_clock  -name {clkintfull} {n:THE_CLOCK_RESET.gen_norecov_clock\.gen_200\.THE_INT_PLL.CLKOP} -period {5}
+
+###==== END Clocks
+
+###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
+###==== END "Generated Clocks"
+
+###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
+###==== END Inputs/Outputs
+
+
+###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
+###==== END "Delay Paths"
+
+###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
+###==== END Attributes
+
+###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
+###==== END "I/O Standards"
+
+###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
+###==== END "Compile Points"
+
+
+
+
+
+
+
+
+

diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj
index e32699b6fa65b1e34a4de92ac1f996c8168bc883..1417925c50dc9314ed863081fc20a2d153628464 100644 (file)
--- a/template/trb3sc_basic.prj
+++ b/template/trb3sc_basic.prj
@@ -16,11 +16,11 @@ set_option -top_module "trb3sc_basic"
 set_option -resource_sharing false
 
 # map options
-set_option -frequency 200
+set_option -frequency 120
 set_option -fanout_limit 100
 set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
+set_option -retiming 1
+set_option -pipe 1
 set_option -force_gsr false
 set_option -fixgatedclocks 3
 set_option -fixgeneratedclocks 3
@@ -63,9 +63,10 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd"
 
 #Basic Infrastructure
-add_file -vhdl -lib work "../../trb3/base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
+add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
@@ -124,6 +125,8 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
@@ -174,7 +177,7 @@ add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
 
 
 add_file -vhdl -lib work "./trb3sc_basic.vhd"
-
+#add_file -fpga_constraint "./synplify.fdc"
 
 
 

diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd
index 34952ae3183eba3d5b7eff421a4d340fc4124429..4b21470b1f31b38101a1bec241e899e94b044a58 100644 (file)
--- a/template/trb3sc_basic.vhd
+++ b/template/trb3sc_basic.vhd
@@ -13,35 +13,34 @@ use work.version.all;
 use work.trb_net_gbe_components.all;
 use work.med_sync_define.all;
 
-
-
-
 entity trb3sc_basic is
   port(
-    CLK_SUPPL_PCLK       : in    std_logic;
-    CLK_SUPPL_PLL_LEFT   : in    std_logic;
-    CLK_SUPPL_PLL_RIGHT  : in    std_logic;
-    CLK_CORE_PCLK        : in    std_logic;
-    CLK_CORE_PLL_LEFT    : in    std_logic;
-    CLK_CORE_PLL_RIGHT   : in    std_logic;
-    CLK_EXT_PCLK         : in    std_logic;
-    CLK_EXT_PLL_LEFT     : in    std_logic;
-    CLK_EXT_PLL_RIGHT    : in    std_logic;
+    CLK_SUPPL_PCLK       : in    std_logic; --125 MHz for GbE
+    CLK_CORE_PCLK        : in    std_logic; --Main Oscillator
+    CLK_EXT_PLL_LEFT     : in    std_logic; --External Clock
+    --CLK_SUPPL_PLL_LEFT   : in    std_logic; --not used
+    --CLK_SUPPL_PLL_RIGHT  : in    std_logic; --not used
+    --CLK_CORE_PLL_LEFT    : in    std_logic; --not used
+    --CLK_CORE_PLL_RIGHT   : in    std_logic; --not used
+    --CLK_EXT_PCLK         : in    std_logic; --not used
+    --CLK_EXT_PLL_RIGHT    : in    std_logic; --not used
     
-    TRIG_PLL             : in    std_logic;
-    TRIG_LEFT            : in    std_logic;
-    TRIG_RIGHT           : in    std_logic;
+    TRIG_LEFT            : in    std_logic; --Trigger Input
+    --TRIG_PLL             : in    std_logic; --not used
+    --TRIG_RIGHT           : in    std_logic; --not used
     
-    --Backplane
+    --Backplane, all lines
     BACK_GPIO            : inout std_logic_vector(15 downto 0);
     BACK_LVDS            : inout std_logic_vector( 1 downto 0);
     BACK_3V3             : inout std_logic_vector( 3 downto 0);
+    --Backplane for slaves on trbv3scbp1
+--     BACK_GPIO            : inout std_logic_vector(3 downto 0);
     
     --AddOn Connector
     --to be added
     
     --KEL Connector
-    KEL                  : inout std_logic_vector(40 downto 1);
+--     KEL                  : inout std_logic_vector(40 downto 1);
     
     --Additional IO
     HDR_IO               : inout std_logic_vector( 9 downto 0);
@@ -50,11 +49,11 @@ entity trb3sc_basic is
     
     --LED
     LED_GREEN            : out   std_logic;
+    LED_YELLOW           : out   std_logic;
     LED_ORANGE           : out   std_logic;
     LED_RED              : out   std_logic;
     LED_RJ_GREEN         : out   std_logic_vector( 1 downto 0);
     LED_RJ_RED           : out   std_logic_vector( 1 downto 0);
-    LED_YELLOW           : out   std_logic;
     LED_WHITE            : out   std_logic_vector( 1 downto 0);
     LED_SFP_GREEN        : out   std_logic_vector( 1 downto 0);
     LED_SFP_RED          : out   std_logic_vector( 1 downto 0);
@@ -62,12 +61,12 @@ entity trb3sc_basic is
     --SFP
     SFP_LOS              : in    std_logic_vector( 1 downto 0);
     SFP_MOD0             : in    std_logic_vector( 1 downto 0);  
-    SFP_MOD1             : inout std_logic_vector( 1 downto 0);
-    SFP_MOD2             : inout std_logic_vector( 1 downto 0);
-    SFP_TX_DIS           : out   std_logic_vector( 1 downto 0);  
+    SFP_MOD1             : inout std_logic_vector( 1 downto 0) := (others => 'Z');
+    SFP_MOD2             : inout std_logic_vector( 1 downto 0) := (others => 'Z');
+    SFP_TX_DIS           : out   std_logic_vector( 1 downto 0) := (others => '0');  
     
-    SERDES_TX            : out   std_logic_vector(27 downto 0);
-    SERDES_RX            : in    std_logic_vector(27 downto 0);
+    SERDES_TX            : out   std_logic_vector(1 downto 0);
+    SERDES_RX            : in    std_logic_vector(1 downto 0);
     
     --Serdes switch
     PCSSW_ENSMB          : out   std_logic;
@@ -96,29 +95,6 @@ entity trb3sc_basic is
 
 
   attribute syn_useioff                  : boolean;
-  --no IO-FF for LEDs relaxes timing constraints
-  attribute syn_useioff of LED_GREEN       : signal is false;
-  attribute syn_useioff of LED_ORANGE      : signal is false;
-  attribute syn_useioff of LED_RED         : signal is false;
-  attribute syn_useioff of LED_RJ_GREEN  : signal is false;
-  attribute syn_useioff of LED_RJ_RED    : signal is false;
-  attribute syn_useioff of LED_YELLOW      : signal is false;
-  attribute syn_useioff of LED_WHITE       : signal is false;
-  attribute syn_useioff of LED_SFP_GREEN   : signal is false;
-  attribute syn_useioff of LED_SFP_RED     : signal is false; 
-  
-  attribute syn_useioff of TEMPSENS        : signal is false;
-  attribute syn_useioff of PROGRAMN        : signal is false;
-  attribute syn_useioff of TRIG_LEFT       : signal is false;
-  attribute syn_useioff of TRIG_RIGHT      : signal is false;
-  
-  attribute syn_useioff of SFP_LOS         : signal is false;
-  attribute syn_useioff of SFP_MOD0        : signal is false;
-  attribute syn_useioff of SFP_MOD1        : signal is false;
-  attribute syn_useioff of SFP_MOD2        : signal is false;
-  attribute syn_useioff of SFP_TX_DIS      : signal is false;
-  
-  --important signals _with_ IO-FF
   attribute syn_useioff of FLASH_CLK  : signal is true;
   attribute syn_useioff of FLASH_CS   : signal is true;
   attribute syn_useioff of FLASH_IN   : signal is true;
@@ -138,8 +114,6 @@ architecture trb3sc_arch of trb3sc_basic is
   attribute syn_preserve : boolean;
   
   signal clk_sys, clk_full, clk_full_osc   : std_logic;
-  signal clk_half_rx, clk_full_rx : std_logic;
-
   signal GSR_N       : std_logic;
   signal reset_i     : std_logic;
   signal clear_i     : std_logic;
@@ -148,18 +122,9 @@ architecture trb3sc_arch of trb3sc_basic is
   signal debug_clock_reset : std_logic_vector(31 downto 0);
 
   --Media Interface
-  signal med_stat_op             : std_logic_vector (1*16-1  downto 0);
-  signal med_ctrl_op             : std_logic_vector (1*16-1  downto 0);
+  signal med2int                 : med2int_array_t(0 to 0);
+  signal int2med                 : int2med_array_t(0 to 0);
   signal med_stat_debug          : std_logic_vector (1*64-1  downto 0);
-  signal med_ctrl_debug          : std_logic_vector (1*64-1  downto 0);
-  signal med_data_out            : std_logic_vector (1*16-1  downto 0);
-  signal med_packet_num_out      : std_logic_vector (1*3-1   downto 0);
-  signal med_dataready_out       : std_logic_vector (1*1-1   downto 0);
-  signal med_read_out            : std_logic_vector (1*1-1   downto 0);
-  signal med_data_in             : std_logic_vector (1*16-1  downto 0);
-  signal med_packet_num_in       : std_logic_vector (1*3-1   downto 0);
-  signal med_dataready_in        : std_logic_vector (1*1-1   downto 0);
-  signal med_read_in             : std_logic_vector (1*1-1   downto 0);
   
   --READOUT
   signal readout_rx              : READOUT_RX;
@@ -170,12 +135,11 @@ architecture trb3sc_arch of trb3sc_basic is
   
   signal common_stat_reg         : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
   signal common_ctrl_reg         : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-  signal common_stat_reg_strobe  : std_logic_vector(std_COMSTATREG-1 downto 0);
-  signal common_ctrl_reg_strobe  : std_logic_vector(std_COMCTRLREG-1 downto 0);
   
   signal sed_error_i    : std_logic;
   signal clock_select   : std_logic;
 
+  signal timer          : TIMERS;
   
   attribute syn_keep of GSR_N     : signal is true;
   attribute syn_preserve of GSR_N : signal is true;  
@@ -195,9 +159,9 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
   port map(
     INT_CLK_IN      => CLK_CORE_PCLK,
     EXT_CLK_IN      => CLK_EXT_PLL_LEFT,
-    NET_CLK_FULL_IN => clk_full_rx,
-    NET_CLK_HALF_IN => clk_half_rx,
-    RESET_FROM_NET  => med_stat_op(13),
+    NET_CLK_FULL_IN => med2int(0).clk_full,
+    NET_CLK_HALF_IN => med2int(0).clk_half,
+    RESET_FROM_NET  => med2int(0).stat_op(13),
     
     BUS_RX          => bustc_rx,
     BUS_TX          => bustc_tx,
@@ -210,6 +174,7 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     SYS_CLK_OUT     => clk_sys,
     REF_CLK_OUT     => clk_full_osc,
     
+    ENPIRION_CLOCK  => ENPIRION_CLOCK,    
     LED_RED_OUT     => LED_RJ_RED,
     LED_GREEN_OUT   => LED_RJ_GREEN,
     DEBUG_OUT       => debug_clock_reset
@@ -220,10 +185,10 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
 -- TrbNet Uplink
 ---------------------------------------------------------------------------
 
-THE_MEDIA_INTERFACE : med_ecp3_sfp_sync
+THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
   generic map(
     SERDES_NUM  => 3,
-    IS_SYNC_SLAVE   => c_YES
+    IS_SYNC_SLAVE   => c_NO
     )
   port map(
     CLK                => clk_full_osc,
@@ -231,17 +196,9 @@ THE_MEDIA_INTERFACE : med_ecp3_sfp_sync
     RESET              => reset_i,
     CLEAR              => clear_i,
     --Internal Connection
-    MED_DATA_IN        => med_data_out(15 downto 0),
-    MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
-    MED_DATAREADY_IN   => med_dataready_out(0),
-    MED_READ_OUT       => med_read_in(0),
-    MED_DATA_OUT       => med_data_in(15 downto 0),
-    MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
-    MED_DATAREADY_OUT  => med_dataready_in(0),
-    MED_READ_IN        => med_read_out(0),
-    CLK_RX_HALF_OUT    => clk_half_rx,
-    CLK_RX_FULL_OUT    => clk_full_rx,
-    
+    MEDIA_MED2INT      => med2int(0),
+    MEDIA_INT2MED      => int2med(0),
+
     --Sync operation
     RX_DLM             => open,
     RX_DLM_WORD        => open,
@@ -259,20 +216,14 @@ THE_MEDIA_INTERFACE : med_ecp3_sfp_sync
     SD_LOS_IN          => SFP_LOS(1),
     SD_TXDIS_OUT       => SFP_TX_DIS(1),
     --Control Interface
-    SCI_DATA_IN        => bussci_RX.data(7 downto 0),
-    SCI_DATA_OUT       => bussci_TX.data(7 downto 0),
-    SCI_ADDR           => bussci_RX.addr(8 downto 0),
-    SCI_READ           => bussci_RX.read,
-    SCI_WRITE          => bussci_RX.write,
-    SCI_ACK            => bussci_TX.ack,
-    SCI_NACK           => bussci_TX.unknown,
+    BUS_RX             => bussci_rx,
+    BUS_TX             => bussci_tx,
     -- Status and control port
-    STAT_OP            => med_stat_op(15 downto 0),
-    CTRL_OP            => med_ctrl_op(15 downto 0),
     STAT_DEBUG         => med_stat_debug(63 downto 0),
     CTRL_DEBUG         => open
-   );
+  );
 
+SFP_TX_DIS(0) <= '1';
 
 ---------------------------------------------------------------------------
 -- Endpoint
@@ -300,16 +251,8 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
     CLK_EN                       => '1',
 
     --  Media direction port
-    MED_DATAREADY_OUT            => med_dataready_out(0),
-    MED_DATA_OUT                 => med_data_out(15 downto 0),
-    MED_PACKET_NUM_OUT           => med_packet_num_out(2 downto 0),
-    MED_READ_IN                  => med_read_in(0),
-    MED_DATAREADY_IN             => med_dataready_in(0),
-    MED_DATA_IN                  => med_data_in(15 downto 0),
-    MED_PACKET_NUM_IN            => med_packet_num_in(2 downto 0),
-    MED_READ_OUT                 => med_read_out(0),
-    MED_STAT_OP_IN               => med_stat_op(15 downto 0),
-    MED_CTRL_OP_OUT              => med_ctrl_op(15 downto 0),
+    MEDIA_MED2INT                => med2int(0),
+    MEDIA_INT2MED                => int2med(0),
 
     --Timing trigger in
     TRG_TIMING_TRG_RECEIVED_IN   => TRIG_LEFT,
@@ -320,17 +263,11 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
     --Slow Control Port
     REGIO_COMMON_STAT_REG_IN     => common_stat_reg,  --0x00
     REGIO_COMMON_CTRL_REG_OUT    => common_ctrl_reg,  --0x20
-    REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
-    REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
     BUS_RX                       => ctrlbus_rx,
     BUS_TX                       => ctrlbus_tx,
     ONEWIRE_INOUT                => TEMPSENS,
     --Timing registers
-    TIME_GLOBAL_OUT              => open, --global time, microseconds
-    TIME_LOCAL_OUT               => open, --local time running with chip frequency
-    TIME_SINCE_LAST_TRG_OUT      => open, --local time, resetted with each trigger
-    TIME_TICKS_OUT               => open  --bit 1 ms-tick, 0 us-tick
-
+    TIMERS_OUT                   => timer
     );
 
 ---------------------------------------------------------------------------
@@ -400,20 +337,17 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
 ---------------------------------------------------------------------------
 -- Switches
 ---------------------------------------------------------------------------
-
 --Serdes Select
   PCSSW_ENSMB <= '0';
   PCSSW_EQ    <= x"0";
   PCSSW_PE    <= x"F";
   PCSSW       <= "01001110"; --SFP2 on B3, AddOn on D1
 
-
 ---------------------------------------------------------------------------
 -- I/O
 ---------------------------------------------------------------------------
   HDR_IO              <= (others => '0');
   RJ_IO               <= "0000";
-
   
   BACK_GPIO           <= (others => 'Z');
   BACK_LVDS           <= (others => '0');
@@ -422,29 +356,33 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
 ---------------------------------------------------------------------------
 -- LED
 ---------------------------------------------------------------------------
+  --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
   LED_GREEN            <= debug_clock_reset(0);   
   LED_ORANGE           <= debug_clock_reset(1);
-  LED_RED              <= debug_clock_reset(2); --not sed_error_i;
-  LED_YELLOW           <= debug_clock_reset(3);
-
---   LED_RJ_GREEN         <= '0' & not std_logic_vector(to_unsigned(USE_RXCLOCK,1));   --1 must be 0, 
---   LED_RJ_RED           <= not clock_select & std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+  LED_RED              <= not sed_error_i;
+  LED_YELLOW           <= debug_clock_reset(2);
   LED_WHITE            <= time_counter(26) & time_counter(28);  
-  LED_SFP_GREEN        <= not med_stat_op(9) & '1';  --SFP Link Status
-  LED_SFP_RED          <= not (med_stat_op(10) or med_stat_op(11)) & '1';  --SFP RX/TX
+  LED_SFP_GREEN        <= not med2int(0).stat_op(9) & '1';  --SFP Link Status
+  LED_SFP_RED          <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1';  --SFP RX/TX
 
+--   DEBUG_OUT(0)  <= pll_int_lock;
+-- DEBUG_OUT(1)  <= pll_ext_lock;
+-- DEBUG_OUT(2)  <= clock_select;
+  
 ---------------------------------------------------------------------------
 -- Test Circuits
 ---------------------------------------------------------------------------
-  process
-    begin
-      wait until rising_edge(clk_sys);
-      time_counter <= time_counter + 1;
-    end process;
-
-
+  process begin
+    wait until rising_edge(clk_sys);
+    time_counter <= time_counter + 1; 
+    if reset_i = '1' then
+      time_counter <= (others => '0');
+    end if;
+  end process;  
+
+--   TEST_LINE <= med_stat_debug(15 downto 0);
+  
 end architecture;
 
 
 
-