TOPNAME => "trb5sc_adc",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
-lm_license_file_for_par => "1702\@jspc29",
+lm_license_file_for_par => "1710\@jspc29",
lattice_path => '/d/jspc29/lattice/diamond/3.12',
synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2/',
#-m nodelist.txt # Controlled by the compile.pl script.
#-n 1 # Controlled by the compile.pl script.
-s 10
--t 11
+-t 13
-c 2
-e 2
-i 10
CLK_ADCRAW : in std_logic; --200 MHz
ADC_DATA : in std_logic_vector(1 downto 0);
- SHIFT_ALIGN_IN : in std_logic;
+ CONF_ALIGN_EN : in std_logic;
+ CONF_DATA_SHIFTED : in std_logic;
DEL_CFLAG : out std_logic;
DEL_DIRECTION : in std_logic;
DEL_LOADN : in std_logic;
DATA_OUT : out std_logic_vector(17 downto 0);
DATA_VALID_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(31 downto 0)
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
);
end entity;
signal data_in : std_logic_vector(3 downto 0);
signal clock_enable : std_logic;
+signal data_shifted : std_logic;
+signal cycle_counter : integer range 0 to 30;
+signal cycle_input : integer range 0 to 13;
-signal cycle_counter : integer range 0 to 12;
+signal data_reg : std_logic_vector(27 downto 0);
+signal data_reg_save : std_logic_vector(27 downto 0);
+signal clock_reg : std_logic_vector(27 downto 0);
+signal clock_reg_save : std_logic_vector(27 downto 0);
+constant TESTPATTERN : std_logic_vector(17 downto 0) := 18x"281FC";
+
+signal start_timer : unsigned(23 downto 0) := (others => '0');
begin
-THE_INPUT : adc_1ch_inp
+THE_INPUT : entity work.adc_1ch_inp
port map (
clkin => CLK_ADCRAW,
data_cflag => DEL_CFLAG,
);
-THE_CLOCK_OUT : adc_1ch_clk
+THE_CLOCK_OUT : entity work.adc_1ch_clk
port map(
refclk => CLK_ADCRAW,
reset => '0',
data => '0' & clock_enable,
- dout => ADC_CLK_OUT
+ dout(0) => ADC_CLK_OUT
);
+
+
+PROC_START : process begin
+ wait until rising_edge(CLK_ADCRAW);
+ if RESET_ADC = '1' then
+ start_timer <= (others => '0');
+ elsif start_timer(start_timer'left) = '0' then
+ start_timer <= start_timer + 1;
+ end if;
+end process;
+
+PROC_CONTROL : process begin
+ wait until rising_edge(CLK_ADCRAW);
+
+ if start_timer(start_timer'left) = '1' then
+ if cycle_counter = 30 then
+ cycle_counter <= 0;
+ else
+ cycle_counter <= cycle_counter + 1;
+ end if;
+
+ if cycle_counter = 10 then
+ clock_enable <= '1';
+ elsif cycle_counter = 19 then
+ clock_enable <= '0';
+ end if;
+
+ if cycle_counter = 0 or cycle_counter = 1 then
+ ADC_CNV_OUT <= '1';
+ else
+ ADC_CNV_OUT <= '0';
+ end if;
+ end if;
+end process;
-
+PROC_INPUT : process begin
+ wait until rising_edge(CLK_ADCRAW);
+ data_reg <= data_reg(25 downto 0) & data_in(1 downto 0);
+ clock_reg <= clock_reg(25 downto 0) & data_in(3 downto 2);
+
+
+ if cycle_input = 13 then
+ cycle_input <= 0;
+ else
+ cycle_input <= cycle_input + 1;
+ end if;
+
+
+ if CONF_ALIGN_EN = '1' and data_reg(17 downto 0) = TESTPATTERN then
+ cycle_input <= 1;
+ data_shifted <= CONF_data_shifted;
+ elsif CONF_ALIGN_EN = '1' and data_reg(18 downto 1) = TESTPATTERN then
+ cycle_input <= 1;
+ data_shifted <= not CONF_data_shifted;
+ end if;
+
+ if data_in(3 downto 2) = "00" and cycle_input = 0 then
+ cycle_input <= 0;
+ end if;
+
+
+ if cycle_input = 10 then
+ data_reg_save <= data_reg;
+ clock_reg_save <= clock_reg;
+
+ if data_shifted = '0' then
+ DATA_OUT <= data_reg(17 downto 0);
+ DATA_VALID_OUT <= '1';
+ else
+ DATA_OUT <= data_reg(18 downto 1);
+ DATA_VALID_OUT <= '1';
+ end if;
+ end if;
+ if cycle_input = 11 then
+ DATA_VALID_OUT <= '0';
+ end if;
+
+
+
+end process;
+
+DEBUG_OUT(27 downto 0) <= data_reg_save;
+DEBUG_OUT(28) <= data_shifted;
+DEBUG_OUT(59 downto 32) <= clock_reg_save;
+
+
end architecture;
);
port(
CLK : in std_logic; -- 100 MHz
+ CLK_ADCBRAW : in std_logic; -- 200 MHz
CLK_ADCRAW : in std_logic; -- 350 MHz
RESET : in std_logic;
signal data_valid_a : std_logic;
signal debug_a : std_logic_vector(31 downto 0);
+ signal data_in_b : std_logic_vector(17 downto 0);
+ signal data_valid_b : std_logic;
+ signal debug_b : std_logic_vector(63 downto 0);
+
type adc_data_arr is array(0 to 4) of std_logic_vector(17 downto 0);
signal data_processor_in : adc_data_arr;
signal data_processor_valid: std_logic_vector(4 downto 0);
-- alias CONF_baseline_always_on : std_logic is basic_control(1);
alias CONF_del_direction : std_logic is basic_control(2);
alias CONF_del_loadn : std_logic is basic_control(3);
-
+ alias CONF_alignen_b : std_logic is basic_control(16);
+ alias CONF_testpat_b : std_logic is basic_control(17);
+ alias CONF_data_shifted_b : std_logic is basic_control(18);
+
signal CONF_input_select : std_logic_vector(31 downto 0) := x"21043210";
type config_arr_t is array(0 to ACTIVE_CHANNELS-1) of cfg_t;
DEBUG_OUT => debug_a
);
+THE_INPUT_B : entity work.adc_18bit_input
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ RESET_ADC => STROBE_reset_b,
+
+ CLK_ADCRAW => CLK_ADCBRAW,
+ ADC_DATA => DCO_B & DATA_B,
+
+ CONF_ALIGN_EN => CONF_alignen_b,
+ CONF_DATA_SHIFTED => CONF_data_shifted_b,
+ DEL_CFLAG => open,
+ DEL_DIRECTION => CONF_del_direction,
+ DEL_LOADN => CONF_del_loadn,
+ DEL_MOVE => STROBE_del_move_b,
+
+
+ ADC_CLK_OUT => CLK_B,
+ ADC_CNV_OUT => CNV_B,
+
+ DATA_OUT => data_in_b,
+ DATA_VALID_OUT => data_valid_b,
+ DEBUG_OUT => debug_b
+ );
+
+TESTPAT_B <= CONF_testpat_b;
-------------------------------------------------------------------------------
-- ADC Input Multiplexer
data_processor_valid(i) <= data_valid_a;
when x"3" => data_processor_in(i) <= x"0" & data_in_a((3+1)*14-1 downto 3*14);
data_processor_valid(i) <= data_valid_a;
- --case x"4" => data_processor_in <= data_in_b;
+ when x"4" => data_processor_in(i) <= data_in_b;
+ data_processor_valid(i) <= data_valid_b;
end case;
end process;
CONTROL => basic_control(15 downto 0),
CONFIG => config(i),
- PSA_DATA => psa_data,
- PSA_ADDR => psa_addr,
- PSA_WRITE => psa_write(i),
+ PSA_DATA => psa_data,
+ PSA_ADDR => psa_addr,
+ PSA_WRITE => psa_write(i),
PROC_REG_ADDR => proc_reg_addr,
PROC_REG_READ => proc_reg_read(i),
when x"11" => BUS_TX.data(13 downto 0) <= data_in_a(27 downto 14);
when x"12" => BUS_TX.data(13 downto 0) <= data_in_a(41 downto 28);
when x"13" => BUS_TX.data(13 downto 0) <= data_in_a(55 downto 42);
- when x"14" => BUS_TX.data <= debug_a;
+ when x"14" => BUS_TX.data(17 downto 0) <= data_in_b;
+ when x"18" => BUS_TX.data <= debug_a;
+ when x"19" => BUS_TX.data <= debug_b(31 downto 0);
+ when x"1a" => BUS_TX.data <= debug_b(63 downto 32);
when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
end case;
elsif BUS_RX.addr(11 downto 10) = "00" then --1,2,3
add_file -vhdl -lib work "./cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd"
add_file -vhdl -lib work "./cores/mulaccsub3/mulaccsub3.vhd"
add_file -vhdl -lib work "./cores/adc_pll/adc_pll.vhd"
+add_file -vhdl -lib work "./cores/adc_1ch_clk/adc_1ch_clk.vhd"
+add_file -vhdl -lib work "./cores/adc_1ch/adc_1ch_edited.vhd"
+
add_file -vhdl -lib work "./cores/input_4ch/input_4ch_edited.vhd"
add_file -vhdl -lib work "./source/adc_input.vhd"
+add_file -vhdl -lib work "./source/adc_18bit_input.vhd"
add_file -vhdl -lib work "./source/adc_processor.vhd"
add_file -vhdl -lib work "./source/adc_addon.vhd"
TESTPAT_B : out std_logic;\r
DCO_B : in std_logic;\r
DATA_B : in std_logic;\r
+ CNV_B : out std_logic;\r
\r
LEMO_OUT : out std_logic_vector(1 downto 0);\r
LEMO_OE : out std_logic_vector(1 downto 0);\r
)\r
port map(\r
CLK => clk_sys,\r
+ CLK_ADCBRAW => clk_full_osc,\r
CLK_ADCRAW => clk_350,\r
RESET => reset_i,\r
\r
DATA_A => DATA_A,\r
DCO_A => DCO_A,\r
\r
+ DCO_B => DCO_B, \r
+ DATA_B => DATA_B, \r
+ CLK_B => CLK_B, \r
+ CNV_B => CNV_B, \r
+ TESTPAT_B => TESTPAT_B,\r
+ \r
TRIGGER_OUT => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0),\r
READOUT_RX => readout_rx,\r
READOUT_TX => readout_tx,\r
LOCATE COMP "DATA_A_1" SITE "D30" ; #"FE_DIFF[19]"
LOCATE COMP "DATA_A_3" SITE "F30" ; #"FE_DIFF[20]"
LOCATE COMP "DATA_A_2" SITE "C32" ; #"FE_DIFF[21]"
-# LOCATE COMP "" SITE "F31" ; #"FE_DIFF[22]"
+# LOCATE COMP "CLK_A" SITE "F31" ; #"FE_DIFF[22]"
# LOCATE COMP "" SITE "F32" ; #"FE_DIFF[23]"
# LOCATE COMP "" SITE "H31" ; #"FE_DIFF[24]"
# LOCATE COMP "" SITE "J30" ; #"FE_DIFF[25]"
IOBUF PORT "DATA_A_2" IO_TYPE=LVDS DIFFRESISTOR=100 ;
IOBUF PORT "DATA_A_3" IO_TYPE=LVDS DIFFRESISTOR=100 ;
IOBUF PORT "DATA_B" IO_TYPE=LVDS DIFFRESISTOR=100 ;
+IOBUF PORT "DCO_B" IO_TYPE=LVDS DIFFRESISTOR=100 ;
IOBUF PORT "CLK_A" IO_TYPE=LVDS ;
IOBUF PORT "CLK_B" IO_TYPE=LVDS ;
IOBUF PORT "CNV_B" IO_TYPE=LVDS ;
jspc29 / trb5sc.git / commitdiff