*** empty log message ***

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index 9cb0445e666f0ae7db003c1e2e2041ff2ab8afd2..b7473300594257118ff230625b5a469828e00572 100644 (file)
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -114,7 +114,7 @@ entity trb_net16_endpoint_hades_full is
     REGIO_IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
     REGIO_IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0) := "000";
     REGIO_IDRAM_WR_IN         : in  std_logic := '0';
-    REGIO_ONEWIRE_INOUT       : inout std_logic;
+    REGIO_ONEWIRE_INOUT       : inout std_logic;  --temperature sensor
     REGIO_ONEWIRE_MONITOR_IN  : in  std_logic;
     REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
 

diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd
index 5b10554524c23e75b7aa4a17e61510876d2c37ad..a1a8764158cf8994027ddc349b0a884bb3597462 100644 (file)
--- a/trb_net16_io_multiplexer.vhd
+++ b/trb_net16_io_multiplexer.vhd
@@ -106,6 +106,11 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is
   signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
   signal sbuf_status : std_logic;
 
+  -- Placer Directives
+  attribute HGROUP : string;
+  -- for whole architecture
+  attribute HGROUP of trb_net16_io_multiplexer_arch : architecture  is "MUX_group";
+
   begin
 -------------------------------------------------------------------------------
 -- DEMUX

diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd
index 4afe5c9441da12300135dfd3187bd513f5fc6622..c7406b0d9f0827ce7e41268df50f83f500efd98a 100644 (file)
--- a/trb_net16_obuf.vhd
+++ b/trb_net16_obuf.vhd
@@ -234,7 +234,7 @@ begin
       current_ACK_word  <= (others => '0');
       current_EOB_word  <= (others => '0');
       current_DATA_word <= int_data_in_i;
-      if    transfer_counter = c_F0 then
+      if transfer_counter = c_F0 then
         current_EOB_word <= CRC;
         if saved_packet_type = TYPE_TRM and USE_CHECKSUM = c_YES then
           current_DATA_word <= CRC;

diff --git a/trb_net16_obuf_nodata.vhd b/trb_net16_obuf_nodata.vhd
index 318efe6e5f6dbf264631900a1f3ffc803d5eaf55..0ef217f86fb9920137e773b48d44cb07bb945b8e 100644 (file)
--- a/trb_net16_obuf_nodata.vhd
+++ b/trb_net16_obuf_nodata.vhd
@@ -37,7 +37,8 @@ architecture trb_net16_obuf_nodata_arch of trb_net16_obuf_nodata is
   signal reg_SEND_ACK_IN_2                             : std_logic;
   signal reg_SEND_ACK_IN                               : std_logic;
 
-
+  attribute syn_keep : boolean;
+  attribute syn_keep of buf_MED_DATAREADY_OUT : signal is true;
 
 begin
   SEND_BUFFER_SIZE_IN       <= CTRL_BUFFER(3 downto 0);

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index b2512519af2ef66b083a69d2e1ef55cfaef0b3e5..823549e370a4cdd86d6c7a015ae5ed5963cf558e 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -794,6 +794,46 @@ package trb_net_components is
 
 
 
+  component trb_net16_med_ecp_sfp_8bit_4 is
+    generic(
+      REVERSE_ORDER : integer range 0 to 1 := c_NO
+    --  USED_PORTS : std_logic-vector(3 downto 0) := "1111"
+      );
+    port(
+      CLK        : in  std_logic; -- SerDes clock
+      SYSCLK     : in  std_logic; -- fabric clock
+      RESET        : in  std_logic; -- synchronous reset
+      CLEAR        : in  std_logic; -- asynchronous reset
+      CLK_EN       : in  std_logic;
+      --Internal Connection
+      MED_DATA_IN        : in  std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_IN  : in  std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+      MED_DATAREADY_IN   : in  std_logic_vector(3 downto 0);
+      MED_READ_OUT       : out std_logic_vector(3 downto 0);
+      MED_DATA_OUT       : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+      MED_DATAREADY_OUT  : out std_logic_vector(3 downto 0);
+      MED_READ_IN        : in  std_logic_vector(3 downto 0);
+      REFCLK2CORE_OUT    : out std_logic;
+      --SFP Connection
+      SD_RXD_P_IN        : in  std_logic_vector(3 downto 0);
+      SD_RXD_N_IN        : in  std_logic_vector(3 downto 0);
+      SD_TXD_P_OUT       : out std_logic_vector(3 downto 0);
+      SD_TXD_N_OUT       : out std_logic_vector(3 downto 0);
+      SD_REFCLK_P_IN     : in  std_logic;
+      SD_REFCLK_N_IN     : in  std_logic;
+      SD_PRSNT_N_IN      : in  std_logic_vector(3 downto 0);
+      SD_LOS_IN          : in  std_logic_vector(3 downto 0);
+      SD_TXDIS_OUT       : out std_logic_vector(3 downto 0);
+      -- Status and control port
+      STAT_OP            : out  std_logic_vector (4*16-1 downto 0);
+      CTRL_OP            : in  std_logic_vector (4*16-1 downto 0);
+      STAT_DEBUG         : out  std_logic_vector (63 downto 0);
+      CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+      );
+  end component;
+
+
 
 
   component trb_net16_med_ecp_sfp_4 is
@@ -885,6 +925,7 @@ package trb_net_components is
     port(
       CLK      : in std_logic;
       RESET    : in std_logic;
+      READOUT_ENABLE_IN : in std_logic := '1';
       --connection to 1-wire interface
       ONEWIRE  : inout std_logic;
       MONITOR_OUT : out std_logic;

diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd
index a09522fd138cdaabb3ee27d549383968c57103c9..2f5945786cfc54e3e59d7eb8334859f04f70c343 100644 (file)
--- a/trb_net_onewire.vhd
+++ b/trb_net_onewire.vhd
@@ -16,6 +16,7 @@ entity trb_net_onewire is
   port(
     CLK      : in std_logic;
     RESET    : in std_logic;
+    READOUT_ENABLE_IN : in std_logic := '1';
     --connection to 1-wire interface
     ONEWIRE  : inout std_logic;
     MONITOR_OUT : out std_logic;
@@ -31,7 +32,7 @@ end entity;
 
 architecture trb_net_onewire_arch of trb_net_onewire is
   constant MAX_COUNTER : integer := 2**28-1;
-  type state_t is (IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT,
+  type state_t is (START, IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT,
                    WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP,
                    READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP);
   signal state, next_state : state_t;
@@ -92,6 +93,10 @@ begin
       next_strong_pullup <= '0';
       case state is
 --reset / presence
+        when START =>
+          if READOUT_ENABLE_IN = '1' then
+            next_state <= IDLE;
+          end if;
         when IDLE =>
           if is_time_reached(timecounter,640000,CLK_PERIOD) = '1' then
             next_state <= SEND_RESET;
@@ -178,18 +183,20 @@ begin
 
 --reading sensor answers
         when READ_CONV_TEMP => --waiting for end of conversion
-          if PARASITIC_MODE = c_NO then
-            if recv_bit = '1' then    --polling device for end of measurement
-              next_state <= IDLE;
-              if USE_TEMPERATURE_READOUT = 1 then
-                next_conv_temp <= '0';
-                next_reading_temp <= '1';
-              end if;
-            else
-              next_state <= READ_BIT;
+--           if PARASITIC_MODE = c_NO then
+--             if recv_bit = '1' then    --polling device for end of measurement
+--               next_state <= IDLE;
+--               if USE_TEMPERATURE_READOUT = 1 then
+--                 next_conv_temp <= '0';
+--                 next_reading_temp <= '1';
+--               end if;
+--             else
+--               next_state <= READ_BIT;
+--             end if;
+--           elsif PARASITIC_MODE = c_YES then --waiting 1.3s, then start reading
+            if PARASITIC_MODE = c_YES then
+              next_strong_pullup <= '1';
             end if;
-          elsif PARASITIC_MODE = c_YES then --waiting 1.3s, then start reading
-            next_strong_pullup <= '1';
             if is_time_reached(timecounter,130000000,CLK_PERIOD) = '1' then
               next_state <= IDLE;
               if USE_TEMPERATURE_READOUT = 1 then
@@ -197,7 +204,7 @@ begin
                 next_reading_temp <= '1';
               end if;
             end if;
-          end if;
+--           end if;
 
         when READ_READ_TEMP =>
           inc_bitcounter <= '1';