add adc reader to components, add new memory file

diff --git a/basics/ram_dp_19x8_preset.vhd b/basics/ram_dp_19x8_preset.vhd
new file mode 100644 (file)
index 0000000..6725f1a
--- /dev/null
+++ b/basics/ram_dp_19x8_preset.vhd
@@ -0,0 +1,44 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+entity ram_dp_19x8_preset is
+  generic(
+    depth : integer := 3;
+    width : integer := 20;
+    content : std_logic_vector_array_20(0 to 7) := (others => (others => '0'))
+    );
+  port(
+    CLK   : in  std_logic;
+    wr1   : in  std_logic;
+    a1    : in  std_logic_vector(depth-1 downto 0);
+    dout1 : out std_logic_vector(width-1 downto 0);
+    din1  : in  std_logic_vector(width-1 downto 0);
+    a2    : in  std_logic_vector(depth-1 downto 0);
+    dout2 : out std_logic_vector(width-1 downto 0)
+    );
+end entity;
+
+architecture ram_dp_arch of ram_dp_19x8_preset is
+  --type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0);
+  SIGNAL ram : std_logic_vector_array_20(0 to 7) := content;
+
+begin
+
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if wr1 = '1' then
+          ram(conv_integer(a1)) <= din1;
+        end if;
+        dout1 <= ram(conv_integer(a1));
+        dout2 <= ram(conv_integer(a2));
+      end if;
+    end process;
+
+end architecture;

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 9dd5cb8e87205fbca77492be576ce2fa9e41919b..c0c81c014c8ba0da463fe4a0ca7be74346865db9 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -7,7 +7,26 @@ use work.trb_net_std.all;
 \r
 package trb_net_components is\r
 \r
-\r
+component adc_controller is\r
+    generic (\r
+        CH1_CMD         : STD_LOGIC_VECTOR(19 downto 0) := x"1c3cb";\r
+        CH2_CMD         : STD_LOGIC_VECTOR(19 downto 0) := x"1d5cb";\r
+        CH3_CMD         : STD_LOGIC_VECTOR(19 downto 0) := x"2e3cb";\r
+        CH4_CMD         : STD_LOGIC_VECTOR(19 downto 0) := x"2f5cb";\r
+        TMP_CMD         : STD_LOGIC_VECTOR(19 downto 0) := x"1F393"\r
+    ); \r
+    port (\r
+        CLK       : in std_logic;\r
+        RST       : in std_logic;\r
+        BUS_RX    : in CTRLBUS_RX;\r
+        BUS_TX    : out CTRLBUS_TX;\r
+\r
+        ADC_CS    : out std_logic;\r
+        ADC_MOSI  : out std_logic;\r
+        ADC_MISO  : in  std_logic;\r
+        ADC_CLK   : out std_logic\r
+    );\r
+end component;\r
 \r
 --This list of components is sorted alphabetically, ignoring the trb_net or trb_net16 prefix of some component names\r
 component  gbe_wrapper is\r
@@ -2850,7 +2869,22 @@ end component;
   end component;\r
 \r
 \r
-\r
+  component ram_dp_19x8_preset is\r
+    generic(\r
+      depth : integer := 3;\r
+      width : integer := 20;\r
+      content : std_logic_vector_array_20(0 to 7) := (others => (others => '0'))\r
+      );\r
+    port(\r
+      CLK   : in  std_logic;\r
+      wr1   : in  std_logic;\r
+      a1    : in  std_logic_vector(depth-1 downto 0);\r
+      dout1 : out std_logic_vector(width-1 downto 0);\r
+      din1  : in  std_logic_vector(width-1 downto 0);\r
+      a2    : in  std_logic_vector(depth-1 downto 0);\r
+      dout2 : out std_logic_vector(width-1 downto 0)\r
+      );\r
+  end component;\r
 \r
   component trb_net16_regIO is\r
     generic (\r

diff --git a/trb_net_std.vhd b/trb_net_std.vhd
index c442f05c2d491e0b313a41dcb2418b315ddf4c58..5e5abf37c338ed41e01ae02b01f8b4a8a06051ff 100644 (file)
--- a/trb_net_std.vhd
+++ b/trb_net_std.vhd
@@ -260,6 +260,7 @@ package trb_net_std is
   type std_logic_vector_array_32 is array (integer range <>) of std_logic_vector(31 downto 0);
   type std_logic_vector_array_31 is array (integer range <>) of std_logic_vector(30 downto 0);
   type std_logic_vector_array_24 is array (integer range <>) of std_logic_vector(23 downto 0);
+  type std_logic_vector_array_20 is array (integer range <>) of std_logic_vector(19 downto 0);
   type std_logic_vector_array_11 is array (integer range <>) of std_logic_vector(10 downto 0);
   type std_logic_vector_array_8  is array (integer range <>) of std_logic_vector(7 downto 0);
   type int_array_t is array(integer range <>) of integer;