-The block of VHDL entities that provide the interface between the application (the ``user'') and the network is called endpoint. The top level entity is \filename{trb\_net16\_endpoint\_hades\_full.vhd} on almost all frontends. Here, a frontend is defined as a data-collecting FPGA that only has connections to one other FPGA. FPGAs with more than one connection are Hubs (E.g. the Shower AddOn contains two frontends and one hub).
+There are two different endpoints: The ``old'' one (\filename{trb\_\-net16\_\-endpoint\_\-hades\_\-full.vhd}) and a newer one including LVL1 trigger and IPU readout handling as well as all data buffers with full handling of all necessary information. Monitoring features of all hubs are included as well.
-The endpoint provides the logical interface for transporting data. Besides, one also needs a media interface entity that implements the logic needed to physically transport data from one FPGA to another. Which entity has to be used depends on the type of hardware. Its ports are all named \portname{Med\_*} and need no further description in this place.
-The majority of ports of the endpoint are used to interface all three channels on TrbNet, namely LVL1 trigger, IPU Data and Slow Control. The \portname{Stat\_*} and \portname{Ctrl\_*} ports are mainly used for debugging and can be left unconnected.
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{The Endpoint}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The block of VHDL entities that provide the interface between the application (the ``user'') and the network is called endpoint. The top level entity is \filename{trb\_\-net16\_\-end\-point\_\-hades\_\-full.vhd} on almost all frontends. Here, a frontend is defined as a data-collecting FPGA that only has connections to one other FPGA. FPGAs with more than one connection are Hubs (E.g. the Shower AddOn contains two frontends and one hub).
-The standard ports of the entity include a \portname{Clk} input (100MHz), a \portname{Reset} signal which is essential for the entity to work correctly and a \portname{Clk\_En}. The latter should be left unconncected despite there is a situation where the whole board whould be stopped.
+The endpoint provides the logical interface for transporting data. Besides, one also needs a media interface entity that implements the logic needed to physically transport data from one FPGA to another. Which entity has to be used depends on the type of hardware. Its ports are all named \portname{Med\_\-*} and need no further description in this place.
-\subsection{Generic Settings}
+The majority of ports of the endpoint are used to interface all three channels on TrbNet, namely LVL1 trigger, IPU Data and Slow Control. The \portname{Stat\_\-*} and \portname{Ctrl\_\-*} ports are mainly used for debugging and can be left unconnected.
+
+The standard ports of the entity include a \portname{Clk} input (100MHz), a \portname{Reset} signal which is essential for the entity to work correctly and a \portname{Clk\_\-En}. The latter should be left unconncected despite there is a situation where the whole board whould be stopped.
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{Generic Settings}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
The endpoint features many generic settings to configure the behaviour for the users needs. Most of them should be kept at there default value and are not described here.
The global settings for the endpoint are:
\begin{description}
- \item[\portname{Clock\_Frequency}] The frequency of the main clock in MHz. Normally 100 MHz.
- \item[\portname{Address\_Mask}] The address mask used for replacement boards. See section \ref{ReplacementAddresses}
- \item[\portname{Broadcast\_Bitmask}] The lower 8 bit of the specific broadcast address. See section \ref{BroadcastAddresses}
- \item[\portname{Regio\_Init\_Address}] The initial network address. Should be a number above 0xF000.
- \item[\portname{Regio\_Init\_Board\_Info}] 32bit word to give information about the board type, hardware version etc. Bits can be defined by user.
- \item[\portname{Regio\_Init\_Endpoint\_Id}] The number of the FPGA on the board. For boards with one single FPGA 1.
- \item[\portname{Regio\_Compile\_Time}] Unix timestamp when the design has been synthesized. There is an automatic perl script available that generates this value, but the user has to care about this.
- \item[\portname{Regio\_Compile\_Version}] Version number of the design. Definition is up to user.
- \item[\portname{Regio\_Hardware\_Version}] Version number of the hardware. Definition is up to user.
+ \item[\portname{Clock\_\-Frequency}] The frequency of the main clock in MHz. Normally 100 MHz.
+ \item[\portname{Address\_\-Mask}] The address mask used for replacement boards. See section \ref{ReplacementAddresses}
+ \item[\portname{Broadcast\_\-Bitmask}] The lower 8 bit of the specific broadcast address. See section \ref{BroadcastAddresses}
+ \item[\portname{Regio\_\-Init\_\-Address}] The initial network address. Should be a number above 0xF000.
+ \item[\portname{Regio\_\-Init\_\-Board\_\-Info}] 32bit word to give information about the board type, hardware version etc. Bits can be defined by user.
+ \item[\portname{Regio\_\-Init\_\-Endpoint\_\-Id}] The number of the FPGA on the board. For boards with one single FPGA 1.
+ \item[\portname{Regio\_\-Compile\_\-Time}] Unix timestamp when the design has been synthesized. There is an automatic perl script available that generates this value, but the user has to care about this.
+ \item[\portname{Regio\_\-Compile\_\-Version}] Version number of the design. Definition is up to user.
+ \item[\portname{Regio\_\-Hardware\_\-Version}] Version number of the hardware. Definition is up to user.
\end{description}
-\subsection{Common Error and Status Bits}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{The Full Endpoint Including Data Handlers}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{Generic Settings}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+ \begin{description}
+ \item[\portname{Address\_\-mask}] Mask applied on network addresses to account for changed addresses when a board gets replaced. This mask should be choosen in a way that allows to address the board with any of the available replacement addresses. The board will always answer with its actual network address.
+ \item[\portname{Broadcast\_\-bitmask}] The mask applied on the network address used in broadcast messages. See table \ref{BroadcastAddresses} for details.
+ \item[\portname{Regio\_\-num\_\-stat\_\-regs}] The number of status registers. The given value is interpreted as the $log_2$ of registers. Due to the assigned address space, the maximum number is 6 ($=2^6=64$ registers).
+ \item[\portname{Regio\_\-num\_\-ctrl\_\-regs}] The number of control registers. The given value is interpreted as the $log_2$ of registers. Due to the assigned address space, the maximum number is 6 ($=2^6=64$ registers).
+ \item[\portname{Regio\_\-init\_\-ctrl\_\-regs}] The initial value of all user defined control registers. The width of this generic is always $2^6\cdot32 = 2048$ bit, no matter how \portname{Regio\_\-num\_\-ctrl\_\-regs} is set.
+ \item[\portname{Regio\_\-init\_\-address}] The initial network address of the board. Should always be set to a value higher than 0xF000 but lower than 0xFF00. N.B.: This value is currently ignored by the Linux toolchain on Lattice devices.
+ \item[\portname{Regio\_\-init\_\-board\_\-info}] The value to store in the board information register. This register has not yet been defined.
+ \item[\portname{Regio\_\-init\_\-endpoint\_\-id}] The endpoint id. Typically a number counting the FPGAs on one PCB (more precise: counting the FPGA connected to one temperature sensor) starting with 1. Exception: The FPGA responsible for readout mostly gets the endpoint id 0.
+ \item[\portname{Regio\_\-compile\_\-time}] The unix time stamp when the design has been compiled.
+ \item[\portname{Regio\_\-compile\_\-version}] A version number defining the version of code. No global definition has been made.
+ \item[\portname{Regio\_\-hardware\_\-version}] The type of hardware. See table \ref{HardwareInformation} for details.
+ \item[\portname{Regio\_\-use\_\-1wire\_\-interface}] Selects which type of 1-wire interface to use. Values are c\_\-No (no 1-wire interface), c\_\-Yes (1-wire chip is connected directly to this FPGA) or c\_\-Monitor (1-wire chip is connected to another FPGA with the 1-wire monitor output connected to this FPGA)
+ \item[\portname{Regio\_\-use\_\-var\_\-endpoint\_\-id}] If set to c\_\-Yes, the generic \portname{Regio\_\-init\_\-endpoint\_\-id} is ignored and the port \portname{Regio\_\-var\_\-endpoint\_\-id} is used instead to select the endpoint id of the FPGA.
+ \item[\portname{Clock\_\-frequency}] Sets the clock frequency of the design which is needed for time measurements. The value is given in MHz.
+ \item[\portname{Data\_\-interface\_\-number}] The number of data interfaces on the data handler. Selects how many parallel fifos are provided by the endpoint.
+ \item[\portname{Data\_\-buffer\_\-depth}] The depth of the data fifos. The given value is interpreted as the $log_2$ of words that can be stored in the fifo. Currently, valid values reach from 8 to 15.
+ \item[\portname{Data\_\-buffer\_\-width}] The width of the data fifos. Currently, only a width of 32 bit is available.
+ \item[\portname{Data\_\-buffer\_\-full\_\-thresh}] The threshold on the fill level at which the buffers report to be ``almost full''. This value has to be set to be at least the size of one maximum sized event lower than the total depth of the fifo (if \portname{Trg\_\-release\_\-after\_\-data} is set to c\_\-Yes) or two maximum sized events lower than the total depth in case \portname{Trg\_\-release\_\-after\_\-data} is set to c\_\-No.
+ \item[\portname{Trg\_\-release\_\-after\_\-data}] Selects the behaviour of the busy release given by the buffers. If set to c\_\-No, the busy release from the buffer is given immediately after the trigger has been received - the user has full control over the busy release sent to the CTS. If set to c\_\-Yes, the release is given after all data inputs finished writing data to the buffers. Please note the influence of this setting on the full threshold of the buffers.
+ \item[\portname{Header\_\-buffer\_\-depth}] The depth of the LVL1 information buffer. I.e. the maximum number of events that the endpoint should be able to store before readout. The given value is interpreted as the $log_2$ of words that can be stored in the fifo. Currently, valid values reach from 8 to 11.
+ \item[\portname{Header\_\-buffer\_\-full\_\-thresh}] The ``almost full'' threshold on the fill level of the LVL1 information fifo.
+ \end{description}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{Ports}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+ \begin{description}
+ \item[\portname{Med*}] The connection to the media interface. For a description of these ports please see the (not yet existing) section about media interfaces.
+ \item[\portname{Lvl1*}] The information about timing triggers and LVL1 triggers received is exchanged between the endpoint and the user logic. See section \ref{channel0} for details.
+
+ \item[\portname{Fee\_\-trg\_\-release\_\-in}] The busy release signal from the FEE. One port for each data interface.
+ \item[\portname{Fee\_\-trg\_\-statusbits\_\-in}] The statusbits sent on the LVL1 trigger channel. Input is read by the endpoint when \portname{Fee\_\-trg\_\-release\_\-in} is high. One 32 bit port for each data interface.
+ \item[\portname{Fee\_\-data\_\-in}] The data to be stored in the data buffer. Input is written to buffer when \portname{Fee\_\-data\_\-write\_\-in} is high. One 32 bit port for each data interface.
+ \item[\portname{Fee\_\-data\_\-write\_\-in}] Write strobe to store data inside the data buffer. One port for each data interface.
+ \item[\portname{Fee\_\-data\_\-finished\_\-in}] Strobe signal generated by the user after the last data word of one event has been filled into the buffer. One port for each data interface.
+ \item[\portname{Fee\_\-data\_\-almost\_\-full\_\-out}] The data buffer reports to be almost full. The user can ignore this signal since all necessary actions are already taken care for by the endpoint itself. The user will always be able to finish the current event and no further lvl1 triggers will be sent by the CTS until the buffers are not almost full any more. One port for each data interface.
+
+ \item[\portname{Regio\_\-common*}] The common status and control registers. See section \ref{RegIORegisters} for details.
+ \item[\portname{Regio\_\-stat*}] The user defined status registers. See section \ref{RegIORegisters} for details.
+ \item[\portname{Regio\_\-ctrl*}] The user defined control registers. See section \ref{RegIORegisters} for details.
+
+ \item[\portname{Bus*}] The internal slow control data bus. Here, only addresses above 0x8000 are available. For details, see section \ref{RegIORegisters} for details on the internal data bus.
+
+ \item[\portname{Onewire*}] Connection to the onboard 1-wire device or from / to the monitor in-/output of another FPGA
+ \item[\portname{Regio\_\-var\_\-end\-point\_\-id}] The variable endpoint id. Used only if \portname{Regio\_\-use\_\-var\_\-end\-point\_\-id} is set to c\_\-Yes.
+
+ \item[\portname{Time*}] The registers for global and local timer, the time since last trigger and timer ticks each microsecond (bit 0 of \portname{Time\_\-Ticks\_\-Out}) and millisecond (bit 1 of \portname{Time\_\-Ticks\_\-Out}). For details, see section \ref{RegIORegisters}.
+ \end{description}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{Notes}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\begin{itemize}
+ \item The data ports are always read (and sent on the IPU channel) in order. That means, data interface 0 is the first to be sent, afterwards 0 and so on. Data Interfaces with a length of 0 are skipped.
+ \item If you want to add a debug header in front of the data, you can simply specify one more data port than needed for the real data and feed the header into data interface 0. Likewise, a trailer can be added by writing to the uppermost data interface
+ \item If the readout is controlled by one central instance, the not needed \portname{Fee\_\-trg\_\-*} can be set to fixed values as long as at least one input is used with the correct behaviour. The unused \portname{Fee\_\-trg\_\-release\_\-in} should be kept at '1' and the corresponding \portname{Fee\_\-trg\_\-statusbits\_\-in} should be kept at all bits set to 0.
+\end{itemize}
+
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{Slowcontrol Registers}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+All endpoint monitoring and status registers can be found in the address region between 0x7000 and 0x7FFF according to table \ref{endpointhandlerregister}.
+
+\begin{table}[htbp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|c|C|}
+\hline
+\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
+7100 - 710F & Data Buffer Status & Status of the data buffers, one register for each data buffer defined \\
+7110 & LVL1 Buffer Status & Status of the LVL1 header / data buffer \\
+\hline
+\end{tabularx}
+\caption{Register Map of the full endpoint containing data handlers.}
+\label{endpointhandlerregister}
+\end{center}
+\end{table}
+
+\begin{description}
+ \item[Data Buffer Status] The registers 0x7100 to 0x710F give status information about each of the data buffers. The exact amount of available registers depends on the number of data interfaces set in the entities generics. The bits inside each register are defined as shown in table \ref{endpointbufferstatus}. The status of the fifo holding the length of each event in each buffer is only briefly shown. Normally, the state machine forces the fill level of all length fifos and the LVL1 header fifo to be equal.
+ \item[LVL1 Buffer Status] The register 0x7110 gives status information about the LVL1 header buffer. The bit definition is the same as for register 0x7100 given in table \ref{endpointbufferstatus}. Here, the bits referring to the length buffers are not defined and will always read as 0.
+\end{description}
+
+\begin{table}[htbp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|C|}
+\hline
+\textbf{Bit} & \textbf{Description} \\
+\hline\hline
+15 - 0 & The current fill level of the fifo. The value is the number of words currently stored in the fifo\\
+16 & Buffer is empty\\
+17 & Buffer is almost full\\
+18 & Buffer is completely full (this is an error flag - if set, something went wrong)\\
+19 & Buffer write strobe \\
+20 & Buffer control state machine is idle, waiting for trigger\\
+21 & Buffer control state machine is busy, waiting for data, writing to buffer\\
+22 & Buffer control state machine is waiting for busy release, the data input has already been closed\\
+23 & reserved \\
+24 & Length fifo is empty\\
+25 & Length fifo is almost full\\
+26 & Length fifo is full (this is an error flag - if set, something went wrong) \\
+27 & Length fifo write strobe\\
+31 - 28 & reserved\\
+\hline
+\end{tabularx}
+\caption{Definition of bits in registers 0x7100++}
+\label{endpointbufferstatus}
+\end{center}
+\end{table}
+
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\section{Common Error and Status Bits}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
For each transmission there are 32 bits that give a rough overview of the status of the boards and transport error information. The meaning of the upper 16 bit depends on the channel while the lower 16 bit are the same on all channels. Their meaning is given in table \ref{commonerrorbits}. From these bits, only bit 4 can be set by the user, the rest is generated inside the network.
\begin{table}
\begin{center}
-\begin{tabularx}{\textwidth}{c|c|C}
+\begin{tabularx}{\textwidth}{|c|c|C|}
+\hline
\textbf{Bits} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
0 & endpoint reached & At least one endpoint has been addressed by the transfer. If not set, no endpoint with the given address exists in the network. \\
1 & collision detected & Used in the (theoretical) case that two active endpoints send data at the same time. The initial transfer this reply belongs to has been lost. \\
2 & word missing & There was a mismatch between an internal packet counter and the length transported in an EOB packet.\\
5 & buffer mismatch & The numbers of sent EOB and received ACK do not match. \\
6 & answer missing & An endpoint connected to a hub did not send an answer. \\
7 - 15 & t.b.d & Bits not yet used. Reserved. \\
+\hline
\end{tabularx}
\caption{Common Error- and Status information contained in the network termination packet on all channels}
\label{commonerrorbits}
\end{center}
\end{table}
-
-
-
+\label{channel0}
\subsection{Trigger Procedure Overview}
In the new system each trigger consists of to separated events: First, a timing trigger is received on the dedicated trigger input which delivers accurate timing information and starts the readout cycle.
\end{figure}
\begin{description}
- \item [Lvl1\_Trg\_Type\_Out] The trigger type, similar to the old system.
- \item [Lvl1\_Trg\_Received\_Out] Rising edge marks that a LVL1 trigger information has been received. Falling edge comes after user set \portname{Lvl1\_Trg\_Release}. While high, \portname{Lvl1\_\-Trg\_\-Type}, \portname{Lvl1\_\-Trg\_Number}, \portname{Lvl1\_\-Trg\_\-Code} and \portname{Lvl1\_\-Trg\_\-In\-for\-mation} are valid.
- \item [Lvl1\_Trg\_Number\_Out] (16 bit) Trigger number.
- \item [Lvl1\_Trg\_Code\_Out] (8 bit) A random code generated by CTS that has to be stored and put to the IPU data stream.
- \item [Lvl1\_Trg\_Information\_Out] (24 bit) Additional information about trigger as explained in the corresponding section.
- \item [Lvl1\_Error\_Pattern\_In] (32 bit) Error and status bits as explained in the corresponding section. Must be valid when \portname{Lvl1\_\-Trg\_\-Release} is high.
- \item [Lvl1\_Trg\_Release\_In] Must be set for at least one clock cycle to release the trigger (comparable to the old ``busy release'').
- \item [Lvl1\_Int\_Trg\_Number\_Out] (16 bit) The internal trigger counter counting the received timing triggers. Will be valid 5 clock cycles after a timing trigger has been received until \portname{Lvl1\_\-Trg\_\-Received} goes down.
- \item [Trigger\_Monitor\_In] Here are pulse for each received timing trigger has to be connected. This allows the endpoint to generate the \portname{Lvl1\_Int\_Trg\_Number\_Out}.
+
+ \item [\portname{Lvl1\_valid\_timing\_trg\_out}] A timing trigger has been received and the internal state machine marked it as valid. Typically set 2 to 5 clock cycles after \portname{trg\_timing\_trg\_received\_in} was high.
+ \item [\portname{Lvl1\_valid\_notiming\_trg\_out}] A valid timing-trigger-less LVL1 trigger has been received. Typically high 1 to 2 clock cycles after the rising edge of \portname{Lvl1\_trg\_data\_valid\_out}.
+ \item [\portname{Lvl1\_invalid\_trg\_out}] A trigger (either timing trigger or LVL1 trigger) has been received which has been marked invalid by the internal state machine. E.g. to timing triggers without a LVL1 trigger or a LVL1 trigger without preceeding timing trigger has been detected.
+ \item [\portname{Lvl1\_trg\_type\_out}] The trigger type, similar to the old system.
+ \item [\portname{Lvl1\_trg\_data\_valid\_out}] Rising edge marks that a LVL1 trigger information has been received. Falling edge comes after user set \portname{Lvl1\_Trg\_Release}. While high, \portname{Lvl1\_\-Trg\_\-Type}, \portname{Lvl1\_\-Trg\_Number}, \portname{Lvl1\_\-Trg\_\-Code} and \portname{Lvl1\_\-Trg\_\-In\-for\-mation} are valid.
+ \item [\portname{Lvl1\_trg\_number\_out}] (16 bit) Trigger number.
+ \item [\portname{Lvl1\_trg\_code\_out}] (8 bit) A random code generated by CTS that has to be stored and put to the IPU data stream.
+ \item [\portname{Lvl1\_trg\_information\_out}] (24 bit) Additional information about trigger as explained in the corresponding section.
+ \item [\portname{Lvl1\_error\_pattern\_in}] (32 bit) Error and status bits as explained in the corresponding section. Must be valid when \portname{Lvl1\_\-Trg\_\-Release} is high.
+ \item [\portname{Lvl1\_trg\_release\_in}] Must be set for at least one clock cycle to release the trigger (comparable to the old ``busy release'').
+ \item [\portname{Lvl1\_int\_trg\_number\_out}] (16 bit) The internal trigger counter counting the received timing triggers. Will be valid 5 clock cycles after a timing trigger has been received until \portname{Lvl1\_\-Trg\_\-Received} goes down.
+ \item [\portname{trg\_timing\_trg\_received\_in}] Here are pulse for each received timing trigger has to be connected. This allows the endpoint to generate the \portname{Lvl1\_Int\_Trg\_Number\_Out}.
\end{description}
\subsection{Status and Error Bits}
\begin{table}
\begin{center}
-\begin{tabularx}{\textwidth}{c|C|C|C}
+\begin{tabularx}{\textwidth}{|c|C|C|C|}
+\hline
\textbf{Bits} & \textbf{Phys. Trigger} & \textbf{Ped. Trigger} & \textbf{Calib. Trigger} \\
+\hline\hline
9 - 0 & ADC Data & Pedestal value & ADC Data \\
-11 - 10 & \multicolumn{3}{c}{---} \\
-16 - 12 & \multicolumn{3}{c}{Column} \\
-19 - 17 & \multicolumn{3}{c}{---} \\
-24 - 20 & \multicolumn{3}{c}{Row} \\
-27 - 25 & \multicolumn{3}{c}{---} \\
-29 - 28 & \multicolumn{3}{c}{Plane (0: Pre, 1: P1, 2: P2)} \\
-30 & \multicolumn{3}{c}{---} \\
-31 & \multicolumn{3}{c}{0: normal data, 1: debug/status word} \\
-
+11 - 10 & \multicolumn{3}{c|}{---} \\
+16 - 12 & \multicolumn{3}{c|}{Column} \\
+19 - 17 & \multicolumn{3}{c|}{---} \\
+24 - 20 & \multicolumn{3}{c|}{Row} \\
+27 - 25 & \multicolumn{3}{c|}{---} \\
+29 - 28 & \multicolumn{3}{c|}{Plane (0: Pre, 1: P1, 2: P2)} \\
+30 & \multicolumn{3}{c|}{---} \\
+31 & \multicolumn{3}{c|}{0: normal data, 1: debug/status word} \\
+\hline
\end{tabularx}
\caption{The shower data format (as seen in software and detector hardware)}
\label{showerdatanormal}
\begin{table}
\begin{center}
-\begin{tabularx}{\textwidth}{c|C|C|C}
+\begin{tabularx}{\textwidth}{|c|C|C|C|}
+\hline
\textbf{Bits} & \textbf{Phys. Trigger} & \textbf{Ped. Trigger} & \textbf{Calib. Trigger} \\
+\hline\hline
9 - 0 & ADC Data & Pedestal value & ADC Data \\
-11 - 10 & \multicolumn{3}{c}{---} \\
-16 - 12 & \multicolumn{3}{c}{Column} \\
-19 - 17 & \multicolumn{3}{c}{---} \\
-22 - 20 & \multicolumn{3}{c}{ADC Channel} \\
-23 & \multicolumn{3}{c}{ADC Number (counted per FPGA) divided by 3} \\
-24 & \multicolumn{3}{c}{FPGA number (hardcoded, also used for address assignment)} \\
-27 - 25 & \multicolumn{3}{c}{---} \\
-29 - 28 & \multicolumn{3}{c}{ADC Number modulo 3} \\
-30 & \multicolumn{3}{c}{---} \\
-31 & \multicolumn{3}{c}{0: normal data, 1: debug/status word} \\
-
+11 - 10 & \multicolumn{3}{c|}{---} \\
+16 - 12 & \multicolumn{3}{c|}{Column} \\
+19 - 17 & \multicolumn{3}{c|}{---} \\
+22 - 20 & \multicolumn{3}{c|}{ADC Channel} \\
+23 & \multicolumn{3}{c|}{ADC Number (counted per FPGA) divided by 3} \\
+24 & \multicolumn{3}{c|}{FPGA number (hardcoded, also used for address assignment)} \\
+27 - 25 & \multicolumn{3}{c|}{---} \\
+29 - 28 & \multicolumn{3}{c|}{ADC Number modulo 3} \\
+30 & \multicolumn{3}{c|}{---} \\
+31 & \multicolumn{3}{c|}{0: normal data, 1: debug/status word} \\
+\hline
\end{tabularx}
\caption{The shower data format as seen from a readout-hardware point of view}
\label{showerdatahardware}
\begin{table}[hbtp]
\begin{center}
-\begin{tabularx}{\textwidth}{l|l|X}
+\begin{tabularx}{\textwidth}{|l|l|X|}
+\hline
\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
A000 - ABFF & Thresh./Ped. Mem.& Memory for pedestal and threshold values, see table \ref{ShowerADCMemory} \\
D000 & SPI Status Reg. & see section SPI Flash \\
D001 & SPI Control Reg. & see section SPI Flash \\
D100 - D13F & SPI Data Mem. & see section SPI Flash \\
E000 & Spy Fifo & Fifo for debugging signals \\
+\hline
\end{tabularx}
\caption{Memory map for FPGA 1 and 2 on Shower AddOn2}
\label{ShowerADCFPGAMemoryMap}
\begin{table}[htbp]
\begin{center}
-\begin{tabularx}{\textwidth}{l|l|X}
+\begin{tabularx}{\textwidth}{|l|l|X|}
+\hline
\textbf{Address Bit} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
4 - 0 & Column & Column of detector \\
7 - 5 & Channel & ADC Channel \\
8 & Ped/Thresh & 1: pedestals, 0: thresholds \\
11 - 9 & ADC & ADC Number \\
+\hline
\end{tabularx}
\caption{Memory map for ADC pedestals and thresholds on Shower AddOn2}
\label{ShowerADCMemory}
\subsection{User Interface}
The ports on the user interface can be divided into several sets:
\paragraph{Registers}
+\label{RegIORegisters}
There are four types of registers provided by RegIO: Common registers that are defined for all boards in the same way and user specific resgisters. These two sets are further divided into status registers that can be written by the internal logic and control registers that can be written over the network. The registers have a size of 32 bits each. The number of user registers in each of the four groups can be set using generics (see \ref{regiogenerics}).
For each register there is a strobe signal that shows read access (in case of status register) or write access (in case of control registers) from the network side. The following listing shows the name of all ports:
\begin{lstlisting}
Regio_Common_Stat_Reg_In (std_comstatreg*32-1 downto 0)
Regio_Common_Ctrl_Reg_Out (std_comctrlreg*32-1 downto 0)
-Regio_Registers_In (32*2**(num_stat_regs)-1 downto 0)
-Regio_Registers_Out (32*2**(num_ctrl_regs)-1 downto 0)
+Regio_Stat_Reg_In (32*2**(num_stat_regs)-1 downto 0)
+Regio_Ctrl_Reg_Out (32*2**(num_ctrl_regs)-1 downto 0)
-Common_Stat_Reg_Strobe(std_comstatreg-1 downto 0)
-Common_Ctrl_Reg_Strobe(std_comctrlreg-1 downto 0)
-Stat_Reg_Strobe(2**(num_stat_regs)-1 downto 0)
-Ctrl_Reg_Strobe(2**(num_ctrl_regs)-1 downto 0)
+Regio_Common_Stat_Strobe(std_comstatreg-1 downto 0)
+Regio_Common_Ctrl_Strobe(std_comctrlreg-1 downto 0)
+Regio_Stat_Strobe(2**(num_stat_regs)-1 downto 0)
+Regio_Ctrl_Strobe(2**(num_ctrl_regs)-1 downto 0)
\end{lstlisting}
\begin{table}[htbp]
\begin{center}
-\begin{tabularx}{\textwidth}{c|c|C}
-\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+\begin{tabularx}{\textwidth}{|c|c|C|}
\hline
+\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
00 & common status register 0 & Basic Error Flags and Temperature (see below) (r) \\
01 & common status register 1 & LVL1 trigger number (Bits 15..0), timing Trigger number (Bits 31..16) (r) \\
20 & common control register 0 & Strobes for board resets and test triggers (see below) (w)\\
51 & time since trigger & Time since last timing trigger (r)\\
80 - BF & user status registers & User status registers \\
C0 - FF & user control registers & User control registers \\
-0100 - 7FFF & reserved & Reserved addresses on internal data port (e.g. for monitoring and other features)\\
+0100 - 6FFF & reserved & Reserved addresses on internal data port (e.g. for monitoring and other features)\\
+7000 - 7FFF & endpoint monitoring & Monitoring Registers for Endpoint\\
8000 - FFFF & user defined & User defined address space on the internal data bus \\
+\hline
\end{tabularx}
\caption{Register Map of the Slow Control Endpoint.}
\label{regioaddressmap}
\begin{table}[htbp]
\begin{center}
-\begin{tabularx}{\textwidth}{c|c|C}
-\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+\begin{tabularx}{\textwidth}{|c|c|C|}
\hline
+\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
A000 - CFFF & FEE & Thresholds, Pedestals, Frontend settings \\
D000 - D13F & Flash & Control for SPI Flashes \\
E000 - FFFF & Debugging & Memories and Registers for Debugging \\
+\hline
\end{tabularx}
\caption{Register Map of the Slow Control Endpoint. Suggested usage of the user defined registers.}
\label{regioaddressmapsuggested}
\begin{table}
\begin{center}
-\begin{tabular}{c|c}
-\textbf{Bits} & \textbf{Description} \\
+\begin{tabular}{|c|c|}
\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
0 & serious error flag \\
1 & error flag \\
2 & warning flag \\
4 & LVL1 trigger counter mismatch \\
5 & IPU channel counter mismatch \\
20 - 31 & temperature \\
+\hline
\end{tabular}
\caption{Common Status Register 0}
\label{CommonStatReg0}
\begin{table}
\begin{center}
-\begin{tabular}{c|c}
-\textbf{Bits} & \textbf{Description} \\
+\begin{tabular}{|c|c|}
\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
0 & reset frontends \\
1 & reset trigger logic \\
2 & empty IPU chain / reset IPU logic \\
15 & reboot FPGA \\
16 - 23 & dummy timing triggers \\
24 - 31 & user defined \\
+\hline
\end{tabular}
\caption{Common Control Register 0}
\label{CommonCtrlReg0}
6220 & Hub AddOn version 2 FPGA 2 without GbE\\
6221 & Hub AddOn version 2 FPGA 2 with GbE\\
7300 & PEXOR version 3 \\
-8000 & TRB (purpose not defined)\\
+8000 & TRB using TDC readout (purpose not defined)\\
8100 & TOF TRB \\
8200 & Start/Veto TRB \\
8300 & RPC TRB \\
+8800 & Other TRB \\
\hline
\end{tabularx}
-\caption{Upper 16 bit in register 0x42 marking the hardware the design is belonging to. The value can be set by a generic value of the TrbNet endpoint. The lower 16bit are not globally defined.}
+\caption{Upper 16 bit in register 0x42 marking the hardware the design is belonging to. The value can be set by a generic value (\genericname{Regio\_Hardware\_Version}) of the TrbNet endpoint. The lower 16bit are not globally defined.}
\label{HardwareInformation}
\end{center}
\end{table}
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