+ project structure - unnessesary include directives

diff --git a/firmware/src/CB_functions.c b/firmware/src/CB_functions.c
index 12a1640ad465eaf1d724b24bc708c2928c95c9d9..bfd3e7a54e09b48db5957f13eaec92340dffd5c7 100644 (file)
--- a/firmware/src/CB_functions.c
+++ b/firmware/src/CB_functions.c
@@ -7,8 +7,8 @@
  */
 
 #include "CB_functions.h"
-
 #include "periph_conf.h"
+#include "stm32f10x_conf.h"
 
 
 

diff --git a/firmware/src/CB_functions.h b/firmware/src/CB_functions.h
index 2a2d6790d91ed7db386169489e1d8c837ae6c1dd..b8c7b5a5085f5bedf280e2f0382d97eef5be7f7b 100644 (file)
--- a/firmware/src/CB_functions.h
+++ b/firmware/src/CB_functions.h
@@ -7,9 +7,6 @@
  */
 
 #include "stm32f10x.h"
-#include "stm32f10x_conf.h" // contains all std periph includes
-#include "core_cm3.h"
-// #include "stm32f10x_it.h"
 
 
 void init_CB_GPIO_Outputs(void);

diff --git a/firmware/src/Makefile b/firmware/src/Makefile
index 174d4e731360fc4882bad1070b1d8252557c5231..24959973762104e6661b5208b91f395eb2160203 100644 (file)
--- a/firmware/src/Makefile
+++ b/firmware/src/Makefile
@@ -8,6 +8,7 @@ OBJS+=stm32f10x_it.o
 OBJS+=periph_conf.o
 OBJS+=CB_functions.o
 OBJS+=usart1.o
+OBJS+=spi2.o
 
 # OBJS+=keypins.o
 

diff --git a/firmware/src/main.c b/firmware/src/main.c
index 658d4659de1bcf6f2b1dce3b588fd031bb645724..df5932f44b03e76111facddc4038221250847959 100644 (file)
--- a/firmware/src/main.c
+++ b/firmware/src/main.c
@@ -15,16 +15,19 @@
 #include "newlib_stubs.c"
 #include "CB_functions.h"
 #include "usart1.h"
+#include "spi2.h"
 
 
 #define UC_NO_REGS 17
 
+
+extern uint16_t SPIBuffer[];
+
 GPIO_InitTypeDef GPIO_InitStructure;
 NVIC_InitTypeDef NVIC_InitStructure;
 SPI_InitTypeDef SPI_InitStructure;
 USART_InitTypeDef USART_InitStructure;
 DMA_InitTypeDef DMA_InitStructure;
-uint16_t SPIBuffer[] = {0xAAAA, 0xAAAA, 0xAAAA};
 
 uint16_t uC_regs[UC_NO_REGS];
 
@@ -35,9 +38,7 @@ void SysTick_Handler(void);
 
 void disable_JTAG(void);
 
-void init_SPI2(void);
 
-void spi_dma_shovel(void);
 
 
 
@@ -83,8 +84,8 @@ int main(int argc, char *argv[]) {
   
   init_SPI2();
 
-  SPIBuffer[0] = 0x1234;
-  SPIBuffer[1] = 0x5678;
+//   SPIBuffer[0] = 0x1234;
+//   SPIBuffer[1] = 0x5678;
   
   init_USART1();
   
@@ -97,115 +98,6 @@ int main(int argc, char *argv[]) {
 }
 
 
-void spi_dma_shovel(void) {
-
-
-  
-//   DMA_Cmd(DMA1_Channel4, DISABLE);
-  DMA_Cmd(DMA1_Channel5, DISABLE);
-//   DMA_SetCurrDataCounter(DMA1_Channel4, 2);
-  DMA_SetCurrDataCounter(DMA1_Channel5, 2);
-  
-  // Chip Select Low
-//   GPIO_WriteBit(GPIOB, GPIO_Pin_12, RESET);
-  CB_GPIO_Out_Lo(UC_CS);     // spi nCS -> idle Hi
-  
-//   DMA_Cmd(DMA1_Channel4, ENABLE);
-  DMA_Cmd(DMA1_Channel5, ENABLE);
-}
-
-
-
-void init_SPI2(void) {
-  // configure the spi with DMA
-  // code example from dillertech.de
-  
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
-  
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-  
-  // // MISO, not used
-//   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
-//   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-//   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-//   GPIO_Init(GPIOB, &GPIO_InitStructure);
-  // use different CS
-//   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
-//   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-//   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-//   GPIO_Init(GPIOB, &GPIO_InitStructure);
-//   
-//   GPIO_WriteBit(GPIOB, GPIO_Pin_12, SET);
-  
-//   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
-  SPI_InitStructure.SPI_CRCPolynomial = 0;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_Init(SPI2, &SPI_InitStructure);
-  
-  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
-  // // MISO not used
-//   SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);
-  
-  SPI_Cmd(SPI2, ENABLE);
-  
-  
-  // // MISO not used
-//   // DMA Channel 4 - SPI RX
-//   DMA_InitStructure.DMA_BufferSize = 0;
-//   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-//   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-//   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPIBuffer;
-//   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
-//   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-//   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-//   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI2->DR;
-//   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
-//   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-//   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-//   DMA_Init(DMA1_Channel4, &DMA_InitStructure);
-//   
-//   DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE);
-  
-  // DMA Channel 5 - SPI TX
-  DMA_InitStructure.DMA_BufferSize = 0;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-//   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPIBuffer; 
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPIBuffer; 
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI2->DR;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_Init(DMA1_Channel5, &DMA_InitStructure);
-  
-  NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel4_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-  
-  
-  
-
-  
-  
-}
-
 
 
 

diff --git a/firmware/src/periph_conf.c b/firmware/src/periph_conf.c
index 21b81a169bc711660a9c95eef28c900156b4c61a..5f2495d1a1cb2288bebe8b2046947c502eb293b4 100644 (file)
--- a/firmware/src/periph_conf.c
+++ b/firmware/src/periph_conf.c
@@ -7,10 +7,8 @@
  */\r
   \r
 /* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_conf.h"\r
 #include "periph_conf.h"\r
-#include "stm32f10x_spi.h"\r
-#include "stm32f10x_i2c.h"\r
-#include "stm32f10x_dma.h"\r
 \r
 // by micha,\r
 \r

diff --git a/firmware/src/periph_conf.h b/firmware/src/periph_conf.h
index a0c03bcad081bc521e487d1fb0547155398cd180..76ec968c98101a327f441d083a465269257924e5 100644 (file)
--- a/firmware/src/periph_conf.h
+++ b/firmware/src/periph_conf.h
@@ -7,8 +7,8 @@
  */\r
   \r
 \r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_conf.h"\r
+#include "stm32f10x.h"\r
+\r
 \r
 \r
 \r

diff --git a/firmware/src/spi2.c b/firmware/src/spi2.c
new file mode 100644 (file)
index 0000000..ce28d55
--- /dev/null
+++ b/firmware/src/spi2.c
@@ -0,0 +1,121 @@
+/**\r
+ ********************************************************\r
+ * \r
+ *  SPI2\r
+ * \r
+ ********************************************************\r
+ */\r
+\r
+#include "spi2.h"\r
+#include "periph_conf.h"\r
+#include "stm32f10x_conf.h"\r
+\r
+uint16_t SPIBuffer[] = {0xAAAA, 0xAAAA, 0xAAAA};\r
+\r
+GPIO_InitTypeDef GPIO_InitStructure;\r
+NVIC_InitTypeDef NVIC_InitStructure;\r
+SPI_InitTypeDef SPI_InitStructure;\r
+DMA_InitTypeDef DMA_InitStructure;\r
+\r
+void init_SPI2(void) {\r
+  // configure the spi with DMA\r
+  // code example from dillertech.de\r
+  \r
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);\r
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);\r
+  \r
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+  GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+  \r
+  // // MISO, not used\r
+//   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;\r
+//   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+//   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+//   GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+  // use different CS\r
+//   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;\r
+//   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;\r
+//   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+//   GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+//   \r
+//   GPIO_WriteBit(GPIOB, GPIO_Pin_12, SET);\r
+  \r
+//   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32;\r
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;\r
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;\r
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;\r
+  SPI_InitStructure.SPI_CRCPolynomial = 0;\r
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;\r
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;\r
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;\r
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;\r
+  SPI_Init(SPI2, &SPI_InitStructure);\r
+  \r
+  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);\r
+  // // MISO not used\r
+//   SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);\r
+  \r
+  SPI_Cmd(SPI2, ENABLE);\r
+  \r
+  \r
+  // // MISO not used\r
+//   // DMA Channel 4 - SPI RX\r
+//   DMA_InitStructure.DMA_BufferSize = 0;\r
+//   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;\r
+//   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;\r
+//   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPIBuffer;\r
+//   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;\r
+//   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;\r
+//   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;\r
+//   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI2->DR;\r
+//   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;\r
+//   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+//   DMA_InitStructure.DMA_Priority = DMA_Priority_High;\r
+//   DMA_Init(DMA1_Channel4, &DMA_InitStructure);\r
+//   \r
+//   DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE);\r
+  \r
+  // DMA Channel 5 - SPI TX\r
+  DMA_InitStructure.DMA_BufferSize = 0;\r
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;\r
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;\r
+//   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPIBuffer; \r
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPIBuffer; \r
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;\r
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;\r
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;\r
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI2->DR;\r
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;\r
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;\r
+  DMA_Init(DMA1_Channel5, &DMA_InitStructure);\r
+  \r
+  NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel4_IRQn;\r
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;\r
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+  NVIC_Init(&NVIC_InitStructure);\r
+}\r
+\r
+\r
+\r
+void spi_dma_shovel(void) {\r
+\r
+\r
+  \r
+//   DMA_Cmd(DMA1_Channel4, DISABLE);\r
+  DMA_Cmd(DMA1_Channel5, DISABLE);\r
+//   DMA_SetCurrDataCounter(DMA1_Channel4, 2);\r
+  DMA_SetCurrDataCounter(DMA1_Channel5, 2);\r
+  \r
+  // Chip Select Low\r
+//   GPIO_WriteBit(GPIOB, GPIO_Pin_12, RESET);\r
+  CB_GPIO_Out_Lo(UC_CS);     // spi nCS -> idle Hi\r
+  \r
+//   DMA_Cmd(DMA1_Channel4, ENABLE);\r
+  DMA_Cmd(DMA1_Channel5, ENABLE);\r
+}\r

diff --git a/firmware/src/spi2.h b/firmware/src/spi2.h
new file mode 100644 (file)
index 0000000..4d6b827
--- /dev/null
+++ b/firmware/src/spi2.h
@@ -0,0 +1,17 @@
+/**\r
+ ********************************************************\r
+ * \r
+ *  SPI2 (headers)\r
+ * \r
+ ********************************************************\r
+ */\r
+  \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+\r
+\r
+void init_SPI2(void);\r
+\r
+void spi_dma_shovel(void);
\ No newline at end of file

diff --git a/firmware/src/stm32f10x_conf.h b/firmware/src/stm32f10x_conf.h
index 49ccdb23838d0c8d5010e67bf6833980fc857e4e..794ff05d2c2382495a30a9349216aedf9a3aac6a 100644 (file)
--- a/firmware/src/stm32f10x_conf.h
+++ b/firmware/src/stm32f10x_conf.h
@@ -12,7 +12,7 @@
  #include "stm32f10x_flash.h"
 /* #include "stm32f10x_fsmc.h" */
  #include "stm32f10x_gpio.h"
- #include "stm32f10x_i2c.h"
+//  #include "stm32f10x_i2c.h"
 /* #include "stm32f10x_iwdg.h" */
 /* #include "stm32f10x_pwr.h" */
  #include "stm32f10x_rcc.h"

diff --git a/firmware/src/usart1.c b/firmware/src/usart1.c
index ba47a61089d262d1a1245caffe4a0a1178fdb300..e26dccaf9ae0411d2400fb69e16e38e9ce066ee0 100644 (file)
--- a/firmware/src/usart1.c
+++ b/firmware/src/usart1.c
@@ -7,6 +7,7 @@
  */\r
 \r
 #include "usart1.h"\r
+#include "stm32f10x_conf.h"\r
   \r
 void init_USART1(void) {\r
   /* structure contains data for USART configuration */\r

diff --git a/firmware/src/usart1.h b/firmware/src/usart1.h
index f07b70be3f48335c48db4f20467803503d27a825..6166cbac006b610f177bedae931784e3fbc54962 100644 (file)
--- a/firmware/src/usart1.h
+++ b/firmware/src/usart1.h
@@ -8,7 +8,8 @@
   \r
 \r
 /* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_conf.h"\r
+\r
+#include "stm32f10x.h"\r
 \r
 \r
 void init_USART1(void);\r