adding address defaults for DiRich modules

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 158399f5c11c74777e13cd32be019765f88b40a1..544939361c72aeb83491a5e237bff9571eba4c85 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -49,7 +49,7 @@ Second, the upper 16 Bit of the Hardware Version register as described below is
 \begin{warning}
   Always ensure that your trbflash accesses the TrbNet over RPC (i.e.
   trbnetd) and \emph{not} locally. So check if \verb!trbflash -V!
-  mentions RPC. If it's not the case, fix your \verb!$PATH!. It you
+  mentions RPC. If it's not the case, fix your \verb!$PATH!. If you
   don't access the TrbNet via trbnetd, a running CTS monitor in the
   background might disrupt your flash and hence corrupt your flash
   image!
@@ -68,6 +68,7 @@ The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (reg
  \item[9300] design for CBM Tof
  \item[9500] design for Trb3sc
  \item[9600] design for DiRich
+ \item[9700] design for DiRich Combiner module
 \end{description*}
 
 The lower 16 Bit are used to identify the contents of the design and the AddOn boards they should be used with. Combine 
@@ -158,10 +159,12 @@ The initial address set with \signal{Regio\_Init\_Address} can be chosen from th
  \item 0xF300 for the central FPGA
  \item 0xF305 for the peripheral FPGA
  \item 0xF30n for a design for FPGA n only
- \item 0xF3C0 default for a design with CTS
- \item 0xF3CC default for slave TRB3sc
- \item 0xF3CD default for TRB3sc with hub AddOn
- \item 0xF3CE default for crate master TRB3sc
+ \item 0xF3C0 a design with CTS
+ \item 0xF3CC slave TRB3sc
+ \item 0xF3CD TRB3sc with hub AddOn
+ \item 0xF3CE crate master TRB3sc
+ \item 0xF3D1 Dirch
+ \item 0xF3DC Dirich combiner
 \end{itemize*}
 
 
@@ -172,6 +175,7 @@ The initial address set with \signal{Regio\_Init\_Address} can be chosen from th
  \item Power-up - current should be around 0.25A at 48V
  \item Check if fixes (Flash 0R) are done
  \item Load set of configuration files (no Flash programming for FPGAs, only load design)
+ \item Also note that you need to issue an \verb!trbcmd reset! after JTAG programming in order to have the FPGAs obtain the correct local number identification reported by an info trbcmd broadcast (5 for central, 0-3 for peripheral FPGAs).
  \item Check basic TrbNet functionality
  \item Program Flash ROMs via TrbNet
  \item Reboot Board to see if all FPGA boot from Flash
@@ -221,11 +225,14 @@ You can unload it automatically using a udev-rule by adding (as one line)
 \\\verb!rmmod ftdi_sio!
 \\after plugging in the cable.
 
-Also note that you need to issue an \verb!trbcmd reset! after JTAG programming in order to have the FPGAs obtain the correct local number identification reported by an info trbcmd broadcast (5 for central, 0-3 for peripheral FPGAs).
-
 \subsection{Data Unpacker}
 \label{Data_Unpacking}
-The data stream contains SubEvent-IDs and SubSubEvent-IDs to identify the sender of each block of data. While SubSubEvent-IDs are equal to the network address of the corresponding board by design, the SubEvent-IDs can be chosen freely, but are defined to be equal to the network address of the board sending the SubEvent via Gigabit Ethernet. The first digit of each SubSubEvent-ID is sufficient to determine how the following data  has to be handled:
+The data stream contains SubEvent-IDs and SubSubEvent-IDs to identify the sender 
+of each block of data. While SubSubEvent-IDs are equal to the network address of 
+the corresponding board by design, the SubEvent-IDs can be chosen freely, but are 
+defined to be equal to the network address of the board sending the SubEvent via 
+Gigabit Ethernet. The first digit of each SubSubEvent-ID is sufficient to determine 
+how the following data has to be handled:
 \begin{description*}
 \item[0..1] Unpack as TDC data
 \item[5555] The only SubSubEvent-ID starting with 5 is 5555 at the end of each SubEvent, marking the beginning of the status information word for this SubEvent.