+*~
*.log
*.rpt
netlists
*.sym
*tmpl.vhd
*.log
-
+workdir
+*.kate-swp
ln -s ../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt
ln -s ../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.txt
ln -s ../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt
+ln -s ../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.txt
ln -s ../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.txt
ln -s ../../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.txt
ln -s ../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.txt
ln -s ../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_125_0.txt
-
+ln -s ../../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.txt
ESB_DATA_OUT : out std_logic_vector(31 downto 0);
ESB_DATAREADY_OUT : out std_logic;
ESB_UNKNOWN_ADDR_OUT : out std_logic;
- EFB_READ_EN_IN : in std_logic;
- EFB_WRITE_EN_IN : in std_logic;
- EFB_ADDR_IN : in std_logic_vector(6 downto 0);
- EFB_DATA_OUT : out std_logic_vector(31 downto 0);
- EFB_DATAREADY_OUT : out std_logic;
- EFB_UNKNOWN_ADDR_OUT : out std_logic;
+ FWB_READ_EN_IN : in std_logic;
+ FWB_WRITE_EN_IN : in std_logic;
+ FWB_ADDR_IN : in std_logic_vector(6 downto 0);
+ FWB_DATA_OUT : out std_logic_vector(31 downto 0);
+ FWB_DATAREADY_OUT : out std_logic;
+ FWB_UNKNOWN_ADDR_OUT : out std_logic;
LHB_READ_EN_IN : in std_logic;
LHB_WRITE_EN_IN : in std_logic;
LHB_ADDR_IN : in std_logic_vector(6 downto 0);
CLK_200 : in std_logic;
CLK_100 : in std_logic;
HIT_IN : in std_logic;
+ TRIGGER_IN : in std_logic;
+ SCALER_IN : in std_logic;
TRIGGER_WIN_END_IN : in std_logic;
READ_EN_IN : in std_logic;
FIFO_DATA_OUT : out std_logic_vector(35 downto 0);
FIFO_ALMOST_FULL_OUT : out std_logic;
COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
--- DATA_FINISHED_IN : in std_logic;
+ DATA_FINISHED_IN : in std_logic;
LOST_HIT_NUMBER : out std_logic_vector(23 downto 0);
HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0);
+ FIFO_WR_NUMBER : out std_logic_vector(23 downto 0);
ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0);
Channel_DEBUG : out std_logic_vector(31 downto 0));
CLK_100 : in std_logic;
RESET_100 : in std_logic;
HIT_IN : in std_logic;
+ TRIGGER_IN : in std_logic;
+ SCALER_IN : in std_logic;
TRIGGER_WIN_END_IN : in std_logic;
EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
--- DATA_FINISHED_IN : in std_logic;
+ DATA_FINISHED_IN : in std_logic;
COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
READ_EN_IN : in std_logic;
FIFO_DATA_OUT : out std_logic_vector(35 downto 0);
FIFO_EMPTY_OUT : out std_logic;
FIFO_FULL_OUT : out std_logic;
FIFO_ALMOST_FULL_OUT : out std_logic;
+ FIFO_WR_OUT : out std_logic;
ENCODER_START_OUT : out std_logic;
ENCODER_FINISHED_OUT : out std_logic);
end component;
DATA_WRITE_OUT : out std_logic;
DATA_FINISHED_OUT : out std_logic;
READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0);
+ HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1);
+ READOUT_BUSY_OUT : out std_logic;
TRIGGER_WIN_END_OUT : out std_logic;
STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 18);
READOUT_DEBUG : out std_logic_vector(31 downto 0));
-w
-i 15
-l 5
--n 1
+-n 3
-y
-s 12
-t 1
-c 1
-e 2
--m nodelist.txt
+-m ../base/nodelist_frankfurt.txt
# -w
# -i 6
# -l 5
--
-- 0x0d Event Builder selection
-- 15 : 00 Event Builder mask (default: 0x1)
--- 23 : 16 Number of events before selecting next builder (useful to aggregate events to support large data packets)
+-- 23 : 16 Number of events before selecting next builder (useful to aggregate events to support large data packets
+-- 27 : 24 Event Builder number of calibration trigger
+-- 28 If asserted: Use special event builder for calibration trigger, otherwise, use ordinary round robin selection.
-- </address_table>
-- Header of data packet written to event builder
eb_mask_buf_i : std_logic_vector(15 downto 0) := (0 => '1', others => '0');
signal eb_aggr_threshold_i, eb_aggr_counter_i : unsigned(7 downto 0) := x"00";
signal eb_selection_i : std_logic_vector(3 downto 0) := x"0";
+ signal eb_special_calibration_eb_i : std_logic_vector(3 downto 0) := x"0";
+ signal eb_use_special_calibration_eb_i : std_logic := '0';
begin
-- Trigger Distribution
-----------------------------------------
CTS_IPU_NUMBER_OUT <= fifo_data_out_i(15 downto 0);
CTS_IPU_RND_CODE_OUT <= fifo_data_out_i(23 downto 16);
CTS_IPU_TYPE_OUT <= fifo_data_out_i(27 downto 24);
- CTS_IPU_INFORMATION_OUT <= X"0" & eb_selection_i;
+ CTS_IPU_INFORMATION_OUT <= X"00";
+
+ if fifo_data_out_i(27 downto 24) = x"e" and eb_use_special_calibration_eb_i = '1' then
+ CTS_IPU_INFORMATION_OUT(3 downto 0) <= eb_special_calibration_eb_i;
+ else
+ CTS_IPU_INFORMATION_OUT(3 downto 0) <= eb_selection_i;
+ end if;
CTS_IPU_SEND_OUT <= '1';
random_proc: process(CLK) is
begin
if rising_edge(CLK) then
- -- sequence repeats every 256 iterations
- td_random_number_i <= STD_LOGIC_VECTOR(UNSIGNED(td_random_number_i) + TO_UNSIGNED(113, 8));
+ -- sequence (without external entropy) repeats every 256 iterations
+ td_random_number_i <= STD_LOGIC_VECTOR(UNSIGNED(td_random_number_i) + TO_UNSIGNED(113, 8) + UNSIGNED(CTS_REGIO_ADDR_IN(7 downto 0)))
+ xor ("0" & LVL1_TRG_DATA_VALID_IN & "0" &LVL1_VALID_TIMING_TRG_IN & "0000");
end if;
end process;
cts_status_registers_i(16#0c#)(throttle_threshold_i'RANGE) <= STD_LOGIC_VECTOR(throttle_threshold_i);
cts_status_registers_i(16#0c#)(throttle_threshold_i'LENGTH) <= throttle_enabled_i;
cts_status_registers_i(16#0c#)(31) <= stop_triggers_i;
+
cts_status_registers_i(16#0d#)(15 downto 0) <= eb_mask_i;
cts_status_registers_i(16#0d#)(23 downto 16) <= STD_LOGIC_VECTOR(eb_aggr_threshold_i);
+ cts_status_registers_i(16#0d#)(27 downto 24) <= eb_special_calibration_eb_i;
+ cts_status_registers_i(16#0d#)(28) <= eb_use_special_calibration_eb_i;
regio_proc: process(CLK) is
variable addr : integer range 0 to 15;
throttle_threshold_i <= (others => '0');
throttle_enabled_i <= '0';
stop_triggers_i <= '0';
+
eb_aggr_threshold_i <= x"00";
eb_mask_i <= (0 => '1', others => '0');
-
+ eb_special_calibration_eb_i <= x"0";
+ eb_use_special_calibration_eb_i <= '0';
else
if addr = 16#0d# and cts_regio_write_enable_in_i = '1' then
eb_mask_i <= cts_regio_data_in_i(15 downto 0);
eb_aggr_threshold_i <= UNSIGNED(cts_regio_data_in_i(23 downto 16));
+ eb_special_calibration_eb_i <= cts_regio_data_in_i(27 downto 24);
+ eb_use_special_calibration_eb_i <= cts_regio_data_in_i(28);
end if;
end if;
end if;
-w
-i 15
-l 5
--n 5
+-n 1
-y
-s 12
-t 20
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic.vhd"
+
add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
use work.trb3_components.all;
use work.med_sync_define.all;
use work.version.all;
entity trb3_periph_sodasource is
generic(
SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_YES
+ USE_125_MHZ : integer := c_NO;
+ CLOCK_FREQUENCY : integer := 100;
+ NUM_INTERFACES : integer := 2
);
port(
--Clocks
signal clk_tdc : std_logic;
signal time_counter, time_counter2 : unsigned(31 downto 0);
--Media Interface
- signal med_stat_op : std_logic_vector (1*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
- signal med_data_out : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_out : std_logic;
- signal med_read_out : std_logic;
- signal med_data_in : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_in : std_logic;
- signal med_read_in : std_logic;
+ signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
--Slow Control channel
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
CLEAR => clear_i,
CLK_EN => '1',
--Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
+ MED_DATA_IN => med_data_out(15 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(15 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
REFCLK2CORE_OUT => open,
CLK_RX_HALF_OUT => rx_clock_half,
CLK_RX_FULL_OUT => rx_clock_full,
SCI_WRITE => sci1_write,
SCI_ACK => sci1_ack,
-- Status and control port
- STAT_OP => med_stat_op,
- CTRL_OP => med_ctrl_op,
- STAT_DEBUG => med_stat_debug,
+ STAT_OP => med_stat_op(15 downto 0),
+ CTRL_OP => med_ctrl_op(15 downto 0),
+ STAT_DEBUG => med_stat_debug(63 downto 0),
CTRL_DEBUG => (others => '0')
);
---------------------------------------------------------------------------
-- Endpoint
---------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"45",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"91000000",
- REGIO_INIT_ADDRESS => x"f306",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => 100,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 9, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 256,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 256
- )
- port map(
- CLK => clk_sys_i,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out,
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out,
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => '0',
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => open,
- LVL1_VALID_TIMING_TRG_OUT => open,
- LVL1_VALID_NOTIMING_TRG_OUT => open,
- LVL1_INVALID_TRG_OUT => open,
-
- LVL1_TRG_TYPE_OUT => open,
- LVL1_TRG_NUMBER_OUT => open,
- LVL1_TRG_CODE_OUT => open,
- LVL1_TRG_INFORMATION_OUT => open,
- LVL1_INT_TRG_NUMBER_OUT => open,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => open,
- TRG_TIMEOUT_DETECTED_OUT => open,
- TRG_SPURIOUS_TRG_OUT => open,
- TRG_MISSING_TMG_TRG_OUT => open,
- TRG_SPIKE_DETECTED_OUT => open,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => '1',
- FEE_TRG_STATUSBITS_IN => (others => '0'),
- FEE_DATA_IN => (others => '0'),
- FEE_DATA_WRITE_IN(0) => '0',
- FEE_DATA_FINISHED_IN(0) => '1',
- FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
+-- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+-- generic map(
+-- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+-- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+-- ADDRESS_MASK => x"FFFF",
+-- BROADCAST_BITMASK => x"FF",
+-- BROADCAST_SPECIAL_ADDR => x"45",
+-- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+-- REGIO_HARDWARE_VERSION => x"91000000",
+-- REGIO_INIT_ADDRESS => x"f306",
+-- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+-- CLOCK_FREQUENCY => 100,
+-- TIMING_TRIGGER_RAW => c_YES,
+-- --Configure data handler
+-- DATA_INTERFACE_NUMBER => 1,
+-- DATA_BUFFER_DEPTH => 9, --13
+-- DATA_BUFFER_WIDTH => 32,
+-- DATA_BUFFER_FULL_THRESH => 256,
+-- TRG_RELEASE_AFTER_DATA => c_YES,
+-- HEADER_BUFFER_DEPTH => 9,
+-- HEADER_BUFFER_FULL_THRESH => 256
+-- )
+-- port map(
+-- CLK => clk_sys_i,
+-- RESET => reset_i,
+-- CLK_EN => '1',
+-- MED_DATAREADY_OUT => med_dataready_out,
+-- MED_DATA_OUT => med_data_out,
+-- MED_PACKET_NUM_OUT => med_packet_num_out,
+-- MED_READ_IN => med_read_in,
+-- MED_DATAREADY_IN => med_dataready_in,
+-- MED_DATA_IN => med_data_in,
+-- MED_PACKET_NUM_IN => med_packet_num_in,
+-- MED_READ_OUT => med_read_out,
+-- MED_STAT_OP_IN => med_stat_op,
+-- MED_CTRL_OP_OUT => med_ctrl_op,
+--
+-- --Timing trigger in
+-- TRG_TIMING_TRG_RECEIVED_IN => '0',
+-- --LVL1 trigger to FEE
+-- LVL1_TRG_DATA_VALID_OUT => open,
+-- LVL1_VALID_TIMING_TRG_OUT => open,
+-- LVL1_VALID_NOTIMING_TRG_OUT => open,
+-- LVL1_INVALID_TRG_OUT => open,
+--
+-- LVL1_TRG_TYPE_OUT => open,
+-- LVL1_TRG_NUMBER_OUT => open,
+-- LVL1_TRG_CODE_OUT => open,
+-- LVL1_TRG_INFORMATION_OUT => open,
+-- LVL1_INT_TRG_NUMBER_OUT => open,
+--
+-- --Information about trigger handler errors
+-- TRG_MULTIPLE_TRG_OUT => open,
+-- TRG_TIMEOUT_DETECTED_OUT => open,
+-- TRG_SPURIOUS_TRG_OUT => open,
+-- TRG_MISSING_TMG_TRG_OUT => open,
+-- TRG_SPIKE_DETECTED_OUT => open,
+--
+-- --Response from FEE
+-- FEE_TRG_RELEASE_IN(0) => '1',
+-- FEE_TRG_STATUSBITS_IN => (others => '0'),
+-- FEE_DATA_IN => (others => '0'),
+-- FEE_DATA_WRITE_IN(0) => '0',
+-- FEE_DATA_FINISHED_IN(0) => '1',
+-- FEE_DATA_ALMOST_FULL_OUT(0) => open,
+--
+-- -- Slow Control Data Port
+-- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+-- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+-- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+-- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+-- REGIO_STAT_REG_IN => stat_reg, --start 0x80
+-- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+-- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+-- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+-- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+-- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+--
+-- BUS_ADDR_OUT => regio_addr_out,
+-- BUS_READ_ENABLE_OUT => regio_read_enable_out,
+-- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+-- BUS_DATA_OUT => regio_data_out,
+-- BUS_DATA_IN => regio_data_in,
+-- BUS_DATAREADY_IN => regio_dataready_in,
+-- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+-- BUS_WRITE_ACK_IN => regio_write_ack_in,
+-- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+-- BUS_TIMEOUT_OUT => regio_timeout_out,
+-- ONEWIRE_INOUT => TEMPSENS,
+-- ONEWIRE_MONITOR_OUT => open,
+--
+-- TIME_GLOBAL_OUT => global_time,
+-- TIME_LOCAL_OUT => local_time,
+-- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+-- TIME_TICKS_OUT => timer_ticks,
+--
+-- STAT_DEBUG_IPU => open,
+-- STAT_DEBUG_1 => open,
+-- STAT_DEBUG_2 => open,
+-- STAT_DEBUG_DATA_HANDLER_OUT => open,
+-- STAT_DEBUG_IPU_HANDLER_OUT => open,
+-- STAT_TRIGGER_OUT => open,
+-- CTRL_MPLEX => (others => '0'),
+-- IOBUF_CTRL_GEN => (others => '0'),
+-- STAT_ONEWIRE => open,
+-- STAT_ADDR_DEBUG => open,
+-- DEBUG_LVL1_HANDLER_OUT => open
+-- );
+
+
+---------------------------------------------------------------------------
+-- Hub
+---------------------------------------------------------------------------
+
+THE_HUB : trb_net16_hub_base
+ generic map (
+ HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),
+ IBUF_SECURE_MODE => c_YES,
+ MII_NUMBER => NUM_INTERFACES,
+ MII_IS_UPLINK => (0 => 1, others => 0),
+ MII_IS_DOWNLINK => (0 => 0, others => 1),
+ MII_IS_UPLINK_ONLY=> (0 => 1, others => 0),
+ INT_NUMBER => 0,
+ USE_ONEWIRE => c_YES,
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+ HARDWARE_VERSION => x"91003200",
+ INIT_ENDPOINT_ID => x"0000",
+ INIT_ADDRESS => x"F355",
+ USE_VAR_ENDPOINT_ID => c_YES,
+ BROADCAST_SPECIAL_ADDR => x"45",
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY
+ )
+ port map (
+ CLK => clk_sys_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ --Media interfacces
+ MED_DATAREADY_OUT(NUM_INTERFACES*1-1 downto 0) => med_dataready_out,
+ MED_DATA_OUT(NUM_INTERFACES*16-1 downto 0) => med_data_out,
+ MED_PACKET_NUM_OUT(NUM_INTERFACES*3-1 downto 0) => med_packet_num_out,
+ MED_READ_IN(NUM_INTERFACES*1-1 downto 0) => med_read_in,
+ MED_DATAREADY_IN(NUM_INTERFACES*1-1 downto 0) => med_dataready_in,
+ MED_DATA_IN(NUM_INTERFACES*16-1 downto 0) => med_data_in,
+ MED_PACKET_NUM_IN(NUM_INTERFACES*3-1 downto 0) => med_packet_num_in,
+ MED_READ_OUT(NUM_INTERFACES*1-1 downto 0) => med_read_out,
+ MED_STAT_OP(NUM_INTERFACES*16-1 downto 0) => med_stat_op,
+ MED_CTRL_OP(NUM_INTERFACES*16-1 downto 0) => med_ctrl_op,
+
+ COMMON_STAT_REGS => common_stat_reg,
+ COMMON_CTRL_REGS => common_ctrl_reg,
+ MY_ADDRESS_OUT => open,
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT => regio_addr_out,
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
+ REGIO_DATA_OUT => regio_data_out,
+ REGIO_DATA_IN => regio_data_in,
+ REGIO_DATAREADY_IN => regio_dataready_in,
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ REGIO_TIMEOUT_OUT => regio_timeout_out,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+ ONEWIRE => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+ --Status ports (for debugging)
+ MPLEX_CTRL => (others => '0'),
+ CTRL_DEBUG => (others => '0'),
+ STAT_DEBUG => open
+ );
+
---------------------------------------------------------------------------
RESET => reset_i,
CLEAR => clear_i,
--Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => (others => '0'),
- MED_PACKET_NUM_IN => (others => '0'),
- MED_DATAREADY_IN => '0',
- MED_READ_OUT => open,
- MED_DATA_OUT => open,
- MED_PACKET_NUM_OUT => open,
- MED_DATAREADY_OUT => open,
- MED_READ_IN => '1',
+ MED_DATA_IN => med_data_out(31 downto 16),
+ MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),
+ MED_DATAREADY_IN => med_dataready_out(1),
+ MED_READ_OUT => med_read_in(1),
+ MED_DATA_OUT => med_data_in(31 downto 16),
+ MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
+ MED_DATAREADY_OUT => med_dataready_in(1),
+ MED_READ_IN => med_read_out(1),
CLK_RX_HALF_OUT => soda_rx_clock_half,
CLK_RX_FULL_OUT => soda_rx_clock_full,
SCI_ACK => sci2_ack,
SCI_NACK => sci2_nack,
-- Status and control port
- STAT_OP => open,
- CTRL_OP => (others => '0'),
+ STAT_OP => med_stat_op(31 downto 16),
+ CTRL_OP => med_ctrl_op(31 downto 16),
STAT_DEBUG => open,
CTRL_DEBUG => (others => '0')
);
---------------------------------------------------------------------------
-- The Soda Source
---------------------------------------------------------------------------
-
+ tx_dlm_i <= '0';
+ tx_dlm_word <= x"00";
---------------------------------------------------------------------------
+++ /dev/null
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := 1364404198;
-
-end package version;
constant USE_ETHERNET : integer := c_YES;
--Run wih 125 MHz instead of 100 MHz
- constant USE_125_MHZ : integer := c_YES;
+ constant USE_125_MHZ : integer := c_NO;
--Only slow-control, no trigger or read-out
- constant USE_SCTRL_ONLY : integer := c_YES;
+ constant USE_SCTRL_ONLY : integer := c_NO;
--Use sync mode, RX clock for all parts of the FPGA
constant USE_RXCLOCK : integer := c_NO;
--this is used to select the proper configuration in the main code
constant CFG_MODE : integer;
-
- --first entry is normal CTS with one optical output, second one is with four optical outputs
- --slow-control is accepted on SFP1 only, triggers are sent to all used SFP
+ -- --optical link SFP1 is uplink on all channels (e.g. connect a Hub)
+
+
constant INTERNAL_NUM_ARR : hub_mii_t := (0,0);
constant INTERFACE_NUM_ARR : hub_mii_t := (5,5);
constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0));
constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1),
- (1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0));
+ (1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0));
constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0));
constant INTERNAL_CHANNEL_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
--- /dev/null
+.*ini
+*log*
+*.sty
+*.xml
+trb3_gbe
+*.pty
+*.ccl
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="2.0" title="trb3_gbe" device="LFE3-150EA-8FN1156C" default_implementation="trb3_gbe">
+ <Options/>
+ <Implementation title="trb3_gbe" dir="trb3_gbe" description="trb3_gbe" default_strategy="Strategy1">
+ <Options top="trb3_central"/>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v" type="Verilog" type_short="Verilog">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v" type="Verilog" type_short="Verilog">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v" type="Verilog" type_short="Verilog">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v" type="Verilog" type_short="Verilog">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v" type="Verilog" type_short="Verilog">
+ <Options/>
+ </Source>
+ <Source name="../version.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../config.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/priority_arbiter.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_receive_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_main_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_mac_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_type_validator.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu2gbe_simple_sender.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ip_configurator.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/mb_mac_sim.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/slv_mac_memory.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_api_ipu_streaming.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_hub_streaming_port.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_hub_streaming_port_sctrl.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/wide_adder_17x16.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_sbuf4.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_sbuf3.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_sbuf2.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_hub_logic_2.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_hub_ipu_logic.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/special/slv_register.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/fifo_dualclock_width_16_reg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trb3_central.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../workdir/trb3_central.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="Strategy1.sty"/>
+</BaliProject>
-n 2
-y
-s 12
--t 12
+-t 14
-c 1
-e 2
#-g guidefile.ncd
#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu2gbe_simple_sender.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu2gbe_simple_sender.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_mac_memory.vhd"
#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_register.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd"
add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
port map(
CLK => clk_sys_i,
TEST_CLK => '0',
- CLK_125_IN => CLK_GPLL_RIGHT,
+ CLK_125_IN => clk_gbe_internal,
RESET => reset_i,
GSR_N => gsr_n,
--Debug
\r
\r
MULTICYCLE FROM CELL "gen_ethernet_hub_THE_HUB/reset_i" 20 ns;\r
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/reset" 20 ns;\r
\r
#TrbNet Hub \r
REGION "REGION_IOBUF" "R20C96D" 88 86 DEVSIZE;\r
BLKNAME gen_ethernet_hub_GBE/FRAME_CONSTRUCTOR\r
BLKNAME gen_ethernet_hub_GBE/MB_IP_CONFIG\r
BLKNAME gen_ethernet_hub_GBE/THE_IP_CONFIGURATOR\r
- BLKNAME gen_ethernet_hub_GBE/PACKET_CONSTRUCTOR\r
+# BLKNAME gen_ethernet_hub_GBE/PACKET_CONSTRUCTOR\r
#BLKNAME gen_ethernet_hub_GBE/THE_IPU_INTERFACE\r
BLKNAME gen_ethernet_hub_GBE/setup_imp_gen_SETUP;\r
\r
\r
\r
#Normal design\r
-# REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;\r
-# REGION "GBE_MAIN_REGION" "R74C30C" 38 36 DEVSIZE;\r
-# LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
-# LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
+REGION "GBE_REGION" "R30C20D" 35 40 DEVSIZE;\r
+REGION "GBE_MAIN_REGION" "R74C40C" 38 36 DEVSIZE;\r
+LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
+LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
\r
#Reduced design\r
# REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;\r
\r
\r
\r
-REGION "MED0" "R70C2D" 35 40 DEVSIZE;\r
+REGION "MED0" "R69C4D" 35 40 DEVSIZE;\r
FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;\r
FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125_c" 125.000000 MHz ;\r
LOCATE UGROUP "tsmac" REGION "MED0" ;\r
BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ;\r
BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ;\r
\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2.000000 X ;\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2.000000 X ;\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2.000000 X ;\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;\r
-MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;\r
-MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;\r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2.000000 X ;\r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2.000000 X ;\r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2.000000 X ;\r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;\r
+# MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;\r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;\r
+# MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;\r
\r
#BLOCK INTERCLOCKDOMAIN PATHS ;
\ No newline at end of file
\r
entity panda_dirc_wasa is\r
generic(\r
- NORMAL_ORDER : integer := 1\r
+ NORMAL_ORDER : integer := 0\r
);\r
port(\r
CON : out std_logic_vector(16 downto 1);\r
end generate;\r
\r
gen_outputs_2 : if NORMAL_ORDER = 0 generate\r
- INP_i <= INP(15) & INP(7) & INP(14) & INP(6) & INP(13) & INP(5) & INP(12) & INP(4) & \r
- INP(11) & INP(3) & INP(10) & INP(2) & INP(9) & INP(1) & INP(8) & INP(0);\r
+ INP_i <= INP(16) & INP(8) & INP(15) & INP(7) & INP(14) & INP(6) & INP(13) & INP(5) & \r
+ INP(12) & INP(4) & INP(11) & INP(3) & INP(10) & INP(2) & INP(9) & INP(1);\r
PWM <= pwm_i(15) & pwm_i(7) & pwm_i(14) & pwm_i(6) & pwm_i(13) & pwm_i(5) & pwm_i(12) & pwm_i(4) & \r
pwm_i(11) & pwm_i(3) & pwm_i(10) & pwm_i(2) & pwm_i(9) & pwm_i(1) & pwm_i(8) & pwm_i(0);\r
end generate;\r
case spi_channel_i(3 downto 0) is\r
when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
+ when x"2" => spi_reg20_i <= x"000" & "000" & std_logic_vector(to_unsigned(NORMAL_ORDER,1));\r
when others => null;\r
end case;\r
end if;\r
jspc29 / trb3.git / commitdiff