{
"design": {
"design_info": {
- "boundary_crc": "0x1DD12A2FE1BACBB7",
+ "boundary_crc": "0x6FE76044F4026DDC",
"device": "xcku115-flvf1924-2-e",
"name": "design_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"mode": "Master",
"vlnv": "xilinx.com:interface:gpio_rtl:1.0"
},
- "RESETS": {
+ "EXT_RESETS_N": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:gpio_rtl:1.0"
+ },
+ "SYSCLK_RESET": {
"mode": "Master",
"vlnv": "xilinx.com:interface:gpio_rtl:1.0"
}
}
},
"interface_nets": {
- "microblaze_0_dlmb_bus": {
+ "microblaze_0_dlmb": {
"interface_ports": [
- "dlmb_v10/LMB_Sl_0",
- "dlmb_bram_if_cntlr/SLMB"
+ "DLMB",
+ "dlmb_v10/LMB_M"
]
},
"microblaze_0_ilmb": {
"lmb_bram/BRAM_PORTA"
]
},
- "microblaze_0_ilmb_cntlr": {
+ "microblaze_0_dlmb_bus": {
"interface_ports": [
- "ilmb_bram_if_cntlr/BRAM_PORT",
- "lmb_bram/BRAM_PORTB"
+ "dlmb_v10/LMB_Sl_0",
+ "dlmb_bram_if_cntlr/SLMB"
]
},
"microblaze_0_ilmb_bus": {
"ilmb_bram_if_cntlr/SLMB"
]
},
- "microblaze_0_dlmb": {
+ "microblaze_0_ilmb_cntlr": {
"interface_ports": [
- "DLMB",
- "dlmb_v10/LMB_M"
+ "ilmb_bram_if_cntlr/BRAM_PORT",
+ "lmb_bram/BRAM_PORTB"
]
}
},
"m05_couplers/S_AXI"
]
},
- "m06_couplers_to_microblaze_0_axi_periph": {
- "interface_ports": [
- "M06_AXI",
- "m06_couplers/M_AXI"
- ]
- },
- "s00_couplers_to_xbar": {
- "interface_ports": [
- "s00_couplers/M_AXI",
- "xbar/S00_AXI"
- ]
- },
- "m00_couplers_to_microblaze_0_axi_periph": {
+ "m01_couplers_to_microblaze_0_axi_periph": {
"interface_ports": [
- "M00_AXI",
- "m00_couplers/M_AXI"
+ "M01_AXI",
+ "m01_couplers/M_AXI"
]
},
"xbar_to_m06_couplers": {
"m06_couplers/S_AXI"
]
},
- "xbar_to_m00_couplers": {
+ "xbar_to_m04_couplers": {
"interface_ports": [
- "xbar/M00_AXI",
- "m00_couplers/S_AXI"
+ "xbar/M04_AXI",
+ "m04_couplers/S_AXI"
]
},
- "m01_couplers_to_microblaze_0_axi_periph": {
+ "xbar_to_m03_couplers": {
"interface_ports": [
- "M01_AXI",
- "m01_couplers/M_AXI"
+ "xbar/M03_AXI",
+ "m03_couplers/S_AXI"
]
},
- "xbar_to_m01_couplers": {
+ "m03_couplers_to_microblaze_0_axi_periph": {
"interface_ports": [
- "xbar/M01_AXI",
- "m01_couplers/S_AXI"
+ "M03_AXI",
+ "m03_couplers/M_AXI"
]
},
"m02_couplers_to_microblaze_0_axi_periph": {
"m02_couplers/M_AXI"
]
},
+ "microblaze_0_axi_periph_to_s00_couplers": {
+ "interface_ports": [
+ "S00_AXI",
+ "s00_couplers/S_AXI"
+ ]
+ },
"xbar_to_m02_couplers": {
"interface_ports": [
"xbar/M02_AXI",
"m02_couplers/S_AXI"
]
},
- "m03_couplers_to_microblaze_0_axi_periph": {
+ "m04_couplers_to_microblaze_0_axi_periph": {
"interface_ports": [
- "M03_AXI",
- "m03_couplers/M_AXI"
+ "M04_AXI",
+ "m04_couplers/M_AXI"
+ ]
+ },
+ "m06_couplers_to_microblaze_0_axi_periph": {
+ "interface_ports": [
+ "M06_AXI",
+ "m06_couplers/M_AXI"
]
},
"m05_couplers_to_microblaze_0_axi_periph": {
"m05_couplers/M_AXI"
]
},
- "xbar_to_m03_couplers": {
+ "m00_couplers_to_microblaze_0_axi_periph": {
"interface_ports": [
- "xbar/M03_AXI",
- "m03_couplers/S_AXI"
+ "M00_AXI",
+ "m00_couplers/M_AXI"
]
},
- "xbar_to_m04_couplers": {
+ "xbar_to_m01_couplers": {
"interface_ports": [
- "xbar/M04_AXI",
- "m04_couplers/S_AXI"
+ "xbar/M01_AXI",
+ "m01_couplers/S_AXI"
]
},
- "m04_couplers_to_microblaze_0_axi_periph": {
+ "s00_couplers_to_xbar": {
"interface_ports": [
- "M04_AXI",
- "m04_couplers/M_AXI"
+ "s00_couplers/M_AXI",
+ "xbar/S00_AXI"
]
},
- "microblaze_0_axi_periph_to_s00_couplers": {
+ "xbar_to_m00_couplers": {
"interface_ports": [
- "S00_AXI",
- "s00_couplers/S_AXI"
+ "xbar/M00_AXI",
+ "m00_couplers/S_AXI"
]
}
},
"C_ALL_OUTPUTS": {
"value": "1"
},
+ "C_ALL_OUTPUTS_2": {
+ "value": "1"
+ },
+ "C_DOUT_DEFAULT_2": {
+ "value": "0xFFFFFFFF"
+ },
+ "C_GPIO2_WIDTH": {
+ "value": "1"
+ },
"C_GPIO_WIDTH": {
"value": "8"
+ },
+ "C_IS_DUAL": {
+ "value": "1"
}
}
}
},
"interface_nets": {
+ "axi_gpio_resets_GPIO2": {
+ "interface_ports": [
+ "SYSCLK_RESET",
+ "axi_gpio_resets/GPIO2"
+ ]
+ },
"microblaze_0_axi_periph_M05_AXI": {
"interface_ports": [
"microblaze_0_axi_periph/M05_AXI",
"axi_gpio_mpod_txdis/S_AXI"
]
},
- "microblaze_0_dlmb_1": {
+ "microblaze_0_axi_periph_M03_AXI": {
"interface_ports": [
- "microblaze_0/DLMB",
- "microblaze_0_local_memory/DLMB"
+ "microblaze_0_axi_periph/M03_AXI",
+ "axi_gpio_mpod_los/S_AXI"
]
},
- "microblaze_0_ilmb_1": {
+ "axi_gpio_mpod_los_GPIO2": {
"interface_ports": [
- "microblaze_0/ILMB",
- "microblaze_0_local_memory/ILMB"
+ "MPOD_LOS_1",
+ "axi_gpio_mpod_los/GPIO2"
]
},
- "axi_gpio_resets_GPIO": {
+ "microblaze_0_debug": {
"interface_ports": [
- "RESETS",
- "axi_gpio_resets/GPIO"
+ "mdm_1/MBDEBUG_0",
+ "microblaze_0/DEBUG"
]
},
- "microblaze_0_axi_periph_M02_AXI": {
+ "microblaze_0_interrupt": {
"interface_ports": [
- "microblaze_0_axi_periph/M02_AXI",
- "axi_iic_0/S_AXI"
+ "microblaze_0_axi_intc/interrupt",
+ "microblaze_0/INTERRUPT"
]
},
"axi_iic_0_IIC": {
"axi_iic_0/IIC"
]
},
- "axi_gpio_mpod_txdis_GPIO": {
+ "microblaze_0_dlmb_1": {
"interface_ports": [
- "MPOD_TXDIS_0",
- "axi_gpio_mpod_txdis/GPIO"
+ "microblaze_0/DLMB",
+ "microblaze_0_local_memory/DLMB"
]
},
- "microblaze_0_debug": {
+ "axi_gpio_mpod_txdis_GPIO2": {
"interface_ports": [
- "mdm_1/MBDEBUG_0",
- "microblaze_0/DEBUG"
+ "MPOD_TXDIS_1",
+ "axi_gpio_mpod_txdis/GPIO2"
]
},
- "microblaze_0_interrupt": {
+ "axi_gpio_mpod_txdis_GPIO": {
"interface_ports": [
- "microblaze_0_axi_intc/interrupt",
- "microblaze_0/INTERRUPT"
+ "MPOD_TXDIS_0",
+ "axi_gpio_mpod_txdis/GPIO"
+ ]
+ },
+ "microblaze_0_axi_periph_M06_AXI": {
+ "interface_ports": [
+ "microblaze_0_axi_periph/M06_AXI",
+ "axi_gpio_resets/S_AXI"
]
},
"microblaze_0_intc_axi": {
"microblaze_0_axi_intc/s_axi"
]
},
- "microblaze_0_axi_periph_M03_AXI": {
+ "microblaze_0_axi_periph_M02_AXI": {
"interface_ports": [
- "microblaze_0_axi_periph/M03_AXI",
- "axi_gpio_mpod_los/S_AXI"
+ "microblaze_0_axi_periph/M02_AXI",
+ "axi_iic_0/S_AXI"
]
},
- "microblaze_0_axi_periph_M04_AXI": {
+ "microblaze_0_ilmb_1": {
"interface_ports": [
- "microblaze_0_axi_periph/M04_AXI",
- "axi_timer_0/S_AXI"
+ "microblaze_0/ILMB",
+ "microblaze_0_local_memory/ILMB"
]
},
- "axi_gpio_mpod_los_GPIO2": {
+ "microblaze_0_axi_periph_M04_AXI": {
"interface_ports": [
- "MPOD_LOS_1",
- "axi_gpio_mpod_los/GPIO2"
+ "microblaze_0_axi_periph/M04_AXI",
+ "axi_timer_0/S_AXI"
]
},
- "axi_gpio_mpod_txdis_GPIO2": {
+ "axi_gpio_resets_GPIO": {
"interface_ports": [
- "MPOD_TXDIS_1",
- "axi_gpio_mpod_txdis/GPIO2"
+ "EXT_RESETS_N",
+ "axi_gpio_resets/GPIO"
]
},
"microblaze_0_axi_dp": {
"MPOD_LOS_0",
"axi_gpio_mpod_los/GPIO"
]
- },
- "microblaze_0_axi_periph_M06_AXI": {
- "interface_ports": [
- "microblaze_0_axi_periph/M06_AXI",
- "axi_gpio_resets/S_AXI"
- ]
}
},
"nets": {
set_property PACKAGE_PIN R18 [get_ports SI5345_I2C_SEL]
set_property IOSTANDARD LVCMOS18 [get_ports SI5345_I2C_SEL]
-set_property PACKAGE_PIN P16 [get_ports SI5345_LOL_N]
-set_property IOSTANDARD LVCMOS18 [get_ports SI5345_LOL_N]
-
set_property PACKAGE_PIN W11 [get_ports PCA9546A_DEVS_RESET_N]
set_property IOSTANDARD LVTTL [get_ports PCA9546A_DEVS_RESET_N]
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/ip/clk_wiz_1/clk_wiz_1.xci">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
<File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/common/gth_xcku_init.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
MPOD_TX2_RESET_N : out std_logic;
SI5345_RST_N : out std_logic;
SI5345_I2C_SEL : out std_logic;
- SI5345_LOL_N : in std_logic;
PCA9546A_DEVS_RESET_N : out std_logic;
PCA9546A_PCIE_RESET_N : out std_logic;
PEX_I2C_SEL0 : out std_logic;
);
end component;
- component clk_wiz_1
- port (
- clk_out1 : out std_logic;
- reset : in std_logic;
- locked : out std_logic;
- clk_in1_p : in std_logic;
- clk_in1_n : in std_logic
- );
- end component;
-
+ signal clk_200_ibuf : std_logic;
signal baseclk_100 : std_logic;
- signal baseclk_locked : std_logic;
signal baseclk_out : std_logic;
- signal microblaze_reset : std_logic;
- signal resets_from_microblaze : std_logic_vector(7 downto 0);
+ signal mb_ext_resets_n : std_logic_vector(7 downto 0);
+ signal mb_sysclk_reset : std_logic;
- signal sysclk_reset : std_logic;
signal sysclk_100 : std_logic;
signal sysclk_200 : std_logic;
signal sysclk_locked : std_logic;
signal ms_count : integer range 0 to MS_PERIOD_COUNTS - 1 := 0;
signal trg_out : std_logic := '0';
begin
- THE_BASECLK : clk_wiz_1
+ IBUFDS_baseclk : IBUFDS
port map (
- clk_out1 => baseclk_100,
- reset => '0',
- locked => baseclk_locked,
- clk_in1_p => CLK_200_P,
- clk_in1_n => CLK_200_N
+ O => clk_200_ibuf,
+ I => CLK_200_P,
+ IB => CLK_200_N
+ );
+
+ BUFGCE_DIV_baseclk : BUFGCE_DIV
+ generic map (
+ BUFGCE_DIVIDE => 2,
+ IS_CE_INVERTED => '0',
+ IS_CLR_INVERTED => '0',
+ IS_I_INVERTED => '0'
+ )
+ port map (
+ O => baseclk_100,
+ CE => '1',
+ CLR => '0',
+ I => clk_200_ibuf
);
- microblaze_reset <= not baseclk_locked;
ODDRE1_baseclk : ODDRE1
generic map (
C => baseclk_100,
D1 => '1',
D2 => '0',
- SR => microblaze_reset
+ SR => '0'
);
OBUFDS_baseclk : OBUFDS
I => baseclk_out
);
- sysclk_reset <= not SI5345_LOL_N;
THE_SYSCLK : clk_wiz_0
port map (
clk_out1 => sysclk_100,
clk_out2 => sysclk_200,
- reset => sysclk_reset,
+ reset => mb_sysclk_reset,
locked => sysclk_locked,
clk_in1_p => SI5345_OUT7_P,
clk_in1_n => SI5345_OUT7_N
THE_VIO : vio_0
port map (
- clk => sysclk_100,
+ clk => baseclk_100,
probe_in0(11 downto 0) => mpod_a_los,
probe_in0(23 downto 12) => mpod_b_los,
probe_in0(35 downto 24) => mpod_c_los,
design_1_wrapper_i : entity work.design_1_wrapper
port map (
CLK => baseclk_100,
+ EXT_RESETS_N_tri_o => mb_ext_resets_n,
I2C_scl_io => SCL,
I2C_sda_io => SDA,
MPOD_LOS_0_tri_o(11 downto 0) => mpod_a_los,
MPOD_TXDIS_0_tri_i(23 downto 12) => mpod_b_txdis,
MPOD_TXDIS_1_tri_i(11 downto 0) => mpod_c_txdis,
MPOD_TXDIS_1_tri_i(23 downto 12) => mpod_d_txdis,
- RESET => microblaze_reset,
- RESETS_tri_o => resets_from_microblaze
+ RESET => '0',
+ SYSCLK_RESET_tri_o(0) => mb_sysclk_reset
+
);
- MPOD_RX1_RESET_N <= resets_from_microblaze(0);
- MPOD_RX2_RESET_N <= resets_from_microblaze(1);
- MPOD_TX1_RESET_N <= resets_from_microblaze(2);
- MPOD_TX2_RESET_N <= resets_from_microblaze(3);
- SI5345_RST_N <= resets_from_microblaze(4);
- PCA9546A_DEVS_RESET_N <= resets_from_microblaze(5);
- PCA9546A_PCIE_RESET_N <= resets_from_microblaze(6);
- UC_RESET_N <= resets_from_microblaze(7);
+ MPOD_RX1_RESET_N <= mb_ext_resets_n(0);
+ MPOD_RX2_RESET_N <= mb_ext_resets_n(1);
+ MPOD_TX1_RESET_N <= mb_ext_resets_n(2);
+ MPOD_TX2_RESET_N <= mb_ext_resets_n(3);
+ SI5345_RST_N <= mb_ext_resets_n(4);
+ PCA9546A_DEVS_RESET_N <= mb_ext_resets_n(5);
+ PCA9546A_PCIE_RESET_N <= mb_ext_resets_n(6);
+ UC_RESET_N <= mb_ext_resets_n(7);
SI5345_I2C_SEL <= '1';
PEX_I2C_SEL0 <= '1';
PEX_I2C_SEL1 <= '1';
#include "Si5345-RevD-CRI_100E-Registers.h"
#define NUM_PAGES (12)
-#define SUCCESS (0)
-#define ERR_SEND (1)
-#define ERR_RECEIVE (2)
-#define ERR_PAGE_NUM (3)
+#define SI5345_ADDRESS (0x68)
+#define SI5345_LOL_REGISTER (0x000E)
+#define SI5345_LOL_MASK (0x02)
+
+#define PCA9546A_ADDRESS (0x70)
+#define PCA9546A_PORT_MASK_0 (0x01)
+#define PCA9546A_PORT_MASK_1 (0x02)
+#define PCA9546A_PORT_MASK_2 (0x04)
+#define PCA9546A_PORT_MASK_3 (0x08)
+
+#define SUCCESS (0)
+#define ERR_SEND (1)
+#define ERR_RECEIVE (2)
+#define ERR_PAGE_NUM (3)
+#define ERR_TIMEOUT (4)
static int read_reg(u8 addr, u8 reg, u8 *val);
static int write_reg(u8 addr, u8 reg, u8 val);
static int write_pca9546a_ctrl_reg(u8 val);
static int set_si5345_page(u8 page);
static int write_si5345_regs();
+static int wait_si5345_lock();
static int update_mpods();
int main()
{
- int res;
+ int res;
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheEnable();
Xil_DCacheEnable();
#endif
- print("Resetting external devices.\r\n");
- XGpio_WriteReg(XPAR_AXI_GPIO_RESETS_BASEADDR,
- (0 * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET, 0x00000000);
- usleep(1);
- XGpio_WriteReg(XPAR_AXI_GPIO_RESETS_BASEADDR,
- (0 * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET, 0xFFFFFFFF);
+ print("Asserting logic reset.\r\n");
+ /* (active-high) */
+ XGpio_WriteReg(XPAR_AXI_GPIO_RESETS_BASEADDR, XGPIO_DATA2_OFFSET,
+ 0xFFFFFFFF);
- print("\r\n");
- print("Writing PCA9546A control register.\r\n");
- while ((res = write_pca9546a_ctrl_reg(0x04)) != SUCCESS) {
- xil_printf("Error %d\r\n", res);
- sleep(1);
- }
- print("OK\r\n");
+ for (;;) {
+ print("Resetting external devices.\r\n");
+ /* (active-low) */
+ XGpio_WriteReg(XPAR_AXI_GPIO_RESETS_BASEADDR, XGPIO_DATA_OFFSET,
+ 0x00000000);
+ usleep(1);
+ XGpio_WriteReg(XPAR_AXI_GPIO_RESETS_BASEADDR, XGPIO_DATA_OFFSET,
+ 0xFFFFFFFF);
+
+ print("\r\n");
+ print("Activating PCA9546A port with Si5345.\r\n");
+ if ((res = write_pca9546a_ctrl_reg(PCA9546A_PORT_MASK_2)) != SUCCESS) {
+ xil_printf("Error %d\r\n", res);
+ continue;
+ }
+ print("OK\r\n");
- print("Writing Si5345 registers.\r\n");
- while ((res = write_si5345_regs()) != SUCCESS) {
- xil_printf("Error %d\r\n", res);
- sleep(1);
- }
- print("OK\r\n");
+ print("Writing Si5345 registers.\r\n");
+ if ((res = write_si5345_regs()) != SUCCESS) {
+ xil_printf("Error %d\r\n", res);
+ continue;
+ }
+ print("OK\r\n");
- print("Writing PCA9546A control register.\r\n");
- while ((res = write_pca9546a_ctrl_reg(0x08)) != SUCCESS) {
- xil_printf("Error %d\r\n", res);
- sleep(1);
- }
- print("OK\r\n");
+ print("Waiting for Si5345 lock.\r\n");
+ if ((res = wait_si5345_lock()) != SUCCESS) {
+ xil_printf("Error %d\r\n", res);
+ continue;
+ }
+ print("OK\r\n");
- print("Entering register R/W loop.\r\n");
- for (;;) {
- if (update_mpods() == SUCCESS)
- print(".");
- else
- print("E");
+ print("Deasserting logic reset.\r\n");
+ /* (active-high) */
+ XGpio_WriteReg(XPAR_AXI_GPIO_RESETS_BASEADDR, XGPIO_DATA2_OFFSET,
+ 0x00000000);
- sleep(1);
+ print("Activating PCA9546A port with MiniPODs.\r\n");
+ if ((res = write_pca9546a_ctrl_reg(PCA9546A_PORT_MASK_3)) != SUCCESS) {
+ xil_printf("Error %d\r\n", res);
+ continue;
+ }
+ print("OK\r\n");
+
+ print("Entering MiniPOD register R/W loop.\r\n");
+ while ((res = update_mpods()) == SUCCESS) {
+ print(".");
+ sleep(1);
+ }
+ xil_printf("Error %d\r\n", res);
}
#ifdef XPAR_MICROBLAZE_USE_DCACHE
static int write_pca9546a_ctrl_reg(u8 val)
{
- if (XIic_Send(XPAR_IIC_0_BASEADDR, 0x70, &val, 1, XIIC_STOP) != 1)
+ if (XIic_Send(XPAR_IIC_0_BASEADDR, PCA9546A_ADDRESS, &val, 1, XIIC_STOP) != 1)
return ERR_SEND;
return SUCCESS;
if (page >= NUM_PAGES)
return ERR_PAGE_NUM;
- return write_reg(0x68, 0x01, page);
+ return write_reg(SI5345_ADDRESS, 0x01, page);
}
static int write_si5345_regs()
return res;
}
- if ((res = write_reg(0x68, addr & 0xFF, val)) != SUCCESS)
- return res;
+ if ((res = write_reg(SI5345_ADDRESS, addr & 0xFF, val)) != SUCCESS)
+ return res;
// Required wait time according to the registers file
if (i == 2)
}
+static int wait_si5345_lock()
+{
+ int res;
+ int count;
+ u8 val;
+
+ if ((res = set_si5345_page((SI5345_LOL_REGISTER >> 8) & 0xFF)) != SUCCESS)
+ return res;
+
+ for (count = 0; count < 100; ++count) {
+ print(".");
+ res = read_reg(SI5345_ADDRESS, (SI5345_LOL_REGISTER & 0xFF), &val);
+ if (res != SUCCESS)
+ return res;
+ if ((val & SI5345_LOL_MASK) == 0)
+ return SUCCESS;
+ usleep(100000);
+ }
+
+ return ERR_TIMEOUT;
+}
+
+
static int update_mpods()
{
// 30/2C is RX/TX-MPOD A
// RX reg 10/TX reg 93 7..0 is ch 7..0
// MTP fibers 12..1 correspond to MPOD ch's 11..0
- int res;
+ int res;
u32 gpio_val;
u8 val;
jspc29 / cri.git / commitdiff