use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---TODO: revisit trigger handling in trbnet manual
---TODO: what is the timing between timing trigger and LVL1_Trigger information?
+--TODO: should timing triggers be handled differently?
entity TriggerHandler is
--trigger handler
type trigger_handler_type is (idle,
- timing_trigger,
- no_timing_trigger,
- check_trigger_type,
- status_trigger,
- write_data_to_ipu,
- trigger_release_a,
- trigger_release_b,
- trigger_release_c,
- wait_trigger_release,
- ignore,
- wait_trigger_data_valid_a,
- wait_trigger_data_valid_b);
-
- type trigger_type_type is (t_timing,
- t_physics,
- t_status,
- t_ignore,
- t_unknown);
+ wait_valid_trigger_data,
+ decode_trg_data,
+ write_status,
+ write_data,
+ write_dummy,
+ data_finished1,
+ data_finished2,
+ trg_release);
signal trigger_handler_fsm : trigger_handler_type := idle;
- signal trigger_type : trigger_type_type := t_unknown;
signal wr_header_int : std_logic := '0';
signal wr_data_int : std_logic := '0';
signal wr_status_int : std_logic := '0';
trigger_handler_proc : process(clk_in) is
begin -- process trigger_handler_proc
if rising_edge(CLK_IN) then
- trigger_busy_int <= '1';
- fee_trg_release_int <= '0';
- wr_header_int <= '0';
- wr_data_int <= '0';
- wr_status_int <= '0';
- wr_dummy_int <= '0';
- valid_trigger_int <= '0';
- fee_data_finished_int <= '0';
- fee_trg_release_int <= '0';
- trigger_handler_fsm <= idle;
- if reset_in = '1' or LVL1_INVALID_TRG_IN = '1' or reset_trigger_state = '1' then
+ if reset_in = '1' or reset_trigger_state = '1' then
valid_trigger_int <= '0';
fee_data_finished_int <= '0';
fee_trg_release_int <= '0';
fee_trg_statusbit_int <= (others => '0');
- trigger_busy_int <= '1';
+ trigger_busy_int <= '0';
fee_trg_release_int <= '0';
wr_header_int <= '0';
wr_data_int <= '0';
wr_dummy_int <= '0';
trigger_handler_fsm <= idle;
else
+ valid_trigger_int <= '0';
+ fee_data_finished_int <= '0';
+ fee_trg_release_int <= '0';
+ fee_trg_statusbit_int <= (others => '0');
+ trigger_busy_int <= '0';
+ fee_trg_release_int <= '0';
+ wr_header_int <= '0';
+ wr_data_int <= '0';
+ wr_status_int <= '0';
+ wr_dummy_int <= '0';
+ if LVL1_INVALID_TRG_IN = '1' then
+ trigger_handler_fsm <= idle;
+ fee_trg_release_int <= '1';
+ end if;
case trigger_handler_fsm is
when idle =>
- trigger_busy_int <= '0';
trigger_handler_state <= x"01";
- if LVL1_VALID_TIMING_TRG_IN = '1' then
- wr_header_int <= '1';
- if bypass_trigger = '1' then
- trigger_type <= t_ignore;
- trigger_handler_fsm <= ignore;
- else
- trigger_type <= t_timing;
- trigger_handler_fsm <= timing_trigger;
- end if;
- elsif (LVL1_VALID_NOTIMING_TRG_IN = '1') then
- wr_header_int <= '1';
- if bypass_trigger = '1' then
- trigger_type <= t_ignore;
- trigger_handler_fsm <= ignore;
- else
- trigger_handler_fsm <= check_trigger_type;
- end if;
- end if;
+ -- trigger handling, ignore raw timing triggers for now
+ -- what about invalid triggers
+ if LVL1_VALID_TIMING_TRG_IN = '1' or LVL1_VALID_NOTIMING_TRG_IN = '1' then
+ trigger_handler_fsm <= wait_valid_trigger_data;
+ trigger_busy_int <= '1';
+ else
+ trigger_handler_fsm <= idle;
+ end if;
- when check_trigger_type =>
+ when wait_valid_trigger_data =>
trigger_handler_state <= x"02";
- if (LVL1_TRG_DATA_VALID_IN = '1') then
- if (LVL1_TRG_TYPE_IN = c_trigger_status_type) then
- trigger_type <= t_status;
- trigger_handler_fsm <= no_timing_trigger;
- elsif (LVL1_TRG_TYPE_IN = c_trigger_physics_type) then
- trigger_type <= t_physics;
- trigger_handler_fsm <= no_timing_trigger;
- else
- --unknown trigger
- trigger_type <= t_unknown;
- trigger_handler_fsm <= no_timing_trigger;
- end if;
- else
- trigger_handler_fsm <= check_trigger_type;
+ if LVL1_TRG_DATA_VALID_IN = '1' then
+ trigger_handler_fsm <= decode_trg_data;
end if;
- when timing_trigger => --starts mupix readout fsm
+ when decode_trg_data =>
trigger_handler_state <= x"03";
- valid_trigger_int <= '1';
- trigger_handler_fsm <= write_data_to_ipu;
-
- when no_timing_trigger =>
- trigger_handler_state <= x"04";
- if trigger_type = t_physics then
- trigger_handler_fsm <= timing_trigger;
- elsif trigger_type = t_status then
- trigger_handler_fsm <= status_trigger;
+ wr_header_int <= '1';
+ if bypass_trigger = '1' then
+ trigger_handler_fsm <= write_dummy;
else
- trigger_handler_fsm <= ignore;
+ if LVL1_TRG_TYPE_IN = c_trigger_physics_type then
+ trigger_handler_fsm <= write_data;
+ valid_trigger_int <= '1';
+ elsif LVL1_TRG_TYPE_IN = c_trigger_status_type then
+ trigger_handler_fsm <= write_status;
+ else
+ trigger_handler_fsm <= write_dummy;
+ end if;
end if;
- when ignore =>
- wr_dummy_int <= '1'; --write a dummy value to identify inactive FEE
+ when write_status =>
+ trigger_handler_state <= x"04";
+ wr_status_int <= '1';
+ trigger_handler_fsm <= data_finished1;
+
+ when write_dummy =>
trigger_handler_state <= x"05";
- trigger_handler_fsm <= wait_trigger_data_valid_b;
+ wr_dummy_int <= '1';
+ trigger_handler_fsm <= data_finished1;
- when status_trigger => --dummy implementation
+ when write_data =>
trigger_handler_state <= x"06";
- wr_status_int <= '1';
- trigger_handler_fsm <= wait_trigger_data_valid_b;
-
- when write_data_to_ipu =>
- trigger_handler_state <= x"0A";
wr_data_int <= '1';
if buffer_readout_end_int = "10" then
wr_data_int <= '0';
- trigger_handler_fsm <= wait_trigger_data_valid_a;
+ trigger_handler_fsm <= data_finished1;
else
- trigger_handler_fsm <= write_data_to_ipu;
+ trigger_handler_fsm <= write_data;
end if;
- when wait_trigger_data_valid_a =>
- trigger_handler_state <= x"0B";
- if LVL1_TRG_DATA_VALID_IN = '1' then
- trigger_handler_fsm <= wait_trigger_data_valid_b;
- end if;
-
- when wait_trigger_data_valid_b =>
- trigger_handler_state <= x"0C";
- trigger_handler_fsm <= trigger_release_a;
-
- when trigger_release_a =>
- trigger_handler_state <= x"0D";
- trigger_handler_fsm <= trigger_release_b;
+ when data_finished1 =>
+ trigger_handler_state <= x"07";
+ trigger_handler_fsm <= data_finished2;
- when trigger_release_b =>
- trigger_handler_state <= x"0E";
+ when data_finished2 =>
+ trigger_handler_state <= x"08";
+ trigger_handler_fsm <= trg_release;
fee_data_finished_int <= '1';
- trigger_handler_fsm <= trigger_release_c;
- when trigger_release_c =>
- trigger_handler_state <= x"0F";
+ when trg_release =>
+ trigger_handler_state <= x"09";
+ if LVL1_TRG_DATA_VALID_IN = '1' then
fee_trg_release_int <= '1';
- trigger_handler_fsm <= wait_trigger_release;
+ end if;
+ trigger_handler_fsm <= idle;
- when wait_trigger_release =>
- if (LVL1_TRG_DATA_VALID_IN = '1') then
- trigger_handler_fsm <= wait_trigger_release;
- else
- trigger_handler_fsm <= idle;
- end if;
end case;
end if;
end if;
trigger_rate_time_counter <= trigger_rate_time_counter + 1;
if valid_trigger_int = '1' then
valid_trigger_counter_t <= valid_trigger_counter_t + 1;
- elsif LVL1_INVALID_TRG_IN = '1' or (trigger_busy_int = '1' and timing_trigger_edge = "01") then
+ elsif LVL1_INVALID_TRG_IN = '1' then
invalid_trigger_counter_t <= invalid_trigger_counter_t + 1;
end if;
else
--Pseudo Data Inputs
data_wr_enable : in std_logic_vector(3 downto 0);
- data_in : in std_logic_vector(127 downto 0));
+ data_in : in std_logic_vector(160 downto 0));
end entity TriggerAndReadout;
signal fifo_full_i : std_logic_vector(c_mupix_links - 1 downto 0);
signal fifo_empty_i : std_logic_vector(c_mupix_links - 1 downto 0);
signal fifo_rden_i : std_logic_vector(c_mupix_links - 1 downto 0);
- signal fifo_dataout_i : std_logic_vector(c_mupix_links*32 - 1 downto 0);
+ signal fifo_dataout_i : std_logic_vector(c_mupix_links*40 - 1 downto 0);
begin -- architecture behavorial
MupixTRBReadout_1 : entity work.MupixTRBReadout
generic map (
g_mupix_links => c_mupix_links,
- g_cyc_mem_address_width => 8,
- g_datawidth => 32)
+ g_cyc_mem_address_width => 8)
port map (
clk => clk,
rst => reset,
fifo_gen : for J in 0 to 3 generate
STD_FIFO : entity work.STD_FIFO
generic map (
- data_width => 32,
+ data_width => 40,
fifo_depth => 16)
port map (
clk => clk,
rst => reset,
writeen => data_wr_enable(J),
- datain => data_in((J + 1)*32 - 1 downto J*32),
+ datain => data_in((J + 1)*40 - 1 downto J*40),
readen => fifo_rden_i(J),
- dataout => fifo_dataout_i((J + 1)*32 - 1 downto J*32),
+ dataout => fifo_dataout_i((J + 1)*40 - 1 downto J*40),
empty => fifo_empty_i(J),
full => fifo_full_i(J));
end generate fifo_gen;
signal slv_no_more_data_out : std_logic;
signal slv_unknown_addr_out : std_logic;
signal data_wr_enable : std_logic_vector(3 downto 0) := (others => '0');
- signal data_in : std_logic_vector(127 downto 0) := (others => '0');
+ signal data_in : std_logic_vector(160 downto 0) := (others => '0');
begin -- architecture sim
for i in 0 to 10 loop
data_wr_enable <= (others => '1');
for J in 0 to 3 loop
- data_in((J + 1)*32 - 1 downto J*32) <= x"CA" & std_logic_vector(to_unsigned(J, 8)) & std_logic_vector(to_unsigned(i, 16));
+ data_in((J + 1)*40 - 1 downto J*40) <= x"AACA" & std_logic_vector(to_unsigned(J, 8)) & std_logic_vector(to_unsigned(i, 16));
end loop; -- J
wait for clk_period;
end loop; -- i
jspc29 / trb3.git / commitdiff