add trb_net_xdna to components so that it is not needed in every project

diff --git a/trb_net16_endpoint_hades_full_gbe.vhd b/trb_net16_endpoint_hades_full_gbe.vhd
index 1bc5223a93ad0148bc789bf7ff71b8d3e4985710..ac38bc59fcd954b2a89406af92f5eda26eee826b 100644 (file)
--- a/trb_net16_endpoint_hades_full_gbe.vhd
+++ b/trb_net16_endpoint_hades_full_gbe.vhd
@@ -907,7 +907,7 @@ begin
             REGIO_ONEWIRE_MONITOR_OUT <= '0';
             REGIO_ONEWIRE_INOUT       <= '0';
             
-            XilinxDNA : entity work.trb_net_xdna
+            XilinxDNA : trb_net_xdna
               port map(
                 CLK      => CLK,
                 RESET    => RESET,