--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+use ieee.std_logic_arith.all;
+
+
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+entity system is
+
+end system;
+architecture system of system is
+ component hub
+ port (
+ LVDS_CLK_200P : in std_logic;
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ DBAD : out std_logic;
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DWAIT : out std_logic;
+ LOK : out std_logic_vector(16 downto 1);
+ RT : out std_logic_vector(16 downto 1);
+ TX_DIS : out std_logic_vector(16 downto 1);
+ IPLL : out std_logic;
+ OPLL : out std_logic;
+ SFP_INP_N : in std_logic_vector(15 downto 0);
+ SFP_INP_P : in std_logic_vector(15 downto 0);
+ SFP_OUT_N : out std_logic_vector(15 downto 0);
+ SFP_OUT_P : out std_logic_vector(15 downto 0);
+ FS_PE_11 : inout std_logic;
+ FS_PE : inout std_logic_vector(9 downto 8);
+ SFP_LOS : in std_logic_vector(16 downto 1);
+ OPT_DATA_IN : in std_logic_vector(255 downto 0);
+ OPT_DATA_OUT : out std_logic_vector(255 downto 0);
+ OPT_DATA_VALID_IN : in std_logic_vector(15 downto 0);
+ OPT_DATA_VALID_OUT : out std_logic_vector(15 downto 0));
+ end component;
+ component trb_v2b_fpga
+ generic (
+ RW_SYSTEM : integer range 0 to 5:=1;
+ TRBV2_TYPE : integer range 0 to 5:=0;
+ TRBNET_ENABLE : integer range 0 to 1:=0;
+ DTU_ENABLE : integer range 0 to 2:=2;
+ CTU_ENABLE : integer range 0 to 1:=0;
+ HADES_OLD_BUS_ENABLE : integer range 0 to 1:=0;
+ DSP_INT_ENABLE : integer range 0 to 1:=0;
+ SDRAM_INT_ENABLE : integer range 0 to 1:=0;
+ SCALERS_ENABLE : integer range 0 to 1:=0);
+ port (
+ VIRT_CLK : in std_logic;
+ VIRT_CLKB : in std_logic;
+ RESET_VIRT : in std_logic;
+ DBAD : out std_logic;
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DWAIT : out std_logic;
+ A_RESERVED : in std_logic;
+ A_TEMP : in std_logic;
+ B_RESERVED : in std_logic;
+ B_TEMP : in std_logic;
+ C_RESERVED : in std_logic;
+ C_TEMP : in std_logic;
+ D_RESERVED : in std_logic;
+ D_TEMP : in std_logic;
+ VIR_TRIG : in std_logic;
+ VIR_TRIGB : in std_logic;
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic;
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
+ TOKEN_IN : in std_logic;
+ TOKEN_OUT : out std_logic;
+ C_TOKEN_OUT_TTL : in std_logic;
+ GET_DATA : out std_logic;
+ A_DATA_READY : in std_logic;
+ B_DATA_READY : in std_logic;
+ C_DATA_READY : in std_logic;
+ D_DATA_READY : in std_logic;
+ REF_TDC_CLK : in std_logic;
+ REF_TDC_CLKB : in std_logic;
+ A_TDC_BU_RESET : out std_logic;
+ A_TDC_BU_RESETB : out std_logic;
+ A_TDC_EV_RESET : out std_logic;
+ A_TDC_EV_RESETB : out std_logic;
+ B_TDC_BU_RESET : out std_logic;
+ B_TDC_BU_RESETB : out std_logic;
+ B_TDC_EV_RESET : out std_logic;
+ B_TDC_EV_RESETB : out std_logic;
+ C_TDC_BU_RESET : out std_logic;
+ C_TDC_BU_RESETB : out std_logic;
+ C_TDC_EV_RESET : out std_logic;
+ C_TDC_EV_RESETB : out std_logic;
+ D_TDC_BU_RESET : out std_logic;
+ D_TDC_BU_RESETB : out std_logic;
+ D_TDC_EV_RESET : out std_logic;
+ D_TDC_EV_RESETB : out std_logic;
+ TDC_OUT : in std_logic_vector (31 downto 0);
+ TDC_RESET : out std_logic;
+ A_TRIGGER : out std_logic;
+ A_TRIGGERB : out std_logic;
+ B_TRIGGER : out std_logic;
+ B_TRIGGERB : out std_logic;
+ C_TRIGGER : out std_logic;
+ C_TRIGGERB : out std_logic;
+ D_TRIGGER : out std_logic;
+ D_TRIGGERB : out std_logic;
+ FS_PB : inout std_logic_vector (16 downto 0);
+ FS_PB_17 : in std_logic;
+ FS_PC : inout std_logic_vector (17 downto 0);
+ ETRAX_IRQ : out std_logic;
+ A_SCK : out std_logic;
+ A_SCKB : out std_logic;
+ A_SDI : in std_logic;
+ A_SDIB : in std_logic;
+ A_SDO : out std_logic;
+ A_SDOB : out std_logic;
+ A_CSB : out std_logic;
+ A_CS : out std_logic;
+ B_SCK : out std_logic;
+ B_SCKB : out std_logic;
+ B_SDI : in std_logic;
+ B_SDIB : in std_logic;
+ B_SDO : out std_logic;
+ B_SDOB : out std_logic;
+ B_CSB : out std_logic;
+ B_CS : out std_logic;
+ C_SCK : out std_logic;
+ C_SCKB : out std_logic;
+ C_SDI : in std_logic;
+ C_SDIB : in std_logic;
+ C_SDO : out std_logic;
+ C_SDOB : out std_logic;
+ C_CSB : out std_logic;
+ C_CS : out std_logic;
+ D_SCK : out std_logic;
+ D_SCKB : out std_logic;
+ D_SDI : in std_logic;
+ D_SDIB : in std_logic;
+ D_SDO : out std_logic;
+ D_SDOB : out std_logic;
+ D_CSB : out std_logic;
+ D_CS : out std_logic;
+ A_TEST1 : out std_logic;
+ A_TEST1B : out std_logic;
+ A_TEST2 : out std_logic;
+ A_TEST2B : out std_logic;
+ B_TEST1 : out std_logic;
+ B_TEST1B : out std_logic;
+ B_TEST2 : out std_logic;
+ B_TEST2B : out std_logic;
+ C_TEST1 : out std_logic;
+ C_TEST1B : out std_logic;
+ C_TEST2 : out std_logic;
+ C_TEST2B : out std_logic;
+ D_TEST1 : out std_logic;
+ D_TEST1B : out std_logic;
+ D_TEST2 : out std_logic;
+ D_TEST2B : out std_logic;
+ DSPADDR : out std_logic_vector (31 downto 0);
+ DSPDAT : inout std_logic_vector (31 downto 0);
+ DSP_ACK : in std_logic;
+ DSP_BM : inout std_logic;
+ DSP_BMS : out std_logic;
+ DSP_BOFF : out std_logic;
+ DSP_BRST : inout std_logic;
+ DSP_HBG : in std_logic;
+ DSP_HBR : out std_logic;
+ DSP_IRQ : out std_logic_vector (3 downto 0);
+ DSP_RD : out std_logic;
+ DSP_RESET : out std_logic;
+ DSP_RESET_OUT : in std_logic;
+ DSP_WRH : out std_logic;
+ DSP_WRL : out std_logic;
+ VSD_A : out std_logic_vector (12 downto 0);
+ VSD_BA : out std_logic_vector (1 downto 0);
+ VSD_CAS : out std_logic;
+ VSD_CKE : out std_logic;
+ VSD_CLOCK : out std_logic;
+ VSD_CSEH : out std_logic;
+ VSD_CSEL : out std_logic;
+ VSD_D : inout std_logic_vector (31 downto 0);
+ VSD_DQML : out std_logic_vector (3 downto 0);
+ VSD_RAS : out std_logic;
+ VSD_WE : out std_logic;
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector (15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector (15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_TX_DIS : out std_logic;
+ SFP_TX_FAULT : in std_logic;
+ ADDON_TO_TRB_CLKINN : in std_logic;
+ ADDON_TO_TRB_CLKINP : in std_logic;
+ ADO_LV : in std_logic_vector(51 downto 0);
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ VIRT_TCK : out std_logic;
+ VIRT_TDI : out std_logic;
+ VIRT_TDO : in std_logic;
+ VIRT_TMS : out std_logic;
+ VIRT_TRST : out std_logic);
+ end component;
+ component trb_v2b_fpga_cts
+ generic (
+ RW_SYSTEM : integer range 0 to 5:=1;
+ TRBV2_TYPE : integer range 0 to 5:=5;
+ TRBNET_ENABLE : integer range 0 to 1:=0;
+ DTU_ENABLE : integer range 0 to 2:=2;
+ CTU_ENABLE : integer range 0 to 1:=0;
+ HADES_OLD_BUS_ENABLE : integer range 0 to 1:=0;
+ DSP_INT_ENABLE : integer range 0 to 1:=0;
+ SDRAM_INT_ENABLE : integer range 0 to 1:=0;
+ SCALERS_ENABLE : integer range 0 to 1:=0);
+ port (
+ VIRT_CLK : in std_logic;
+ VIRT_CLKB : in std_logic;
+ RESET_VIRT : in std_logic;
+ DBAD : out std_logic;
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DWAIT : out std_logic;
+ A_RESERVED : in std_logic;
+ A_TEMP : in std_logic;
+ B_RESERVED : in std_logic;
+ B_TEMP : in std_logic;
+ C_RESERVED : in std_logic;
+ C_TEMP : in std_logic;
+ D_RESERVED : in std_logic;
+ D_TEMP : in std_logic;
+ VIR_TRIG : in std_logic;
+ VIR_TRIGB : in std_logic;
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic;
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
+ TOKEN_IN : in std_logic;
+ TOKEN_OUT : out std_logic;
+ C_TOKEN_OUT_TTL : in std_logic;
+ GET_DATA : out std_logic;
+ A_DATA_READY : in std_logic;
+ B_DATA_READY : in std_logic;
+ C_DATA_READY : in std_logic;
+ D_DATA_READY : in std_logic;
+ REF_TDC_CLK : in std_logic;
+ REF_TDC_CLKB : in std_logic;
+ A_TDC_BU_RESET : out std_logic;
+ A_TDC_BU_RESETB : out std_logic;
+ A_TDC_EV_RESET : out std_logic;
+ A_TDC_EV_RESETB : out std_logic;
+ B_TDC_BU_RESET : out std_logic;
+ B_TDC_BU_RESETB : out std_logic;
+ B_TDC_EV_RESET : out std_logic;
+ B_TDC_EV_RESETB : out std_logic;
+ C_TDC_BU_RESET : out std_logic;
+ C_TDC_BU_RESETB : out std_logic;
+ C_TDC_EV_RESET : out std_logic;
+ C_TDC_EV_RESETB : out std_logic;
+ D_TDC_BU_RESET : out std_logic;
+ D_TDC_BU_RESETB : out std_logic;
+ D_TDC_EV_RESET : out std_logic;
+ D_TDC_EV_RESETB : out std_logic;
+ TDC_OUT : in std_logic_vector (31 downto 0);
+ TDC_RESET : out std_logic;
+ A_TRIGGER : out std_logic;
+ A_TRIGGERB : out std_logic;
+ B_TRIGGER : out std_logic;
+ B_TRIGGERB : out std_logic;
+ C_TRIGGER : out std_logic;
+ C_TRIGGERB : out std_logic;
+ D_TRIGGER : out std_logic;
+ D_TRIGGERB : out std_logic;
+ FS_PB : inout std_logic_vector (16 downto 0);
+ FS_PB_17 : in std_logic;
+ FS_PC : inout std_logic_vector (17 downto 0);
+ ETRAX_IRQ : out std_logic;
+ A_SCK : out std_logic;
+ A_SCKB : out std_logic;
+ A_SDI : in std_logic;
+ A_SDIB : in std_logic;
+ A_SDO : out std_logic;
+ A_SDOB : out std_logic;
+ A_CSB : out std_logic;
+ A_CS : out std_logic;
+ B_SCK : out std_logic;
+ B_SCKB : out std_logic;
+ B_SDI : in std_logic;
+ B_SDIB : in std_logic;
+ B_SDO : out std_logic;
+ B_SDOB : out std_logic;
+ B_CSB : out std_logic;
+ B_CS : out std_logic;
+ C_SCK : out std_logic;
+ C_SCKB : out std_logic;
+ C_SDI : in std_logic;
+ C_SDIB : in std_logic;
+ C_SDO : out std_logic;
+ C_SDOB : out std_logic;
+ C_CSB : out std_logic;
+ C_CS : out std_logic;
+ D_SCK : out std_logic;
+ D_SCKB : out std_logic;
+ D_SDI : in std_logic;
+ D_SDIB : in std_logic;
+ D_SDO : out std_logic;
+ D_SDOB : out std_logic;
+ D_CSB : out std_logic;
+ D_CS : out std_logic;
+ A_TEST1 : out std_logic;
+ A_TEST1B : out std_logic;
+ A_TEST2 : out std_logic;
+ A_TEST2B : out std_logic;
+ B_TEST1 : out std_logic;
+ B_TEST1B : out std_logic;
+ B_TEST2 : out std_logic;
+ B_TEST2B : out std_logic;
+ C_TEST1 : out std_logic;
+ C_TEST1B : out std_logic;
+ C_TEST2 : out std_logic;
+ C_TEST2B : out std_logic;
+ D_TEST1 : out std_logic;
+ D_TEST1B : out std_logic;
+ D_TEST2 : out std_logic;
+ D_TEST2B : out std_logic;
+ DSPADDR : out std_logic_vector (31 downto 0);
+ DSPDAT : inout std_logic_vector (31 downto 0);
+ DSP_ACK : in std_logic;
+ DSP_BM : inout std_logic;
+ DSP_BMS : out std_logic;
+ DSP_BOFF : out std_logic;
+ DSP_BRST : inout std_logic;
+ DSP_HBG : in std_logic;
+ DSP_HBR : out std_logic;
+ DSP_IRQ : out std_logic_vector (3 downto 0);
+ DSP_RD : out std_logic;
+ DSP_RESET : out std_logic;
+ DSP_RESET_OUT : in std_logic;
+ DSP_WRH : out std_logic;
+ DSP_WRL : out std_logic;
+ VSD_A : out std_logic_vector (12 downto 0);
+ VSD_BA : out std_logic_vector (1 downto 0);
+ VSD_CAS : out std_logic;
+ VSD_CKE : out std_logic;
+ VSD_CLOCK : out std_logic;
+ VSD_CSEH : out std_logic;
+ VSD_CSEL : out std_logic;
+ VSD_D : inout std_logic_vector (31 downto 0);
+ VSD_DQML : out std_logic_vector (3 downto 0);
+ VSD_RAS : out std_logic;
+ VSD_WE : out std_logic;
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector (15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector (15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_TX_DIS : out std_logic;
+ SFP_TX_FAULT : in std_logic;
+ ADDON_TO_TRB_CLKINN : in std_logic;
+ ADDON_TO_TRB_CLKINP : in std_logic;
+ ADO_LV : in std_logic_vector(51 downto 0);
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ VIRT_TCK : out std_logic;
+ VIRT_TDI : out std_logic;
+ VIRT_TDO : in std_logic;
+ VIRT_TMS : out std_logic;
+ VIRT_TRST : out std_logic);
+ end component;
+ constant HOW_MANY_ACTIVE_TRBS : integer := 15;
+ --hub
+ signal LVDS_CLK_200P_i : std_logic;
+ signal HUB_ADO_TTL_i : std_logic_vector(46 downto 0);
+ signal DBAD_i : std_logic;
+ signal DGOOD_i : std_logic;
+ signal DINT_i : std_logic;
+ signal DWAIT_i : std_logic;
+ signal LOK_i : std_logic_vector(16 downto 1);
+ signal RT_i : std_logic_vector(16 downto 1);
+ signal TX_DIS_i : std_logic_vector(16 downto 1);
+ signal IPLL_i : std_logic;
+ signal OPLL_i : std_logic;
+ signal SFP_INP_N_i : std_logic_vector(15 downto 0);
+ signal SFP_INP_P_i : std_logic_vector(15 downto 0);
+ signal SFP_OUT_N_i : std_logic_vector(15 downto 0);
+ signal SFP_OUT_P_i : std_logic_vector(15 downto 0);
+ signal OPT_DATA_IN_i : std_logic_vector(255 downto 0);
+ signal OPT_DATA_OUT_i : std_logic_vector(255 downto 0);
+ signal OPT_DATA_VALID_IN_i : std_logic_vector(15 downto 0);
+ signal OPT_DATA_VALID_OUT_i : std_logic_vector(15 downto 0);
+
+ --trb
+ signal VIRT_CLK_i : std_logic;
+ signal VIRT_CLKB_i : std_logic;
+ signal RESET_VIRT_i : std_logic;
+-- signal DBAD_i : std_logic;
+-- signal DGOOD_i : std_logic;
+-- signal DINT_i : std_logic;
+-- signal DWAIT_i : std_logic;
+ signal A_RESERVED_i : std_logic;
+ signal A_TEMP_i : std_logic;
+ signal B_RESERVED_i : std_logic;
+ signal B_TEMP_i : std_logic;
+ signal C_RESERVED_i : std_logic;
+ signal C_TEMP_i : std_logic;
+ signal D_RESERVED_i : std_logic;
+ signal D_TEMP_i : std_logic;
+ signal VIR_TRIG_i : std_logic;
+ signal VIR_TRIGB_i : std_logic;
+ signal A_TDC_ERROR_i : std_logic;
+ signal B_TDC_ERROR_i : std_logic;
+ signal C_TDC_ERROR_i : std_logic;
+ signal D_TDC_ERROR_i : std_logic;
+ signal A_TDC_POWERUP_i : std_logic;
+ signal B_TDC_POWERUP_i : std_logic;
+ signal C_TDC_POWERUP_i : std_logic;
+ signal D_TDC_POWERUP_i : std_logic;
+ signal TOKEN_IN_i : std_logic_vector(HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal TOKEN_OUT_i : std_logic_vector(HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal C_TOKEN_OUT_TTL_i : std_logic;
+ signal GET_DATA_i : std_logic;
+ signal A_DATA_READY_i : std_logic_vector(HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal B_DATA_READY_i : std_logic_vector(HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal C_DATA_READY_i : std_logic_vector(HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal D_DATA_READY_i : std_logic_vector(HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal REF_TDC_CLK_i : std_logic;
+ signal REF_TDC_CLKB_i : std_logic;
+ signal A_TDC_BU_RESET_i : std_logic;
+ signal A_TDC_BU_RESETB_i : std_logic;
+ signal A_TDC_EV_RESET_i : std_logic;
+ signal A_TDC_EV_RESETB_i : std_logic;
+ signal B_TDC_BU_RESET_i : std_logic;
+ signal B_TDC_BU_RESETB_i : std_logic;
+ signal B_TDC_EV_RESET_i : std_logic;
+ signal B_TDC_EV_RESETB_i : std_logic;
+ signal C_TDC_BU_RESET_i : std_logic;
+ signal C_TDC_BU_RESETB_i : std_logic;
+ signal C_TDC_EV_RESET_i : std_logic;
+ signal C_TDC_EV_RESETB_i : std_logic;
+ signal D_TDC_BU_RESET_i : std_logic;
+ signal D_TDC_BU_RESETB_i : std_logic;
+ signal D_TDC_EV_RESET_i : std_logic;
+ signal D_TDC_EV_RESETB_i : std_logic;
+ signal TDC_OUT_i : std_logic_vector (HOW_MANY_ACTIVE_TRBS*32-1 downto 0);
+ signal TDC_RESET_i : std_logic;
+ signal A_TRIGGER_i : std_logic;
+ signal A_TRIGGERB_i : std_logic;
+ signal B_TRIGGER_i : std_logic;
+ signal B_TRIGGERB_i : std_logic;
+ signal C_TRIGGER_i : std_logic;
+ signal C_TRIGGERB_i : std_logic;
+ signal D_TRIGGER_i : std_logic;
+ signal D_TRIGGERB_i : std_logic;
+ signal FS_PB_i : std_logic_vector (17*HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal FS_PB_17_i : std_logic_vector(HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal FS_PC_i : std_logic_vector (18*HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal ETRAX_IRQ_i : std_logic;
+ signal A_SCK_i : std_logic;
+ signal A_SCKB_i : std_logic;
+ signal A_SDI_i : std_logic;
+ signal A_SDIB_i : std_logic;
+ signal A_SDO_i : std_logic;
+ signal A_SDOB_i : std_logic;
+ signal A_CSB_i : std_logic;
+ signal A_CS_i : std_logic;
+ signal B_SCK_i : std_logic;
+ signal B_SCKB_i : std_logic;
+ signal B_SDI_i : std_logic;
+ signal B_SDIB_i : std_logic;
+ signal B_SDO_i : std_logic;
+ signal B_SDOB_i : std_logic;
+ signal B_CSB_i : std_logic;
+ signal B_CS_i : std_logic;
+ signal C_SCK_i : std_logic;
+ signal C_SCKB_i : std_logic;
+ signal C_SDI_i : std_logic;
+ signal C_SDIB_i : std_logic;
+ signal C_SDO_i : std_logic;
+ signal C_SDOB_i : std_logic;
+ signal C_CSB_i : std_logic;
+ signal C_CS_i : std_logic;
+ signal D_SCK_i : std_logic;
+ signal D_SCKB_i : std_logic;
+ signal D_SDI_i : std_logic;
+ signal D_SDIB_i : std_logic;
+ signal D_SDO_i : std_logic;
+ signal D_SDOB_i : std_logic;
+ signal D_CSB_i : std_logic;
+ signal D_CS_i : std_logic;
+ signal A_TEST1_i : std_logic;
+ signal A_TEST1B_i : std_logic;
+ signal A_TEST2_i : std_logic;
+ signal A_TEST2B_i : std_logic;
+ signal B_TEST1_i : std_logic;
+ signal B_TEST1B_i : std_logic;
+ signal B_TEST2_i : std_logic;
+ signal B_TEST2B_i : std_logic;
+ signal C_TEST1_i : std_logic;
+ signal C_TEST1B_i : std_logic;
+ signal C_TEST2_i : std_logic;
+ signal C_TEST2B_i : std_logic;
+ signal D_TEST1_i : std_logic;
+ signal D_TEST1B_i : std_logic;
+ signal D_TEST2_i : std_logic;
+ signal D_TEST2B_i : std_logic;
+ signal DSPADDR_i : std_logic_vector (31 downto 0);
+ signal DSPDAT_i : std_logic_vector (31 downto 0);
+ signal DSP_ACK_i : std_logic;
+ signal DSP_BM_i : std_logic;
+ signal DSP_BMS_i : std_logic;
+ signal DSP_BOFF_i : std_logic;
+ signal DSP_BRST_i : std_logic;
+ signal DSP_HBG_i : std_logic;
+ signal DSP_HBR_i : std_logic;
+ signal DSP_IRQ_i : std_logic_vector (3 downto 0);
+ signal DSP_RD_i : std_logic;
+ signal DSP_RESET_i : std_logic;
+ signal DSP_RESET_OUT_i : std_logic;
+ signal DSP_WRH_i : std_logic;
+ signal DSP_WRL_i : std_logic;
+ signal VSD_A_i : std_logic_vector (12 downto 0);
+ signal VSD_BA_i : std_logic_vector (1 downto 0);
+ signal VSD_CAS_i : std_logic;
+ signal VSD_CKE_i : std_logic;
+ signal VSD_CLOCK_i : std_logic;
+ signal VSD_CSEH_i : std_logic;
+ signal VSD_CSEL_i : std_logic;
+ signal VSD_D_i : std_logic_vector (31 downto 0);
+ signal VSD_DQML_i : std_logic_vector (3 downto 0);
+ signal VSD_RAS_i : std_logic;
+ signal VSD_WE_i : std_logic;
+ signal TLK_CLK_i : std_logic;
+ signal TLK_ENABLE_i : std_logic;
+ signal TLK_LCKREFN_i : std_logic;
+ signal TLK_LOOPEN_i : std_logic;
+ signal TLK_PRBSEN_i : std_logic;
+ signal TLK_RXD_i : std_logic_vector (15 downto 0);
+ signal TLK_RX_CLK_i : std_logic;
+ signal TLK_RX_DV_i : std_logic;
+ signal TLK_RX_ER_i : std_logic;
+ signal TLK_TXD_i : std_logic_vector (15 downto 0);
+ signal TLK_TX_EN_i : std_logic;
+ signal TLK_TX_ER_i : std_logic;
+ signal SFP_LOS_i : std_logic;
+ signal SFP_TX_DIS_i : std_logic;
+ signal SFP_TX_FAULT_i : std_logic;
+ signal ADDON_TO_TRB_CLKINN_i : std_logic;
+ signal ADDON_TO_TRB_CLKINP_i : std_logic;
+ signal ADO_LV_i : std_logic_vector(51 downto 0);
+ signal ADO_TTL_i : std_logic_vector(46 downto 0);
+ signal VIRT_TCK_i : std_logic;
+ signal VIRT_TDI_i : std_logic;
+ signal VIRT_TDO_i : std_logic;
+ signal VIRT_TMS_i : std_logic;
+ signal VIRT_TRST_i : std_logic;
+
+ --cts
+ signal CTS_VIRT_CLK_i : std_logic;
+ signal CTS_VIRT_CLKB_i : std_logic;
+ signal CTS_RESET_VIRT_i : std_logic;
+ signal CTS_DBAD_i : std_logic;
+ signal CTS_DGOOD_i : std_logic;
+ signal CTS_DINT_i : std_logic;
+ signal CTS_DWAIT_i : std_logic;
+ signal CTS_A_RESERVED_i : std_logic;
+ signal CTS_A_TEMP_i : std_logic;
+ signal CTS_B_RESERVED_i : std_logic;
+ signal CTS_B_TEMP_i : std_logic;
+ signal CTS_C_RESERVED_i : std_logic;
+ signal CTS_C_TEMP_i : std_logic;
+ signal CTS_D_RESERVED_i : std_logic;
+ signal CTS_D_TEMP_i : std_logic;
+ signal CTS_VIR_TRIG_i : std_logic;
+ signal CTS_VIR_TRIGB_i : std_logic;
+ signal CTS_A_TDC_ERROR_i : std_logic;
+ signal CTS_B_TDC_ERROR_i : std_logic;
+ signal CTS_C_TDC_ERROR_i : std_logic;
+ signal CTS_D_TDC_ERROR_i : std_logic;
+ signal CTS_A_TDC_POWERUP_i : std_logic;
+ signal CTS_B_TDC_POWERUP_i : std_logic;
+ signal CTS_C_TDC_POWERUP_i : std_logic;
+ signal CTS_D_TDC_POWERUP_i : std_logic;
+ signal CTS_TOKEN_IN_i : std_logic;
+ signal CTS_TOKEN_OUT_i : std_logic;
+ signal CTS_C_TOKEN_OUT_TTL_i : std_logic;
+ signal CTS_GET_DATA_i : std_logic;
+ signal CTS_A_DATA_READY_i : std_logic;
+ signal CTS_B_DATA_READY_i : std_logic;
+ signal CTS_C_DATA_READY_i : std_logic;
+ signal CTS_D_DATA_READY_i : std_logic;
+ signal CTS_REF_TDC_CLK_i : std_logic;
+ signal CTS_REF_TDC_CLKB_i : std_logic;
+ signal CTS_A_TDC_BU_RESET_i : std_logic;
+ signal CTS_A_TDC_BU_RESETB_i : std_logic;
+ signal CTS_A_TDC_EV_RESET_i : std_logic;
+ signal CTS_A_TDC_EV_RESETB_i : std_logic;
+ signal CTS_B_TDC_BU_RESET_i : std_logic;
+ signal CTS_B_TDC_BU_RESETB_i : std_logic;
+ signal CTS_B_TDC_EV_RESET_i : std_logic;
+ signal CTS_B_TDC_EV_RESETB_i : std_logic;
+ signal CTS_C_TDC_BU_RESET_i : std_logic;
+ signal CTS_C_TDC_BU_RESETB_i : std_logic;
+ signal CTS_C_TDC_EV_RESET_i : std_logic;
+ signal CTS_C_TDC_EV_RESETB_i : std_logic;
+ signal CTS_D_TDC_BU_RESET_i : std_logic;
+ signal CTS_D_TDC_BU_RESETB_i : std_logic;
+ signal CTS_D_TDC_EV_RESET_i : std_logic;
+ signal CTS_D_TDC_EV_RESETB_i : std_logic;
+ signal CTS_TDC_OUT_i : std_logic_vector (31 downto 0);
+ signal CTS_TDC_RESET_i : std_logic;
+ signal CTS_A_TRIGGER_i : std_logic;
+ signal CTS_A_TRIGGERB_i : std_logic;
+ signal CTS_B_TRIGGER_i : std_logic;
+ signal CTS_B_TRIGGERB_i : std_logic;
+ signal CTS_C_TRIGGER_i : std_logic;
+ signal CTS_C_TRIGGERB_i : std_logic;
+ signal CTS_D_TRIGGER_i : std_logic;
+ signal CTS_D_TRIGGERB_i : std_logic;
+ signal CTS_FS_PB_i : std_logic_vector (16 downto 0);
+ signal CTS_FS_PB_17_i : std_logic;
+ signal CTS_FS_PC_i : std_logic_vector (17 downto 0);
+ signal CTS_ETRAX_IRQ_i : std_logic;
+ signal CTS_A_SCK_i : std_logic;
+ signal CTS_A_SCKB_i : std_logic;
+ signal CTS_A_SDI_i : std_logic;
+ signal CTS_A_SDIB_i : std_logic;
+ signal CTS_A_SDO_i : std_logic;
+ signal CTS_A_SDOB_i : std_logic;
+ signal CTS_A_CSB_i : std_logic;
+ signal CTS_A_CS_i : std_logic;
+ signal CTS_B_SCK_i : std_logic;
+ signal CTS_B_SCKB_i : std_logic;
+ signal CTS_B_SDI_i : std_logic;
+ signal CTS_B_SDIB_i : std_logic;
+ signal CTS_B_SDO_i : std_logic;
+ signal CTS_B_SDOB_i : std_logic;
+ signal CTS_B_CSB_i : std_logic;
+ signal CTS_B_CS_i : std_logic;
+ signal CTS_C_SCK_i : std_logic;
+ signal CTS_C_SCKB_i : std_logic;
+ signal CTS_C_SDI_i : std_logic;
+ signal CTS_C_SDIB_i : std_logic;
+ signal CTS_C_SDO_i : std_logic;
+ signal CTS_C_SDOB_i : std_logic;
+ signal CTS_C_CSB_i : std_logic;
+ signal CTS_C_CS_i : std_logic;
+ signal CTS_D_SCK_i : std_logic;
+ signal CTS_D_SCKB_i : std_logic;
+ signal CTS_D_SDI_i : std_logic;
+ signal CTS_D_SDIB_i : std_logic;
+ signal CTS_D_SDO_i : std_logic;
+ signal CTS_D_SDOB_i : std_logic;
+ signal CTS_D_CSB_i : std_logic;
+ signal CTS_D_CS_i : std_logic;
+ signal CTS_A_TEST1_i : std_logic;
+ signal CTS_A_TEST1B_i : std_logic;
+ signal CTS_A_TEST2_i : std_logic;
+ signal CTS_A_TEST2B_i : std_logic;
+ signal CTS_B_TEST1_i : std_logic;
+ signal CTS_B_TEST1B_i : std_logic;
+ signal CTS_B_TEST2_i : std_logic;
+ signal CTS_B_TEST2B_i : std_logic;
+ signal CTS_C_TEST1_i : std_logic;
+ signal CTS_C_TEST1B_i : std_logic;
+ signal CTS_C_TEST2_i : std_logic;
+ signal CTS_C_TEST2B_i : std_logic;
+ signal CTS_D_TEST1_i : std_logic;
+ signal CTS_D_TEST1B_i : std_logic;
+ signal CTS_D_TEST2_i : std_logic;
+ signal CTS_D_TEST2B_i : std_logic;
+ signal CTS_DSPADDR_i : std_logic_vector (31 downto 0);
+ signal CTS_DSPDAT_i : std_logic_vector (31 downto 0);
+ signal CTS_DSP_ACK_i : std_logic;
+ signal CTS_DSP_BM_i : std_logic;
+ signal CTS_DSP_BMS_i : std_logic;
+ signal CTS_DSP_BOFF_i : std_logic;
+ signal CTS_DSP_BRST_i : std_logic;
+ signal CTS_DSP_HBG_i : std_logic;
+ signal CTS_DSP_HBR_i : std_logic;
+ signal CTS_DSP_IRQ_i : std_logic_vector (3 downto 0);
+ signal CTS_DSP_RD_i : std_logic;
+ signal CTS_DSP_RESET_i : std_logic;
+ signal CTS_DSP_RESET_OUT_i : std_logic;
+ signal CTS_DSP_WRH_i : std_logic;
+ signal CTS_DSP_WRL_i : std_logic;
+ signal CTS_VSD_A_i : std_logic_vector (12 downto 0);
+ signal CTS_VSD_BA_i : std_logic_vector (1 downto 0);
+ signal CTS_VSD_CAS_i : std_logic;
+ signal CTS_VSD_CKE_i : std_logic;
+ signal CTS_VSD_CLOCK_i : std_logic;
+ signal CTS_VSD_CSEH_i : std_logic;
+ signal CTS_VSD_CSEL_i : std_logic;
+ signal CTS_VSD_D_i : std_logic_vector (31 downto 0);
+ signal CTS_VSD_DQML_i : std_logic_vector (3 downto 0);
+ signal CTS_VSD_RAS_i : std_logic;
+ signal CTS_VSD_WE_i : std_logic;
+ signal CTS_TLK_CLK_i : std_logic;
+ signal CTS_TLK_ENABLE_i : std_logic;
+ signal CTS_TLK_LCKREFN_i : std_logic;
+ signal CTS_TLK_LOOPEN_i : std_logic;
+ signal CTS_TLK_PRBSEN_i : std_logic;
+ signal CTS_TLK_RXD_i : std_logic_vector (15 downto 0);
+ signal CTS_TLK_RX_CLK_i : std_logic;
+ signal CTS_TLK_RX_DV_i : std_logic;
+ signal CTS_TLK_RX_ER_i : std_logic;
+ signal CTS_TLK_TXD_i : std_logic_vector (15 downto 0);
+ signal CTS_TLK_TX_EN_i : std_logic;
+ signal CTS_TLK_TX_ER_i : std_logic;
+ signal CTS_SFP_LOS_i : std_logic;
+ signal CTS_SFP_TX_DIS_i : std_logic;
+ signal CTS_SFP_TX_FAULT_i : std_logic;
+ signal CTS_ADDON_TO_TRB_CLKINN_i : std_logic;
+ signal CTS_ADDON_TO_TRB_CLKINP_i : std_logic;
+ signal CTS_ADO_LV_i : std_logic_vector(51 downto 0);
+ signal CTS_ADO_TTL_i : std_logic_vector(46 downto 0);
+ signal CTS_VIRT_TCK_i : std_logic;
+ signal CTS_VIRT_TDI_i : std_logic;
+ signal CTS_VIRT_TDO_i : std_logic;
+ signal CTS_VIRT_TMS_i : std_logic;
+ signal CTS_VIRT_TRST_i : std_logic;
+
+ --
+ signal vulom_lvl1_tag : std_logic_vector(15 downto 0);
+ signal cts_etrax_busy : std_logic;
+ signal cts_rw_mode : std_logic_vector(15 downto 0);
+ signal cts_address : std_logic_vector(31 downto 0);
+ signal cts_data : std_logic_vector(31 downto 0);
+
+ signal hub_rw_mode : std_logic_vector(15 downto 0);
+ signal hub_address : std_logic_vector(31 downto 0);
+ signal hub_data : std_logic_vector(31 downto 0);
+ signal hub_sfp_los_i : std_logic_vector(16 downto 1);
+
+ signal etrax_busy : std_logic_vector(HOW_MANY_ACTIVE_TRBS-1 downto 0);
+ signal tdc_data_i : std_logic_vector(31 downto 0);
+
+ signal HUB_FS_PE_i : std_logic_vector(9 downto 8);
+ signal enable_channels : std_logic_vector(15 downto 0);
+
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- --------------------------------------------------------------------------
+ -- --------------------------------------------------------------------------
+ -- hub
+ -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ HUB_INST: hub
+ port map (
+ LVDS_CLK_200P => LVDS_CLK_200P_i,
+ ADO_TTL => open,
+ DBAD => DBAD_i,
+ DGOOD => DGOOD_i,
+ DINT => DINT_i,
+ DWAIT => DWAIT_i,
+ LOK => LOK_i,
+ RT => RT_i,
+ TX_DIS => TX_DIS_i,
+ IPLL => IPLL_i,
+ OPLL => OPLL_i,
+ SFP_INP_N => SFP_INP_N_i,
+ SFP_INP_P => SFP_INP_P_i,
+ SFP_OUT_N => SFP_OUT_N_i,
+ SFP_OUT_P => SFP_OUT_P_i,
+ FS_PE_11 => open,
+ FS_PE => HUB_FS_PE_i,
+ SFP_LOS => hub_sfp_los_i,
+ OPT_DATA_IN => OPT_DATA_IN_i,
+ OPT_DATA_OUT => OPT_DATA_OUT_i,
+ OPT_DATA_VALID_IN => OPT_DATA_VALID_IN_i,
+ OPT_DATA_VALID_OUT => OPT_DATA_VALID_OUT_i);
+ hub_sfp_los_i <= (others => '0');
+ ---------------------------------------------------------------------------
+ -- writing register
+ ---------------------------------------------------------------------------
+ CONVERT: process
+ begin -- process CONVERT
+ case HOW_MANY_ACTIVE_TRBS is
+ when 0 =>
+ hub_data <= x"0000" & x"0000";
+ when 1 =>
+ hub_data <= x"0000" & x"0002";
+ when 2 =>
+ hub_data <= x"0000" & x"0006";
+ when 3 =>
+ hub_data <= x"0000" & x"000e";
+ when 4 =>
+ hub_data <= x"0000" & x"001e";
+ when 5 =>
+ hub_data <= x"0000" & x"003e";
+ when 6 =>
+ hub_data <= x"0000" & x"007e";
+ when 7 =>
+ hub_data <= x"0000" & x"00fe";
+ when 8 =>
+ hub_data <= x"0000" & x"01fe";
+ when 9 =>
+ hub_data <= x"0000" & x"03fe";
+ when 10 =>
+ hub_data <= x"0000" & x"07fe";
+ when 11 =>
+ hub_data <= x"0000" & x"0ffe";
+ when 12 =>
+ hub_data <= x"0000" & x"1ffe";
+ when 13 =>
+ hub_data <= x"0000" & x"3ffe";
+ when 14 =>
+ hub_data <= x"0000" & x"7ffe";
+ when 15 =>
+ hub_data <= x"0000" & x"fffe";
+ when others =>
+ hub_data <= x"0000" & x"fffe";
+ end case;
+ wait;
+ end process CONVERT;
+
+ hub_etrax_int_test: process
+ begin
+
+ hub_rw_mode <= x"0000";
+ hub_address <= x"00000006";
+-- hub_data <= conv_std_logic_vector(HOW_MANY_ACTIVE_TRBS, 32);--(to_std_logic_vector)HOW_MANY_ACTIVE_TRBS*2;--x"00000100";
+-- hub_data <= x"0000" & enable_channels;
+ HUB_FS_PE_i(9) <= '0';
+ HUB_FS_PE_i(8) <= '0';
+ wait for 200 ns;
+ for rw_mode_counter in 0 to 15 loop
+ wait for 30 ns;
+ HUB_FS_PE_i(9) <= '0';
+ HUB_FS_PE_i(8) <= hub_rw_mode(rw_mode_counter);
+ wait for 30 ns;
+ HUB_FS_PE_i(9) <= '1';
+ HUB_FS_PE_i(8) <= hub_rw_mode(rw_mode_counter);
+ end loop;
+ wait for 30 ns;
+ for address_counter in 0 to 31 loop
+ wait for 30 ns;
+ HUB_FS_PE_i(9) <= '0';
+ HUB_FS_PE_i(8) <= hub_address(address_counter);
+ wait for 30 ns;
+ HUB_FS_PE_i(9) <= '1';
+ HUB_FS_PE_i(8) <= hub_address(address_counter);
+ end loop;
+ wait for 30 ns;
+ for data_counter in 0 to 31 loop
+ wait for 30 ns;
+ HUB_FS_PE_i(9) <= '0';
+ HUB_FS_PE_i(8) <= hub_data(data_counter);
+ wait for 30 ns;
+ HUB_FS_PE_i(9) <= '1';
+ HUB_FS_PE_i(8) <= hub_data(data_counter);
+ end loop;
+ wait for 30 ns;
+ HUB_FS_PE_i(9) <= '0';
+ HUB_FS_PE_i(8) <= '0';
+ wait for 100 ns;
+ HUB_FS_PE_i(9) <= '1';
+ wait for 100 ns;
+ HUB_FS_PE_i(9) <= '0';
+ wait;
+ end process hub_etrax_int_test;
+
+-------------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------
+-- cts
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+ ext_trigger: process
+ begin
+ wait for 3 ns;
+ loop
+ CTS_VIR_TRIG_i <= '1';
+ CTS_VIR_TRIGB_i <= '0';
+ wait for 10 ns;
+ CTS_VIR_TRIG_i <= '0';
+ CTS_VIR_TRIGB_i <= '1';
+ wait for 10 ns;
+ end loop;
+ end process;
+-- CTS_VIR_TRIG_i <= '0';
+-- CTS_VIR_TRIGB_i <= '1';
+ CTS_INST: trb_v2b_fpga_cts
+-- generic map (
+-- RW_SYSTEM => RW_SYSTEM,
+-- TRBV2_TYPE => TRBV2_TYPE,
+-- TRBNET_ENABLE => TRBNET_ENABLE,
+-- DTU_ENABLE => DTU_ENABLE,
+-- CTU_ENABLE => CTU_ENABLE,
+-- HADES_OLD_BUS_ENABLE => HADES_OLD_BUS_ENABLE,
+-- DSP_INT_ENABLE => DSP_INT_ENABLE,
+-- SDRAM_INT_ENABLE => SDRAM_INT_ENABLE,
+-- SCALERS_ENABLE => SCALERS_ENABLE)
+ port map (
+ VIRT_CLK => VIRT_CLK_i,
+ VIRT_CLKB => VIRT_CLKB_i,
+ RESET_VIRT => CTS_RESET_VIRT_i,
+ DBAD => CTS_DBAD_i,
+ DGOOD => CTS_DGOOD_i,
+ DINT => CTS_DINT_i,
+ DWAIT => CTS_DWAIT_i,
+ A_RESERVED => CTS_A_RESERVED_i,
+ A_TEMP => CTS_A_TEMP_i,
+ B_RESERVED => CTS_B_RESERVED_i,
+ B_TEMP => CTS_B_TEMP_i,
+ C_RESERVED => CTS_C_RESERVED_i,
+ C_TEMP => CTS_C_TEMP_i,
+ D_RESERVED => CTS_D_RESERVED_i,
+ D_TEMP => CTS_D_TEMP_i,
+ VIR_TRIG => CTS_VIR_TRIG_i,
+ VIR_TRIGB => CTS_VIR_TRIGB_i,
+ A_TDC_ERROR => CTS_A_TDC_ERROR_i,
+ B_TDC_ERROR => CTS_B_TDC_ERROR_i,
+ C_TDC_ERROR => CTS_C_TDC_ERROR_i,
+ D_TDC_ERROR => CTS_D_TDC_ERROR_i,
+ A_TDC_POWERUP => CTS_A_TDC_POWERUP_i,
+ B_TDC_POWERUP => CTS_B_TDC_POWERUP_i,
+ C_TDC_POWERUP => CTS_C_TDC_POWERUP_i,
+ D_TDC_POWERUP => CTS_D_TDC_POWERUP_i,
+ TOKEN_IN => CTS_TOKEN_IN_i,
+ TOKEN_OUT => CTS_TOKEN_OUT_i,
+ C_TOKEN_OUT_TTL => CTS_C_TOKEN_OUT_TTL_i,
+ GET_DATA => CTS_GET_DATA_i,
+ A_DATA_READY => CTS_A_DATA_READY_i,
+ B_DATA_READY => CTS_B_DATA_READY_i,
+ C_DATA_READY => CTS_C_DATA_READY_i,
+ D_DATA_READY => CTS_D_DATA_READY_i,
+ REF_TDC_CLK => CTS_REF_TDC_CLK_i,
+ REF_TDC_CLKB => CTS_REF_TDC_CLKB_i,
+ A_TDC_BU_RESET => CTS_A_TDC_BU_RESET_i,
+ A_TDC_BU_RESETB => CTS_A_TDC_BU_RESETB_i,
+ A_TDC_EV_RESET => CTS_A_TDC_EV_RESET_i,
+ A_TDC_EV_RESETB => CTS_A_TDC_EV_RESETB_i,
+ B_TDC_BU_RESET => CTS_B_TDC_BU_RESET_i,
+ B_TDC_BU_RESETB => CTS_B_TDC_BU_RESETB_i,
+ B_TDC_EV_RESET => CTS_B_TDC_EV_RESET_i,
+ B_TDC_EV_RESETB => CTS_B_TDC_EV_RESETB_i,
+ C_TDC_BU_RESET => CTS_C_TDC_BU_RESET_i,
+ C_TDC_BU_RESETB => CTS_C_TDC_BU_RESETB_i,
+ C_TDC_EV_RESET => CTS_C_TDC_EV_RESET_i,
+ C_TDC_EV_RESETB => CTS_C_TDC_EV_RESETB_i,
+ D_TDC_BU_RESET => CTS_D_TDC_BU_RESET_i,
+ D_TDC_BU_RESETB => CTS_D_TDC_BU_RESETB_i,
+ D_TDC_EV_RESET => CTS_D_TDC_EV_RESET_i,
+ D_TDC_EV_RESETB => CTS_D_TDC_EV_RESETB_i,
+ TDC_OUT => CTS_TDC_OUT_i,
+ TDC_RESET => CTS_TDC_RESET_i,
+ A_TRIGGER => CTS_A_TRIGGER_i,
+ A_TRIGGERB => CTS_A_TRIGGERB_i,
+ B_TRIGGER => CTS_B_TRIGGER_i,
+ B_TRIGGERB => CTS_B_TRIGGERB_i,
+ C_TRIGGER => CTS_C_TRIGGER_i,
+ C_TRIGGERB => CTS_C_TRIGGERB_i,
+ D_TRIGGER => CTS_D_TRIGGER_i,
+ D_TRIGGERB => CTS_D_TRIGGERB_i,
+ FS_PB => CTS_FS_PB_i,
+ FS_PB_17 => CTS_FS_PB_17_i,
+ FS_PC => CTS_FS_PC_i,
+ ETRAX_IRQ => CTS_ETRAX_IRQ_i,
+ A_SCK => CTS_A_SCK_i,
+ A_SCKB => CTS_A_SCKB_i,
+ A_SDI => CTS_A_SDI_i,
+ A_SDIB => CTS_A_SDIB_i,
+ A_SDO => CTS_A_SDO_i,
+ A_SDOB => CTS_A_SDOB_i,
+ A_CSB => CTS_A_CSB_i,
+ A_CS => CTS_A_CS_i,
+ B_SCK => CTS_B_SCK_i,
+ B_SCKB => CTS_B_SCKB_i,
+ B_SDI => CTS_B_SDI_i,
+ B_SDIB => CTS_B_SDIB_i,
+ B_SDO => CTS_B_SDO_i,
+ B_SDOB => CTS_B_SDOB_i,
+ B_CSB => CTS_B_CSB_i,
+ B_CS => CTS_B_CS_i,
+ C_SCK => CTS_C_SCK_i,
+ C_SCKB => CTS_C_SCKB_i,
+ C_SDI => CTS_C_SDI_i,
+ C_SDIB => CTS_C_SDIB_i,
+ C_SDO => CTS_C_SDO_i,
+ C_SDOB => CTS_C_SDOB_i,
+ C_CSB => CTS_C_CSB_i,
+ C_CS => CTS_C_CS_i,
+ D_SCK => CTS_D_SCK_i,
+ D_SCKB => CTS_D_SCKB_i,
+ D_SDI => CTS_D_SDI_i,
+ D_SDIB => CTS_D_SDIB_i,
+ D_SDO => CTS_D_SDO_i,
+ D_SDOB => CTS_D_SDOB_i,
+ D_CSB => CTS_D_CSB_i,
+ D_CS => CTS_D_CS_i,
+ A_TEST1 => CTS_A_TEST1_i,
+ A_TEST1B => CTS_A_TEST1B_i,
+ A_TEST2 => CTS_A_TEST2_i,
+ A_TEST2B => CTS_A_TEST2B_i,
+ B_TEST1 => CTS_B_TEST1_i,
+ B_TEST1B => CTS_B_TEST1B_i,
+ B_TEST2 => CTS_B_TEST2_i,
+ B_TEST2B => CTS_B_TEST2B_i,
+ C_TEST1 => CTS_C_TEST1_i,
+ C_TEST1B => CTS_C_TEST1B_i,
+ C_TEST2 => CTS_C_TEST2_i,
+ C_TEST2B => CTS_C_TEST2B_i,
+ D_TEST1 => CTS_D_TEST1_i,
+ D_TEST1B => CTS_D_TEST1B_i,
+ D_TEST2 => CTS_D_TEST2_i,
+ D_TEST2B => CTS_D_TEST2B_i,
+ DSPADDR => CTS_DSPADDR_i,
+ DSPDAT => CTS_DSPDAT_i,
+ DSP_ACK => CTS_DSP_ACK_i,
+ DSP_BM => CTS_DSP_BM_i,
+ DSP_BMS => CTS_DSP_BMS_i,
+ DSP_BOFF => CTS_DSP_BOFF_i,
+ DSP_BRST => CTS_DSP_BRST_i,
+ DSP_HBG => CTS_DSP_HBG_i,
+ DSP_HBR => CTS_DSP_HBR_i,
+ DSP_IRQ => CTS_DSP_IRQ_i,
+ DSP_RD => CTS_DSP_RD_i,
+ DSP_RESET => CTS_DSP_RESET_i,
+ DSP_RESET_OUT => CTS_DSP_RESET_OUT_i,
+ DSP_WRH => CTS_DSP_WRH_i,
+ DSP_WRL => CTS_DSP_WRL_i,
+ VSD_A => CTS_VSD_A_i,
+ VSD_BA => CTS_VSD_BA_i,
+ VSD_CAS => CTS_VSD_CAS_i,
+ VSD_CKE => CTS_VSD_CKE_i,
+ VSD_CLOCK => CTS_VSD_CLOCK_i,
+ VSD_CSEH => CTS_VSD_CSEH_i,
+ VSD_CSEL => CTS_VSD_CSEL_i,
+ VSD_D => CTS_VSD_D_i,
+ VSD_DQML => CTS_VSD_DQML_i,
+ VSD_RAS => CTS_VSD_RAS_i,
+ VSD_WE => CTS_VSD_WE_i,
+ TLK_CLK => TLK_CLK_i,
+ TLK_ENABLE => CTS_TLK_ENABLE_i,
+ TLK_LCKREFN => CTS_TLK_LCKREFN_i,
+ TLK_LOOPEN => CTS_TLK_LOOPEN_i,
+ TLK_PRBSEN => CTS_TLK_PRBSEN_i,
+ TLK_RXD => OPT_DATA_OUT_i(15 downto 0),
+ TLK_RX_CLK => TLK_RX_CLK_i,
+ TLK_RX_DV => OPT_DATA_VALID_OUT_i(0),
+ TLK_RX_ER => CTS_TLK_RX_ER_i,
+ TLK_TXD => OPT_DATA_IN_i(15 downto 0),
+ TLK_TX_EN => OPT_DATA_VALID_IN_i(0),
+ TLK_TX_ER => CTS_TLK_TX_ER_i,
+ SFP_LOS => CTS_SFP_LOS_i,
+ SFP_TX_DIS => CTS_SFP_TX_DIS_i,
+ SFP_TX_FAULT => CTS_SFP_TX_FAULT_i,
+ ADDON_TO_TRB_CLKINN => CTS_ADDON_TO_TRB_CLKINN_i,
+ ADDON_TO_TRB_CLKINP => CTS_ADDON_TO_TRB_CLKINP_i,
+ ADO_LV => CTS_ADO_LV_i,
+ ADO_TTL => CTS_ADO_TTL_i,
+ VIRT_TCK => CTS_VIRT_TCK_i,
+ VIRT_TDI => CTS_VIRT_TDI_i,
+ VIRT_TDO => CTS_VIRT_TDO_i,
+ VIRT_TMS => CTS_VIRT_TMS_i,
+ VIRT_TRST => CTS_VIRT_TRST_i);
+
+
+
+ -----------------------------------------------------------------------------
+ -- clocks
+ -----------------------------------------------------------------------------
+ clock_tlk_clk : process
+ begin
+ wait for 7 ns;
+ loop
+ TLK_CLK_i <= '0';
+ wait for 5 ns;
+ TLK_CLK_i <= '1';
+ wait for 5 ns;
+ end loop;
+ end process;
+ clock_tlk_rx_clk : process
+ begin
+ wait for 3 ns;
+ loop
+ TLK_RX_CLK_i <= '0';
+ wait for 5 ns;
+ TLK_RX_CLK_i <= '1';
+ wait for 5 ns;
+ end loop;
+ end process;
+ clock_gclk : process
+ begin
+ VIRT_CLK_i <= '0';
+ VIRT_CLKB_i <= '1';
+ wait for 5 ns;
+ VIRT_CLK_i <= '1';
+ VIRT_CLKB_i <= '0';
+ wait for 5 ns;
+ end process;
+ clock_hub_clk : process
+ begin
+ LVDS_CLK_200P_i<= '0';
+ wait for 5 ns;
+ LVDS_CLK_200P_i <= '1';
+ wait for 5 ns;
+ end process;
+ clock_tdcclk : process
+ begin
+ wait for 12 ns;
+ loop
+ REF_TDC_CLK_i <= '0';
+ REF_TDC_CLKB_i <= '1';
+ wait for 12.5 ns;
+ REF_TDC_CLK_i <= '1';
+ REF_TDC_CLKB_i <= '0';
+ wait for 12.5 ns;
+ end loop;
+ end process;
+
+ cts_clock_tdcclk : process
+ begin
+ wait for 12 ns;
+ loop
+ CTS_REF_TDC_CLK_i <= '0';
+ CTS_REF_TDC_CLKB_i <= '1';
+ wait for 12.5 ns;
+ CTS_REF_TDC_CLK_i <= '1';
+ CTS_REF_TDC_CLKB_i <= '0';
+ wait for 12.5 ns;
+ end loop;
+ end process;
+ ----------------------------------------------------------------------------
+ -- -------------------------------------------------------------------------
+ -- -------------------------------------------------------------------------
+ -- CTS
+ ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+
+ -----------------------------------------------------------------------------
+ -- vulom to cts
+ -----------------------------------------------------------------------------
+
+
+ CTS_ADO_TTL_i(4) <= 'Z';
+
+ VULOM_SENDS_TRIGGER: process
+ variable i,y : integer;
+ begin
+ vulom_lvl1_tag <= (others => '0');
+ CTS_ADO_TTL_i(46) <= '0';
+ CTS_ADO_TTL_i(42 downto 41) <= "00";
+ wait for 2000 ns;
+
+ loop
+ y := 0;
+ CTS_ADO_TTL_i(42 downto 41) <= "01";
+ CTS_ADO_TTL_i(46) <= '1';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(46) <= '0';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(42 downto 41) <= "10";
+ CTS_ADO_TTL_i(46) <= '1';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(46) <= '0';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(42 downto 41) <= "01";
+ CTS_ADO_TTL_i(46) <= '1';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(46) <= '0';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(42 downto 41) <= "10";
+ CTS_ADO_TTL_i(46) <= '1';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(46) <= '0';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(42 downto 41) <= "00";
+ CTS_ADO_TTL_i(46) <= '0';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(46) <= '0';
+ CTS_ADO_TTL_i(46) <= '1';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(46) <= '0';
+
+
+ wait for 10 ns;
+ for i in 0 to 161 loop
+ CTS_ADO_TTL_i(42 downto 41) <= vulom_lvl1_tag (((y mod 15)+1) downto (y mod 15));
+ CTS_ADO_TTL_i(46) <= '1';
+ wait for 10 ns;
+ CTS_ADO_TTL_i(46) <= '0';
+ wait for 10 ns;
+ y := y + 2;
+ end loop; -- 40ns;
+ wait on VIRT_CLK_i until CTS_ADO_TTL_i(34) = '1';
+ wait on VIRT_CLK_i until CTS_ADO_TTL_i(34) = '0';
+ vulom_lvl1_tag <= vulom_lvl1_tag + 1;
+ end loop;
+ end process VULOM_SENDS_TRIGGER;
+
+ --etrax cts readout --dma
+ ETRAX_BUSY_PROC: process
+ variable etrax_busy_time : integer :=0;
+ begin -- process ETRAX_BUSY
+ CTS_FS_PB_17_i <= '0';
+ wait on VIRT_CLK_i until CTS_FS_PB_i(16) ='1';
+ wait for 20 ns;
+ CTS_FS_PB_17_i <= '1';
+ wait for 80 ns;
+ wait on VIRT_CLK_i until cts_etrax_busy ='0';
+ etrax_busy_time := etrax_busy_time*3/2 +1;
+ end process ETRAX_BUSY_PROC;
+
+ WAIT_FOR_TRANSFER_END: process
+ variable wait_int : integer range 0 to 65535;
+ begin
+ cts_etrax_busy <= '0';
+ wait on VIRT_CLK_i until CTS_FS_PB_i(16) ='1';
+ cts_etrax_busy <= '1';
+ wait for 37*10 ns;
+ end process WAIT_FOR_TRANSFER_END;
+-- write fpga register
+ etrax_int_test: process
+ begin
+ cts_rw_mode <= x"0000";
+ cts_address <= x"00000006";
+ cts_data <= x"00000082";
+ CTS_FS_PC_i(17) <= '0';
+ CTS_FS_PC_i(16) <= '0';
+ wait for 1000 ns;
+ for rw_mode_counter in 0 to 15 loop
+ wait for 100 ns;
+ CTS_FS_PC_i(17) <= '0';
+ CTS_FS_PC_i(16) <= cts_rw_mode(rw_mode_counter);
+ wait for 100 ns;
+ CTS_FS_PC_i(17) <= '1';
+ CTS_FS_PC_i(16) <= cts_rw_mode(rw_mode_counter);
+ end loop;
+ wait for 300 ns;
+ for address_counter in 0 to 31 loop
+ wait for 100 ns;
+ CTS_FS_PC_i(17) <= '0';
+ CTS_FS_PC_i(16) <= cts_address(address_counter);
+ wait for 100 ns;
+ CTS_FS_PC_i(17) <= '1';
+ CTS_FS_PC_i(16) <= cts_address(address_counter);
+ end loop;
+ wait for 300 ns;
+ for data_counter in 0 to 31 loop
+ wait for 100 ns;
+ CTS_FS_PC_i(17) <= '0';
+ CTS_FS_PC_i(16) <= cts_data(data_counter);
+ wait for 100 ns;
+ CTS_FS_PC_i(17) <= '1';
+ CTS_FS_PC_i(16) <= cts_data(data_counter);
+ end loop;
+ wait for 300 ns;
+ CTS_FS_PC_i(17) <= '0';
+ CTS_FS_PC_i(16) <= '0';
+ wait for 400 ns;
+ CTS_FS_PC_i(17) <= '1';
+ wait for 100 ns;
+ CTS_FS_PC_i(17) <= '0';
+ end process etrax_int_test;
+ -------------------------------------------------------------------------------
+ -- cts to hub
+ -------------------------------------------------------------------------------
+
+
+-------------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------
+-- trb
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+ VIR_TRIG_i <= CTS_ADO_TTL_i(7);
+ VIR_TRIGB_i <= not CTS_ADO_TTL_i(7);
+
+ GENERATE_TRBS: for next_trb in 0 to HOW_MANY_ACTIVE_TRBS-1 generate
+
+
+ TRB_INST: trb_v2b_fpga
+-- generic map(
+-- RW_SYSTEM <= 1; --1 -trb, 2 -addon with portE 10 9 as rw
+-- TRBV2_TYPE <= 0;
+-- -- 0 - trbv2 + RPC or TOF or FWALL or Start or Veto,
+-- -- 1 - MDC,
+-- -- 2 - SHOWER,
+-- -- 3 - RICH
+-- -- 4 - CTS
+-- TRBNET_ENABLE <= 0; -- 0 - disable,
+-- -- 1 - enable
+-- DTU_ENABLE <= 0; -- 0 - disable, 1 - old
+-- -- HADES bus, 2 - opt
+-- -- without trbnet
+-- CTU_ENABLE <= 0;
+-- HADES_OLD_BUS_ENABLE <= 0;
+-- DSP_INT_ENABLE <= 0; -- dsp interface enable
+-- SDRAM_INT_ENABLE <= 0; -- sdram interface enable
+-- SCALERS_ENABLE <= 0
+-- );
+ port map (
+ VIRT_CLK => VIRT_CLK_i,
+ VIRT_CLKB => VIRT_CLKB_i,
+ RESET_VIRT => RESET_VIRT_i,
+ DBAD => DBAD_i,
+ DGOOD => DGOOD_i,
+ DINT => DINT_i,
+ DWAIT => DWAIT_i,
+ A_RESERVED => A_RESERVED_i,
+ A_TEMP => A_TEMP_i,
+ B_RESERVED => B_RESERVED_i,
+ B_TEMP => B_TEMP_i,
+ C_RESERVED => C_RESERVED_i,
+ C_TEMP => C_TEMP_i,
+ D_RESERVED => D_RESERVED_i,
+ D_TEMP => D_TEMP_i,
+ VIR_TRIG => VIR_TRIG_i,
+ VIR_TRIGB => VIR_TRIGB_i,
+ A_TDC_ERROR => A_TDC_ERROR_i,
+ B_TDC_ERROR => B_TDC_ERROR_i,
+ C_TDC_ERROR => C_TDC_ERROR_i,
+ D_TDC_ERROR => D_TDC_ERROR_i,
+ A_TDC_POWERUP => A_TDC_POWERUP_i,
+ B_TDC_POWERUP => B_TDC_POWERUP_i,
+ C_TDC_POWERUP => C_TDC_POWERUP_i,
+ D_TDC_POWERUP => D_TDC_POWERUP_i,
+ TOKEN_IN => TOKEN_IN_i(next_trb),
+ TOKEN_OUT => TOKEN_OUT_i(next_trb),
+ C_TOKEN_OUT_TTL => C_TOKEN_OUT_TTL_i,
+ GET_DATA => GET_DATA_i,
+ A_DATA_READY => A_DATA_READY_i(next_trb),
+ B_DATA_READY => B_DATA_READY_i(next_trb),
+ C_DATA_READY => C_DATA_READY_i(next_trb),
+ D_DATA_READY => D_DATA_READY_i(next_trb),
+ REF_TDC_CLK => REF_TDC_CLK_i,
+ REF_TDC_CLKB => REF_TDC_CLKB_i,
+ A_TDC_BU_RESET => A_TDC_BU_RESET_i,
+ A_TDC_BU_RESETB => A_TDC_BU_RESETB_i,
+ A_TDC_EV_RESET => A_TDC_EV_RESET_i,
+ A_TDC_EV_RESETB => A_TDC_EV_RESETB_i,
+ B_TDC_BU_RESET => B_TDC_BU_RESET_i,
+ B_TDC_BU_RESETB => B_TDC_BU_RESETB_i,
+ B_TDC_EV_RESET => B_TDC_EV_RESET_i,
+ B_TDC_EV_RESETB => B_TDC_EV_RESETB_i,
+ C_TDC_BU_RESET => C_TDC_BU_RESET_i,
+ C_TDC_BU_RESETB => C_TDC_BU_RESETB_i,
+ C_TDC_EV_RESET => C_TDC_EV_RESET_i,
+ C_TDC_EV_RESETB => C_TDC_EV_RESETB_i,
+ D_TDC_BU_RESET => D_TDC_BU_RESET_i,
+ D_TDC_BU_RESETB => D_TDC_BU_RESETB_i,
+ D_TDC_EV_RESET => D_TDC_EV_RESET_i,
+ D_TDC_EV_RESETB => D_TDC_EV_RESETB_i,
+ TDC_OUT => TDC_OUT_i((next_trb+1)*32-1 downto next_trb*32),
+ TDC_RESET => TDC_RESET_i,
+ A_TRIGGER => A_TRIGGER_i,
+ A_TRIGGERB => A_TRIGGERB_i,
+ B_TRIGGER => B_TRIGGER_i,
+ B_TRIGGERB => B_TRIGGERB_i,
+ C_TRIGGER => C_TRIGGER_i,
+ C_TRIGGERB => C_TRIGGERB_i,
+ D_TRIGGER => D_TRIGGER_i,
+ D_TRIGGERB => D_TRIGGERB_i,
+ FS_PB => FS_PB_i((next_trb+1)*17-1 downto next_trb*17),
+ FS_PB_17 => FS_PB_17_i(next_trb),
+ FS_PC => FS_PC_i((next_trb+1)*18-1 downto next_trb*18),
+ ETRAX_IRQ => ETRAX_IRQ_i,
+ A_SCK => A_SCK_i,
+ A_SCKB => A_SCKB_i,
+ A_SDI => A_SDI_i,
+ A_SDIB => A_SDIB_i,
+ A_SDO => A_SDO_i,
+ A_SDOB => A_SDOB_i,
+ A_CSB => A_CSB_i,
+ A_CS => A_CS_i,
+ B_SCK => B_SCK_i,
+ B_SCKB => B_SCKB_i,
+ B_SDI => B_SDI_i,
+ B_SDIB => B_SDIB_i,
+ B_SDO => B_SDO_i,
+ B_SDOB => B_SDOB_i,
+ B_CSB => B_CSB_i,
+ B_CS => B_CS_i,
+ C_SCK => C_SCK_i,
+ C_SCKB => C_SCKB_i,
+ C_SDI => C_SDI_i,
+ C_SDIB => C_SDIB_i,
+ C_SDO => C_SDO_i,
+ C_SDOB => C_SDOB_i,
+ C_CSB => C_CSB_i,
+ C_CS => C_CS_i,
+ D_SCK => D_SCK_i,
+ D_SCKB => D_SCKB_i,
+ D_SDI => D_SDI_i,
+ D_SDIB => D_SDIB_i,
+ D_SDO => D_SDO_i,
+ D_SDOB => D_SDOB_i,
+ D_CSB => D_CSB_i,
+ D_CS => D_CS_i,
+ A_TEST1 => A_TEST1_i,
+ A_TEST1B => A_TEST1B_i,
+ A_TEST2 => A_TEST2_i,
+ A_TEST2B => A_TEST2B_i,
+ B_TEST1 => B_TEST1_i,
+ B_TEST1B => B_TEST1B_i,
+ B_TEST2 => B_TEST2_i,
+ B_TEST2B => B_TEST2B_i,
+ C_TEST1 => C_TEST1_i,
+ C_TEST1B => C_TEST1B_i,
+ C_TEST2 => C_TEST2_i,
+ C_TEST2B => C_TEST2B_i,
+ D_TEST1 => D_TEST1_i,
+ D_TEST1B => D_TEST1B_i,
+ D_TEST2 => D_TEST2_i,
+ D_TEST2B => D_TEST2B_i,
+ DSPADDR => DSPADDR_i,
+ DSPDAT => DSPDAT_i,
+ DSP_ACK => DSP_ACK_i,
+ DSP_BM => DSP_BM_i,
+ DSP_BMS => DSP_BMS_i,
+ DSP_BOFF => DSP_BOFF_i,
+ DSP_BRST => DSP_BRST_i,
+ DSP_HBG => DSP_HBG_i,
+ DSP_HBR => DSP_HBR_i,
+ DSP_IRQ => DSP_IRQ_i,
+ DSP_RD => DSP_RD_i,
+ DSP_RESET => DSP_RESET_i,
+ DSP_RESET_OUT => DSP_RESET_OUT_i,
+ DSP_WRH => DSP_WRH_i,
+ DSP_WRL => DSP_WRL_i,
+ VSD_A => VSD_A_i,
+ VSD_BA => VSD_BA_i,
+ VSD_CAS => VSD_CAS_i,
+ VSD_CKE => VSD_CKE_i,
+ VSD_CLOCK => VSD_CLOCK_i,
+ VSD_CSEH => VSD_CSEH_i,
+ VSD_CSEL => VSD_CSEL_i,
+ VSD_D => VSD_D_i,
+ VSD_DQML => VSD_DQML_i,
+ VSD_RAS => VSD_RAS_i,
+ VSD_WE => VSD_WE_i,
+ TLK_CLK => TLK_CLK_i,
+ TLK_ENABLE => TLK_ENABLE_i,
+ TLK_LCKREFN => TLK_LCKREFN_i,
+ TLK_LOOPEN => TLK_LOOPEN_i,
+ TLK_PRBSEN => TLK_PRBSEN_i,
+ TLK_RXD => OPT_DATA_OUT_i((next_trb+2)*16-1 downto (next_trb+1)*16),
+ TLK_RX_CLK => TLK_RX_CLK_i,
+ TLK_RX_DV => OPT_DATA_VALID_OUT_i(next_trb+1),
+ TLK_RX_ER => TLK_RX_ER_i,
+ TLK_TXD => OPT_DATA_IN_i((next_trb+2)*16-1 downto (next_trb+1)*16),
+ TLK_TX_EN => OPT_DATA_VALID_IN_i(next_trb+1),
+ TLK_TX_ER => TLK_TX_ER_i,
+ SFP_LOS => SFP_LOS_i,
+ SFP_TX_DIS => SFP_TX_DIS_i,
+ SFP_TX_FAULT => SFP_TX_FAULT_i,
+ ADDON_TO_TRB_CLKINN => ADDON_TO_TRB_CLKINN_i,
+ ADDON_TO_TRB_CLKINP => ADDON_TO_TRB_CLKINP_i,
+ ADO_LV => ADO_LV_i,
+ ADO_TTL => ADO_TTL_i,
+ VIRT_TCK => VIRT_TCK_i,
+ VIRT_TDI => VIRT_TDI_i,
+ VIRT_TDO => VIRT_TDO_i,
+ VIRT_TMS => VIRT_TMS_i,
+ VIRT_TRST => VIRT_TRST_i);
+
+
+ TDC_OUT_i((next_trb+1)*32-1 downto next_trb*32) <= tdc_data_i;--x"00000000";--tdc_data_i;
+
+ TDC_DATA_CHANGE: process(REF_TDC_CLKB_i, RESET_VIRT_i)
+ begin
+ if rising_edge(REF_TDC_CLKB_i) then
+ if RESET_VIRT_i = '1' then
+ tdc_data_i <= x"00000000";
+ else
+ tdc_data_i <= tdc_data_i + 1;
+ end if;
+ end if;
+ end process TDC_DATA_CHANGE;
+
+ trigger_lvl1 : process
+ variable valid_time : integer :=0;
+ begin
+ A_DATA_READY_i(next_trb) <= '0';
+ B_DATA_READY_i(next_trb) <= '0';
+ C_DATA_READY_i(next_trb) <= '0';
+ D_DATA_READY_i(next_trb) <= '0';
+ TOKEN_IN_i(next_trb) <= '0';
+ wait on REF_TDC_CLK_i until TOKEN_OUT_i(next_trb) = '1';
+ wait on REF_TDC_CLK_i until TOKEN_OUT_i(next_trb) = '0';
+ wait for 10 ns;
+ A_DATA_READY_i(next_trb) <= '1';
+ wait for ((valid_time mod 2)*50*3+2*25)*ns;
+ A_DATA_READY_i(next_trb) <= '0';
+ B_DATA_READY_i(next_trb) <= '1';
+ wait for ((valid_time mod 3 )*50*2+2*25)*ns;
+ B_DATA_READY_i(next_trb) <= '0';
+ C_DATA_READY_i(next_trb) <= '1';
+ wait for ((valid_time mod 5 )*50+2*25+next_trb*25)*ns;
+ C_DATA_READY_i(next_trb) <= '0';
+ D_DATA_READY_i(next_trb) <= '1';
+ wait for ((valid_time mod 7 )*50+2*25+next_trb*25)*ns;
+ D_DATA_READY_i(next_trb) <= '0';
+ wait for 0 ns;
+ TOKEN_IN_i(next_trb) <= '1';
+ wait for 25 ns;
+ TOKEN_IN_i(next_trb) <= '0';
+
+ valid_time := valid_time*3/2 +1;
+ end process;
+ ETRAX_BUSY_PROC_TRB: process
+ variable etrax_busy_time : integer :=0;
+ begin -- process ETRAX_BUSY
+ FS_PB_17_i(next_trb) <= '0';
+ wait on VIRT_CLKB_i until FS_PB_i(16+(next_trb*17)) ='1';
+ wait for 20 ns;
+ FS_PB_17_i(next_trb) <= '1';
+ wait for 80 ns;
+ wait on VIRT_CLK_i until etrax_busy(next_trb) ='0';
+
+
+ etrax_busy_time := etrax_busy_time*3/2 +1;
+ end process ETRAX_BUSY_PROC_TRB;
+
+ WAIT_FOR_TRANSFER_END_TRB: process
+ variable wait_int : integer range 0 to 65535;
+ begin
+ etrax_busy(next_trb) <= '0';
+ wait on VIRT_CLK_i until FS_PB_i(16+(next_trb*17)) ='1';
+ etrax_busy(next_trb) <= '1';
+ wait for 37*10 ns;
+ end process WAIT_FOR_TRANSFER_END_TRB;
+ end generate GENERATE_TRBS;
+
+
+
+-------------------------------------------------------------------------------
+-- DTU only lvl2
+------------------------------------------------------------------------------
+-- clock_dtu : process
+-- begin
+-- wait for 34 ns;
+-- loop
+-- dtu_clk <= '0';
+-- wait for 50 ns;
+-- dtu_clk <= '1';
+-- wait for 50 ns;
+-- end loop;
+-- end process;
+-- ADO_TTL_i(34) <= 'Z';
+-- ADO_TTL_i(7) <= 'Z';
+-- LVL2_COUNT : process
+-- begin
+-- wait for 100 ns;
+-- dtu_lvl2_tag <= x"00";
+-- wait on dtu_clk until ADO_TTL_i(8) = '0';
+-- loop
+-- wait on dtu_clk until lvl2_trig = '1';
+-- wait for 500 ns;
+-- dtu_lvl2_tag <= dtu_lvl2_tag +1;
+-- wait on dtu_clk until ADO_TTL_i(8) = '0';
+-- end loop;
+-- end process LVL2_COUNT;
+-- -- ADO_TTL_i(9) <= lvl2_trig;
+-- DTU_EMULATION_LVL2 : process
+-- begin
+-- ADO_TTL_i(9) <= '0';
+-- ADO_TTL_i(13 downto 10) <= x"1";
+-- lvl2_trig <= '0';
+-- wait for 4000 ns;
+-- loop
+-- for number_of_normal_triggers in 0 to 9 loop
+-- ADO_TTL_i(9) <= '0';
+-- wait on VIRT_CLK_i until ADO_TTL_i(7) = '1'; --after lvl1
+-- -- -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1;
+-- -- wait on VIRT_CLK_i until ADO_TTL_i(7) = '0'; --after lvl1
+-- wait for 3000 ns;
+-- wait on VIRT_CLK_i until ADO_TTL_i(15) = '0';
+-- -- wait for 6000 ns;
+-- ADO_TTL_i(13 downto 10) <= x"1";
+-- ADO_TTL_i(8) <= '1';
+-- wait for 100 ns;
+-- ADO_TTL_i(8) <= '0';
+-- ADO_TTL_i(13 downto 10) <= dtu_lvl2_tag(3 downto 0);
+-- lvl2_trig <= '1';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '1';
+-- lvl2_trig <= '0';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '0';
+-- ADO_TTL_i(13 downto 10) <= dtu_lvl2_tag(7 downto 4);
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '1';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '0';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '1';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '0';
+-- end loop; -- number_of_normal_triggers
+-- ADO_TTL_i(9) <= '0';
+-- wait on VIRT_CLK_i until ADO_TTL_i(7) = '1'; --after lvl1
+-- -- -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1;
+-- -- wait on VIRT_CLK_i until ADO_TTL_i(7) = '0'; --after lvl1
+-- wait for 3000 ns;
+-- wait on VIRT_CLK_i until ADO_TTL_i(15) = '0';
+-- -- wait for 6000 ns;
+-- ADO_TTL_i(13 downto 10) <= x"9";
+-- ADO_TTL_i(8) <= '1';
+-- wait for 100 ns;
+-- ADO_TTL_i(8) <= '0';
+-- lvl2_trig <= '1';
+-- ADO_TTL_i(13 downto 10) <= dtu_lvl2_tag(3 downto 0);
+-- wait for 100 ns;
+-- lvl2_trig <= '0';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '1';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '0';
+-- ADO_TTL_i(13 downto 10) <= dtu_lvl2_tag(7 downto 4);
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '1';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '0';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '1';
+-- wait for 100 ns;
+-- ADO_TTL_i(9) <= '0';
+-- end loop;
+-- end process DTU_EMULATION_LVL2;
+
+-- -----------------------------------------------------------------------------
+-- -- etrax trb_0
+-- -----------------------------------------------------------------------------
+-- ETRAX_BUSY_0: process
+-- variable etrax_busy_time : integer :=0;
+-- begin -- process ETRAX_BUSY
+-- FS_PB_0(17) <= '0';
+-- wait on VIRT_CLK_i until FS_PB_0(16) ='1';
+-- wait for 30 ns;
+-- FS_PB_0(17) <= '1';
+-- wait for 80 ns;
+-- wait for ((etrax_busy_time mod 7 )*5+20)*ns;
+-- etrax_busy_time := etrax_busy_time*3/2 +1;
+-- end process ETRAX_BUSY_0;
+-- -----------------------------------------------------------------------------
+-- -- etrax trb_1
+-- -----------------------------------------------------------------------------
+-- ETRAX_BUSY_1: process
+-- variable etrax_busy_time : integer :=0;
+-- begin -- process ETRAX_BUSY
+-- FS_PB_1(17) <= '0';
+-- wait on VIRT_CLK_i until FS_PB_1(16) ='1';
+-- wait for 30 ns;
+-- FS_PB_1(17) <= '1';
+-- wait for 80 ns;
+-- wait for ((etrax_busy_time mod 9 )*5+20)*ns;
+-- etrax_busy_time := etrax_busy_time*3/2 +1;
+-- end process ETRAX_BUSY_1;
+-- -- etrax_intf_trb0 : PROCESS
+-- -- BEGIN
+-- -- loop
+-- -- wait on VIRT_CLK_i until FS_PB_0(16) = '1';
+-- -- wait for 50 ns;
+-- -- FS_PB_0(17) <= '1';
+-- -- wait for 50 ns;
+-- -- FS_PB_0(17) <= '0';
+-- -- wait for 50 ns;
+-- -- end loop;
+-- -- wait; -- will wait forever
+-- -- end process;
+-- -----------------------------------------------------------------------------
+-- -- etrax cts
+-- -----------------------------------------------------------------------------
+-- etrax_intf_cts : PROCESS
+-- BEGIN
+-- loop
+-- wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '1';
+-- wait for 50 ns;
+-- FS_PB_CTS_i(17) <= '1';
+-- wait for 50 ns;
+-- FS_PB_CTS_i(17) <= '0';
+-- wait for 50 ns;
+-- end loop;
+-- wait; -- will wait forever
+-- end process;
+-- -----------------------------------------------------------------------
+-- -- TDC_trb_0
+-- -----------------------------------------------------------------------
+-- TDC_OUT_0 <= tdc_data_i;--x"00000000";--tdc_data_i;
+
+-- TDC_DATA_CHANGE_0: process(REF_TDC_CLK_i, RESET_VIRT_0)
+-- begin
+-- if rising_edge(REF_TDC_CLK_i) then
+-- if RESET_VIRT_0 = '1' then
+-- tdc_data_i <= x"00000000";
+-- else
+-- tdc_data_i <= tdc_data_i + 1;
+-- end if;
+-- end if;
+-- end process TDC_DATA_CHANGE_0;
+
+
+-- trigger_lvl1_0 : process
+-- variable valid_time : integer :=0;
+-- begin
+-- -- ADO_TTL(7) <= '0';
+-- A_DATA_READY_0 <= '0';
+-- B_DATA_READY_0 <= '0';
+-- C_DATA_READY_0 <= '0';
+-- D_DATA_READY_0 <= '0';
+-- TOKEN_IN_0 <= '0';
+-- -- A_TEMP <= '0';
+-- -- wait for 50 ns;
+-- -- A_TEMP <= '1';
+-- -- wait for 10 ns;
+-- -- A_TEMP <= '0';
+-- -- wait for 10 ns;
+-- wait on REF_TDC_CLK_i until TOKEN_OUT_0 = '1';
+-- wait on REF_TDC_CLK_i until TOKEN_OUT_0 = '0';
+-- wait for 10 ns;
+-- -- ADO_TTL(7) <= '0';
+-- A_DATA_READY_0 <= '1';
+-- -- wait for 50 ns;
+-- wait for ((valid_time mod 3)*50*3+2*25)*ns;
+-- A_DATA_READY_0 <= '0';
+-- B_DATA_READY_0 <= '1';
+-- -- wait for 50 ns;
+-- wait for ((valid_time mod 5 )*50*2+2*25)*ns;
+-- B_DATA_READY_0 <= '0';
+-- C_DATA_READY_0 <= '1';
+-- -- wait for 50 ns;
+-- wait for ((valid_time mod 7 )*50+2*25)*ns;
+-- -- ADO_TTL(7) <= '0';
+-- C_DATA_READY_0 <= '0';
+-- D_DATA_READY_0 <= '1';
+-- --wait for 50 ns;
+-- wait for ((valid_time mod 9 )*50+2*25)*ns;
+-- D_DATA_READY_0 <= '0';
+-- wait for 0 ns;
+-- -- ADO_TTL(6) <= '1';
+-- TOKEN_IN_0 <= '1';
+-- wait for 25 ns;
+-- -- ADO_TTL(6) <= '0';
+-- TOKEN_IN_0 <= '0';
+-- -- wait on REF_TDC_CLK until DBAD = '0';
+-- valid_time := valid_time*3/2 +1;
+-- end process;
+-- -----------------------------------------------------------------------
+-- -- TDC_trb_1
+-- -----------------------------------------------------------------------
+-- TDC_OUT_1 <= tdc_data_i;--x"00000000";--tdc_data_i;
+
+-- -- TDC_DATA_CHANGE: process(REF_TDC_CLK_i, RESET_VIRT_1)
+-- -- begin
+-- -- if rising_edge(REF_TDC_CLK_i) then
+-- -- if RESET_VIRT_1 = '1' then
+-- -- tdc_data_i <= x"00000000";
+-- -- else
+-- -- tdc_data_i <= tdc_data_i + 1;
+-- -- end if;
+-- -- end if;
+-- -- end process TDC_DATA_CHANGE;
+
+
+-- trigger_lvl1_1 : process
+-- variable valid_time : integer :=0;
+-- begin
+-- -- ADO_TTL(7) <= '0';
+-- A_DATA_READY_1 <= '0';
+-- B_DATA_READY_1 <= '0';
+-- C_DATA_READY_1 <= '0';
+-- D_DATA_READY_1 <= '0';
+-- TOKEN_IN_1 <= '0';
+-- -- A_TEMP <= '0';
+-- -- wait for 50 ns;
+-- -- A_TEMP <= '1';
+-- -- wait for 10 ns;
+-- -- A_TEMP <= '0';
+-- -- wait for 10 ns;
+-- wait on REF_TDC_CLK_i until TOKEN_OUT_1 = '1';
+-- wait on REF_TDC_CLK_i until TOKEN_OUT_1 = '0';
+-- wait for 10 ns;
+-- -- ADO_TTL(7) <= '0';
+-- A_DATA_READY_1 <= '1';
+-- -- wait for 50 ns;
+-- wait for ((valid_time mod 11)*50*3+2*25)*ns;
+-- A_DATA_READY_1 <= '0';
+-- B_DATA_READY_1 <= '1';
+-- -- wait for 50 ns;
+-- wait for ((valid_time mod 3 )*50*2+2*25)*ns;
+-- B_DATA_READY_1 <= '0';
+-- C_DATA_READY_1 <= '1';
+-- -- wait for 50 ns;
+-- wait for ((valid_time mod 5 )*50+2*25)*ns;
+-- -- ADO_TTL(7) <= '0';
+-- C_DATA_READY_1 <= '0';
+-- D_DATA_READY_1 <= '1';
+-- --wait for 50 ns;
+-- wait for ((valid_time mod 7 )*50+2*25)*ns;
+-- D_DATA_READY_1 <= '0';
+-- wait for 0 ns;
+-- -- ADO_TTL(6) <= '1';
+-- TOKEN_IN_1 <= '1';
+-- wait for 25 ns;
+-- -- ADO_TTL(6) <= '0';
+-- TOKEN_IN_1 <= '0';
+-- -- wait on REF_TDC_CLK until DBAD = '0';
+-- valid_time := valid_time*3/2 +1;
+-- end process;
+
+
+
+end system;
--- /dev/null
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jspc29 / trbv2.git / commitdiff