CLK : in std_logic;
RESET : in std_logic;
DO_REBOOT : in std_logic;
- PROGRAMN : out std_logic
+ PROGRAMN : out std_logic := '1'
);
end entity;
architecture fpga_reboot_arch of fpga_reboot is
- signal delayed_restart_fpga : std_logic;
+ signal delayed_restart_fpga : std_logic := '0';
signal restart_fpga_counter : unsigned(11 downto 0);
begin
end if;
end process;
-PROGRAMN <= not delayed_restart_fpga when rising_edge(CLK);
+PROGRAMN <= not delayed_restart_fpga;
end architecture;
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