Typos corrected, doubles removed, now loads in ispLever8.1 Windows without spellcheck...

diff --git a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd
index 2e0d642a4627779bb9b14f396c337dd7e16677d2..5e1e546d7c26d0da72b202cab3324015e7d351a4 100755 (executable)
--- a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd
+++ b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd
@@ -54,46 +54,13 @@ architecture med_scm_sfp of trb_net16_med_scm_sfp_gbe is
 -- Placer Directives
 attribute HGROUP : string;
 -- for whole architecture
-attribute HGROUP of med_ecp_sfp : architecture  is "media_interface_group";
+attribute HGROUP of med_scm_sfp : architecture  is "media_interface_group";
 attribute syn_sharing : string;
 attribute syn_sharing of med_scm_sfp : architecture is "off";
 
 -- Components
-entity serdes_gbe_0_200 is
-generic(
-       USER_CONFIG_FILE    :  String := "serdes_gbe_0_200.txt"
-);
-port(
-       refclkp              : in  std_logic; -- external CML reference clock 
-       refclkn              : in  std_logic; -- external CML reference clock
-       rxrefclk             : in  std_logic; -- FPGA fabric receive reference clock
-       refclk               : in  std_logic; -- FPGA fabric transmit reference clock
-       rxa_pclk             : out std_logic; -- selectable recovered receive clock
-       rxb_pclk             : out std_logic; -- selectable recovered receive clock
-       hdinp_0              : in  std_logic; -- external SerDes receiver pin
-       hdinn_0              : in  std_logic; -- external SerDes receiver pin
-       hdoutp_0             : out std_logic; -- external SerDes transmitter pin
-       hdoutn_0             : out std_logic; -- external SerDes transmitter pin
-       tclk_0               : in  std_logic; -- transmit clock for compensation FIFO
-       rclk_0               : in  std_logic; -- receive clock for compensation FIFO
-       tx_rst_0             : in  std_logic; -- async PCS transmit logic reset (active high)
-       rx_rst_0             : in  std_logic; -- async PCS receive logic reset (active high)
-       ref_0_sclk           : out std_logic; -- locked reference clock (per channel) 
-       rx_0_sclk            : out std_logic; -- recovered receive clock (per channel)
-       txd_0                : in  std_logic_vector(15 downto 0); -- transmit data
-       tx_k_0               : in  std_logic_vector(1 downto 0);  -- transmit K
-       tx_force_disp_0      : in  std_logic_vector(1 downto 0);  -- transmit force disparity enable
-       tx_disp_sel_0        : in  std_logic_vector(1 downto 0);  -- transmit disparity select
-       rxd_0                : out std_logic_vector(15 downto 0); -- receive data
-       rx_k_0               : out std_logic_vector(1 downto 0);  -- receive K
-       rx_disp_err_detect_0 : out std_logic_vector(1 downto 0);  -- receive disparity error detect
-       rx_cv_detect_0       : out std_logic_vector(1 downto 0);  -- receive code violation detect
-       quad_rst             : in  std_logic; -- async reset for all SerDes and PCS logic (active high)
-       serdes_rst           : in  std_logic; -- async reset for all SerDes (active high) 
-       ref_pclk             : out std_logic  -- selectable locked reference clock
-);
 
-entity serdes_gbe_0_200 is
+component serdes_gbe_0_200 is
 generic(
        USER_CONFIG_FILE    :  String := "serdes_gbe_0_200.txt"
 );
@@ -134,6 +101,7 @@ port(
        serdes_rst           : in  std_logic;
        ref_pclk             : out std_logic
 );
+end component serdes_gbe_0_200; 
 
 -- LSM state machine signals
 signal swap_bytes             : std_logic; -- sysclk
@@ -339,7 +307,7 @@ port map(
        D_IN(0)  => tx_allow,
        CLK0     => sysclk,
        CLK1     => tx_halfclk,
-       D_OUT(0) => tx_allow_q,
+       D_OUT(0) => tx_allow_q
 );
 
 -- RX_ALLOW signal sync
@@ -350,7 +318,7 @@ port map(
        D_IN(0)  => rx_allow,
        CLK0     => sysclk,
        CLK1     => rx_halfclk,
-       D_OUT(0) => rx_allow_q,
+       D_OUT(0) => rx_allow_q
 );
 
 --------------------------------------------------------------------------
@@ -376,8 +344,8 @@ gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YE
                rxb_pclk             => open,
                hdinp_0              => SD_RXD_P_IN, -- SerDes I/O
                hdinn_0              => SD_RXD_N_IN, -- SerDes I/O
-               hdoutp_0             => SD_TXD_P_IN, -- SerDes I/O
-               hdoutn_0             => SD_TXD_N_IN, -- SerDes I/O
+               hdoutp_0             => SD_TXD_P_OUT, -- SerDes I/O
+               hdoutn_0             => SD_TXD_N_OUT, -- SerDes I/O
                tclk_0               => tx_halfclk, -- 100MHz
                rclk_0               => rx_halfclk, -- 100MHz
                tx_rst_0             => lane_rst, -- async reset
@@ -575,7 +543,7 @@ end process;
 ----------------------
 THE_LED_PROC: process( SYSCLK )
 begin
-       if( rising_edge(SYSCK) ) then
+       if( rising_edge(SYSCLK) ) then
                led_counter <= led_counter + 1;
                
                if   ( buf_med_dataready_out = '1' ) then