\section{Introduction}
The $4+1$ FPGA board ``TRB3'' (\cref{fig:trb3}a) can serve various
-applications in experimental particle physics and beyond due to its
+applications in experimental particle physics (and beyond) due to its
general-purpose design. It uses Lattice ECP3-150EA FPGAs as complex
commercial electronic components while realising the remaining
-auxiliary parts with simple standard components. Moreover, the
-board provides flexible connectivity by eight SFP ports and mezzanine
+auxiliary parts with simple standard components. Moreover, the board
+provides flexible connectivity by eight SFP ports and mezzanine
extensions for every FPGA including a high pin-out for the peripheral
FPGAs. We call this concept COME\&KISS: COMplex COMmercial Elements \&
Keep It Small and Simple. This ensures a wide range of applications in
the measured signals, a \emph{flat} fine-time histogram of all
detected signals is expected. Any deviation must be due to different
propagation delays, thus each element can be calibrated appropriately
-(details see \cite{ugur-twepp2011}). However, if the detector signal
-rate is not sufficient (leading to insufficient statistics in the
-fine-time histogram), artificial hits stemming from an uncorrelated
-signal source must be additionally generated and read-out. This
-technique is already available on the TRB3 and is currently under
-test.
+(for details see \cite{ugur-twepp2011}). However, if the detector
+signal rate is not sufficient (leading to insufficient statistics in
+the fine-time histogram), artificial hits stemming from an
+uncorrelated signal source must be additionally generated and
+read-out. This technique is already available on the TRB3 and is
+currently under test.
Any user can profit from several common software developments for this
platform concerning data acquisition and analysis. The well
established HADES eventbuilder software \cite{michel-twepp2011} can be
-applied to acquire the data delivered by the front-ends and store them
+applied to acquire the data delivered by the front-ends and save them
to HLD formatted files. The stored TDC data stream can be subsequently
analysed offline by a ``standalone'' unpacker code
-\cite{unpacker-web}, just based on the ROOT environment. This includes
-well-tested methods for calibration of the delay lines.
+\cite{unpacker-web}, solely based on the ROOT software package. This
+includes well-tested methods for calibration of the delay lines.
DABC \cite{dabc-pub,dabc-web} and Go4 \cite{go4-web} software provide
an alternative way to readout and analyse data from the TRB3. DABC can
used for live monitoring of DABC and Go4.
Depending of experimental needs, a Go4-based analysis provides
-different methods of TDCs channels calibration. Typically calibration
-is automatically recalculated when specified number of hits
-accumulated in each channel. To achieve a sufficient accuracy, about
-$10^5$-$10^6$ hits should be accumulated in each channel.
+different methods of TDCs channels calibration. Typically, the
+calibration is automatically recalculated when a specified number of
+hits accumulated in each channel. To achieve a sufficient accuracy,
+about $10^5$-$10^6$ hits should be accumulated in each channel.
Alternatively, one can store calibration functions determined by
separate measurements (static approach). Later such calibration files
can be used for any following measurements, which is especially useful
\centering
\begin{minipage}{0.4\linewidth}
\centering
- \includegraphics[width=\textwidth]{gfx/frontends/padiwa_transparent.png}\\
+ \includegraphics[width=\textwidth]{gfx/frontends/padiwa_transparent_scaled.png}\\
(a)
\end{minipage}
\quad
front-end board following the COME\&KISS principle
(\cref{fig:padiwa}). It uses the LVDS input buffers of a Lattice
MachXO2 FPGA to realise a leading edge discriminator for $16$ analogue
-input signals. Besides that, few standard components like the MMIC BGA2802
-($20dB$ wideband amplifiers) and RC low-pass filters are used to generate the
-threshold voltages via PWM. Using test pulses with an amplitude of
-$500$\,$\mu$V and a length of $6$\,ns, a time precision of the full
-system including the TRB3 of $23$\,ps was measured
-\cite{ugur-twepp2012}. This front-end has been successfully used in
-beamtimes, see \cref{sec:juelich,sec:mainz}.
+input signals. Besides that, few standard components like the MMIC
+BGA2802 ($20$\,dB wideband amplifiers) and RC low-pass filters are
+used to generate the threshold voltages via pulse-width modulation.
+Using test pulses with an amplitude of $500$\,$\mu$V and a length of
+$6$\,ns, a time precision of the full system including the TRB3 of
+$23$\,ps was measured \cite{ugur-twepp2012}. This front-end has been
+successfully used in beamtimes, see \cref{sec:juelich,sec:mainz}.
\subsection{Charge-to-width Front-end for HADES ECAL}
\subsection{n-XYTER ASIC for HADES Pion Tracker}
The TRB3 can also be used as an infrastructure to read out specialised
-integrated solutions using the peripheral FPGAs, for example to provide a
-timing reference, transport the acquired data to the eventbuilder and
-configuration of the attached ASIC via slow control. This was realised for the
-n-XYTER ASIC, which provides the digital timestamp and the analogue pulse height of
-self-triggered $128$ channels. In this case, the integration of the read-out
-and slow control (e.\,g. trigger windows) on the peripheral FPGA was easily
-achieved due to the well-documented VHDL interfaces of the TRB3 platform.
-The peripheral FPGA also reads out the ADC for the digitisation of the pulse
-height information.
+integrated solutions using the peripheral FPGAs, for example to
+provide a timing reference, transport the acquired data to the
+eventbuilder and configuration of the attached ASIC via slow control.
+This was realised for the n-XYTER ASIC
+\cite{nxyter-2006,nxyter-twepp2007}, which provides the digital
+timestamp and the analogue pulse height of self-triggered $128$
+channels. In this case, the integration of the read-out and slow
+control (e.\,g. trigger windows) on the peripheral FPGA was easily
+achieved due to the well-documented VHDL interfaces of the TRB3
+platform. The peripheral FPGA also reads out the ADC for the
+digitisation of the pulse height information.
\section{J\"{u}lich Test Beamtime 2012}\label{sec:juelich}
trigger rate of approximately $6$\,kHz. The results show a worse
Cherenkov photon detection for PaDiWa with respect to the NINO ASIC,
as seen in the hit patterns, which is probably caused by differences
-in the amplification stage (the gain of the latter is $100$ times
-larger **Comment Michael**: I think we can not state that, as we don't know
-the internal structure of the NINO and the physical threshold of the NINO
-discriminators. You can say that the gain is more than a factor of 10 higher....).
+in the amplification stage (the gain of the latter is about $10$ times
+larger).
+% **Comment Michael**: I think we can not state that, as we don't know
+%the internal structure of the NINO and the physical threshold of the NINO
+%discriminators. You can say that the gain is more than a factor of 10 higher....).
However, the TRB3 provided a stable platform for a successful
test beamtime.
the PaDiWa thresholds and of the TDC calibration is currently
investigated. There are also several further front-end developments:
Integration of the MuPix ASIC for the PANDA luminosity detector and
-the SPADIC ASIC for a TPC in Mainz. An $\sim$50 channel 10bit 65MSPS ADC AddOn (4
-can be put in one TRB3) is in the layout phase. For the
-PANDA-Straw-Tube-Tracker the development of an ADC inside FPGA is
-followed. Test measurements show that an ADC with 8 bits resolution and
->50MSPS is possible. Since both ASICs use the CBMnet
-protocol, an implementation of CBMnet on the TRB3 was started.
-Furthermore, an extension of TrbNet with defined propagation delays of
-trigger signals for PANDA is being developed and tested.
+the SPADIC ASIC for a TPC in Mainz. A $\sim50$ channel $10$\,bit
+$65$\,MSPS ADC AddOn (4 can be put in one TRB3) is in the layout
+phase. For the PANDA Straw Tube Tracker the development of an ADC
+inside FPGA is followed. Test measurements show that an ADC with
+$8$\,bits resolution and $>50$\,MSPS is possible. Since both ASICs use
+the CBMnet protocol, an implementation of CBMnet on the TRB3 was
+started. Furthermore, an extension of TrbNet with defined propagation
+delays of trigger signals for PANDA is being developed and tested.
The Go4 website,
\href{http://go4.gsi.de}{http://go4.gsi.de}.
+\bibitem{nxyter-2006} A.S. Brogna et al., \emph{N-XYTER, a CMOS read-out
+ ASIC for high resolution time and amplitude measurements on high
+ rate multi-channel counting mode neutron detectors}, Nucl. Instrum.
+ Methods A 568 (2006) 301–308
+
+\bibitem{nxyter-twepp2007} C.J. Schmidt et al., \emph{Test results on
+ the n-XYTER ASIC, a self triggered, sparcifying readout ASIC}
+ TWEPP 2007, Prague,
+ \href{http://indico.cern.ch/contributionDisplay.py?contribId=84&sessionId=11&confId=11994}%
+{http://indico.cern.ch/contributionDisplay.py?contribId=84\&sessionId=11\&confId=11994}.
+
% \bibitem{bib3}
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