*** empty log message ***

diff --git a/trb_net16_endpoint_hades_cts.vhd b/trb_net16_endpoint_hades_cts.vhd
new file mode 100644 (file)
index 0000000..72ef04f
--- /dev/null
+++ b/trb_net16_endpoint_hades_cts.vhd
@@ -0,0 +1,85 @@
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+
+entity trb_net16_endpoint_hades_cts is
+
+  port(
+    CLK       : in  std_logic;
+    RESET     : in  std_logic;
+    CLK_EN    : in  std_logic;
+
+    --  Media direction port
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_IN        : in  std_logic;
+
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_DATA_IN        : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_OUT       : out std_logic;
+
+    MED_STAT_OP_IN     : in  std_logic_vector(15 downto 0);
+    MED_CTRL_OP_OUT    : out std_logic_vector(15 downto 0);
+
+    --LVL1 trigger
+    TRG_SEND_IN         : in  std_logic;
+    TRG_TYPE_IN         : in  std_logic_vector (3 downto 0);
+    TRG_NUMBER_IN       : in  std_logic_vector (15 downto 0);
+    TRG_INFORMATION_IN  : in  std_logic_vector (7 downto 0);
+    TRG_RND_CODE_IN     : in  std_logic_vector (7 downto 0);
+    TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
+    TRG_BUSY_OUT        : out std_logic;
+
+    --IPU Channel
+    IPU_SEND_IN         : in  std_logic;
+    IPU_TYPE_IN         : in  std_logic_vector (3 downto 0);
+    IPU_NUMBER_IN       : in  std_logic_vector (15 downto 0);
+    IPU_INFORMATION_IN  : in  std_logic_vector (7 downto 0);
+    IPU_RND_CODE_IN     : in  std_logic_vector (7 downto 0);
+    -- Receiver port
+    IPU_DATA_OUT        : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    IPU_PACKET_NUM_OUT  : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    IPU_TYP_OUT         : out std_logic_vector (2 downto 0);
+    IPU_DATAREADY_OUT   : out std_logic;
+    IPU_READ_IN         : in  std_logic;
+    IPU_BUSY_OUT        : out std_logic;
+
+    -- Slow Control Data Port
+    REGIO_COMMON_STAT_REG_IN  : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+    REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+    REGIO_REGISTERS_IN        : in  std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+    REGIO_REGISTERS_OUT       : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+    REGIO_ADDR_OUT            : out std_logic_vector(16-1 downto 0);
+    REGIO_READ_ENABLE_OUT     : out std_logic;
+    REGIO_WRITE_ENABLE_OUT    : out std_logic;
+    REGIO_DATA_OUT            : out std_logic_vector(32-1 downto 0);
+    REGIO_DATA_IN             : in  std_logic_vector(32-1 downto 0) := (others => '0');
+    REGIO_DATAREADY_IN        : in  std_logic := '0';
+    REGIO_NO_MORE_DATA_IN     : in  std_logic := '0';
+    REGIO_WRITE_ACK_IN        : in  std_logic := '0';
+    REGIO_UNKNOWN_ADDR_IN     : in  std_logic := '0';
+    REGIO_TIMEOUT_OUT         : out std_logic;
+    REGIO_ONEWIRE_INOUT       : inout std_logic;
+    TRIGGER_MONITOR_IN        : in  std_logic;  --strobe when timing trigger received
+    GLOBAL_TIME_OUT           : out std_logic_vector(31 downto 0); --global time, microseconds
+    LOCAL_TIME_OUT            : out std_logic_vector(7 downto 0);  --local time running with chip frequency
+    TIME_SINCE_LAST_TRG_OUT   : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
+    TIMER_US_TICK_OUT         : out std_logic;  --1 tick every microsecond
+
+    );
+
+end entity;
+
+
+architecture trb_net16_endpoint_hades_cts_arch of trb_net16_endpoint_hades_cts is
+
+begin
+
+end architecture;
\ No newline at end of file

diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd
index 0551459fcc7b003eb97b9f9d989cdea2329e5ec2..6ac0e659e8f9106397ffd43cad698c499a34d174 100644 (file)
--- a/trb_net16_hub_ipu_logic.vhd
+++ b/trb_net16_hub_ipu_logic.vhd
@@ -462,7 +462,7 @@ begin
 --saving (D)HDR
 -------------------------
   gen_saving_dhdr : for i in 0 to POINT_NUMBER-1 generate
-    hdrram_write_enable(i) <= (reg_current_reply_reading_HDR(i) or current_reply_reading_DHDR(i)) and not reply_reading_H0(i);
+    hdrram_write_enable(i) <= (reg_current_reply_reading_HDR(i) or reg_current_reply_reading_DHDR(i)) and not reply_reading_H0(i);
 
 --     (current_reply_reading_HDR(i) and
 --                           (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) or reply_reading_F3(i))) or

diff --git a/trb_net16_regio_bus_handler.vhd b/trb_net16_regio_bus_handler.vhd
new file mode 100644 (file)
index 0000000..6632538
--- /dev/null
+++ b/trb_net16_regio_bus_handler.vhd
@@ -0,0 +1,130 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity trb_net16_regio_bus_handler is
+  generic(
+    PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 2;
+    PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));
+    PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)
+    );
+  port(
+    CLK                   : in  std_logic;
+    RESET                 : in  std_logic;
+    DAT_ADDR_IN           : in  std_logic_vector(15 downto 0); -- address bus
+    DAT_DATA_IN           : in  std_logic_vector(31 downto 0); -- data from TRB endpoint
+    DAT_DATA_OUT          : out std_logic_vector(31 downto 0); -- data to TRB endpoint
+    DAT_READ_ENABLE_IN    : in  std_logic; -- read pulse
+    DAT_WRITE_ENABLE_IN   : in  std_logic; -- write pulse
+    DAT_TIMEOUT_IN        : in  std_logic; -- access timed out
+    DAT_DATAREADY_OUT     : out std_logic; -- your data, master, as requested
+    DAT_WRITE_ACK_OUT     : out std_logic; -- data accepted
+    DAT_NO_MORE_DATA_OUT  : out std_logic; -- don't disturb me now
+    DAT_UNKNOWN_ADDR_OUT  : out std_logic; -- noone here to answer your request
+
+    BUS_ADDR_OUT          : out std_logic_vector(15 downto 0);
+    BUS_DATA_OUT          : out std_logic_vector(31 downto 0);
+    BUS_READ_ENABLE_OUT   : out std_logic_vector(PORT_NUMBER-1 downto 0);
+    BUS_WRITE_ENABLE_OUT  : out std_logic_vector(PORT_NUMBER-1 downto 0);
+    BUS_TIMEOUT_OUT       : out std_logic;
+
+    BUS_DATA_IN           : in  std_logic_vector(32*PORT_NUMBER-1 downto 0);
+    BUS_DATAREADY_IN      : in  std_logic_vector(PORT_NUMBER-1 downto 0);
+    BUS_WRITE_ACK_IN      : in  std_logic_vector(PORT_NUMBER-1 downto 0);
+    BUS_NO_MORE_DATA_IN   : in  std_logic_vector(PORT_NUMBER-1 downto 0);
+    BUS_UNKNOWN_ADDR_IN   : in  std_logic_vector(PORT_NUMBER-1 downto 0);
+
+    STAT_DEBUG            : out std_logic_vector(31 downto 0)
+    );
+end entity;
+
+
+
+architecture regio_bus_handler_arch of trb_net16_regio_bus_handler is
+
+  signal port_select          : std_logic_vector(PORT_NUMBER-1 downto 0);
+  signal next_port_select     : std_logic_vector(PORT_NUMBER-1 downto 0);
+  signal port_select_int      : integer range 0 to c_BUS_HANDLER_MAX_PORTS;
+  signal next_port_select_int : integer range 0 to c_BUS_HANDLER_MAX_PORTS;
+
+  signal buf_DAT_DATA_OUT         : std_logic_vector(31 downto 0);
+  signal buf_DAT_DATAREADY_OUT    : std_logic;
+  signal buf_DAT_WRITE_ACK_OUT    : std_logic;
+  signal buf_DAT_NO_MORE_DATA_OUT : std_logic;
+
+  signal buf_BUS_READ_OUT         : std_logic_vector(PORT_NUMBER-1 downto 0);
+  signal buf_BUS_WRITE_OUT        : std_logic_vector(PORT_NUMBER-1 downto 0);
+
+
+begin
+
+---------------------------------------------------------------------
+--Decode Addresses
+---------------------------------------------------------------------
+
+  proc_port_select : process(DAT_ADDR_IN)
+    begin
+      gen_port_select : for i in 0 to PORT_NUMBER-1 loop
+        next_port_select_int <= PORT_NUMBER;
+        if DAT_ADDR_IN(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(15 downto PORT_ADDR_MASK(i)) then
+          next_port_select(i) <= '1';
+          next_port_select_int <= i;
+        else
+          next_port_select(i) <= '0';
+        end if;
+      end loop;
+    end process;
+
+  proc_reg_port_sel : process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          port_select <= (others => '0');
+          port_select_int <= 0;
+        else
+          port_select <= next_port_select;
+          port_select_int <= next_port_select_int;
+        end if;
+      end if;
+    end process;
+
+
+---------------------------------------------------------------------
+--Generate R/W strobes
+---------------------------------------------------------------------
+
+  proc_rw_signals : process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          buf_BUS_READ_OUT  <= (others => '0');
+          buf_BUS_WRITE_OUT <= (others => '0');
+        else
+          buf_BUS_READ_OUT  <= (others => '0');
+          buf_BUS_WRITE_OUT <= (others => '0');
+          if DAT_READ_ENABLE_IN = '1' then
+            buf_BUS_READ_OUT(next_port_select_int) <= '1';
+          end if;
+          if DAT_WRITE_ENABLE_IN = '1' then
+            buf_BUS_WRITE_OUT(next_port_select_int) <= '1';
+          end if;
+        end if;
+      end if;
+    end process;
+
+
+
+
+---------------------------------------------------------------------
+--Multiplex Data Output
+---------------------------------------------------------------------
+
+
+
+
+end architecture;
\ No newline at end of file