-const char trbnet_version[] = "$Revision: 4.4 $";
+#if 0
+ dataBuffer = mmap(NULL,
+ dataBufferSize * 4,
+ PROT_READ,
+ MAP_SHARED,
+ pexorFileHandle,
+ 0x0);
+ tmp = dataBuffer;
+
+ // fprintf(stderr, "map it with size: %d\n", dataBufferSize);
+ if (tmp == ((void *)-1)) {
+ perror("mapping");
+ abort();
+ }
+#endif
+
+
+const char trbnet_version[] = "$Revision: 4.5 $";
#include <stdlib.h>
#include <signal.h>
#include <sys/ioctl.h>
#define PCIBAR 0
-
-#define DATA_BUFFER_SIZE 4096000 /* in 32-Bit words */
+
+#define DATA_BUFFER_SIZE 1048576 /* in 32-Bit words */
static uint32_t dataBuffer[DATA_BUFFER_SIZE];
+//static uint32_t* dataBuffer = NULL;
static unsigned int dataBufferSize = 0;
static struct pexor_trbnet_io pexorDescriptor;
uint32_t fifoAddress;
unsigned int counter = 0;
-#ifdef PEXOR
- if (pexor_dma != 0) return;
-#endif
-
fifoAddress = CHANNEL_N_RECEIVER_DATA | ((channel * 2 + 1) << 4);
do {
unsigned int timeout = 0;
do {
read32_from_FPGA(fifoAddress, &tmp);
- } while (((tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIMEOUT));
+ } while (((tmp & MASK_FIFO_VALID) == 0) && (++timeout < 10/*MAX_TIMEOUT*/));
/* DEBUG INFO */
if ((trb_debug > 1) && ((tmp & MASK_FIFO_VALID) != 0)) {
fprintf(stderr, "FLUSH_FIFO_%03d: 0x%08x\n", counter, tmp);
#ifndef PEXOR
static uint32_t dataBuffer = 0;
uint32_t* tmp = &dataBuffer;
+ uint32_t fifoBuffer = 0;
+ unsigned int timeout = 0;
#else /* Pexor DMA */
uint32_t* tmp = dataBuffer;
#endif
-
- uint32_t fifoBuffer = 0;
- unsigned int timeout = 0;
TRB_Package package = {0,0,0,0,0};
int headerType = 0;
and FIFO_MODE_IPU_DATA Mode */
#ifdef PEXOR
- if (pexor_dma != 0) {
- if (dataBufferSize == 0) {
- trb_errno = TRB_PEXOR_DMA_ERROR;
- return -1;
- }
- } else {
-#endif
-
- /* Determin FIFO-Address */
- if (channel >= 4) {
- trb_errno = TRB_INVALID_CHANNEL;
- return -1;
- }
- fifoBuffer = CHANNEL_N_RECEIVER_DATA | ((channel * 2 + 1) << 4);
-
- /* Check for FIFO Ready */
- timeout = 0;
- do {
- read32_from_FPGA(fifoBuffer, tmp);
- } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIMEOUT));
-
- if (timeout >= MAX_TIMEOUT) {
- fifo_flush(channel);
- trb_errno = TRB_FIFO_TIMEOUT;
- return -1;
- }
-#ifdef PEXOR
+ if (dataBufferSize == 0) {
+ trb_errno = TRB_PEXOR_DMA_ERROR;
+ return -1;
+ }
+ if (read(pexorFileHandle,
+ (void*)dataBuffer, dataBufferSize * 4) != dataBufferSize * 4) {
+ trb_errno = TRB_PEXOR_DMA_ERROR;
+ return -1;
+ }
+#else
+
+ /* Determin FIFO-Address */
+ if (channel >= 4) {
+ trb_errno = TRB_INVALID_CHANNEL;
+ return -1;
+ }
+ fifoBuffer = CHANNEL_N_RECEIVER_DATA | ((channel * 2 + 1) << 4);
+
+ /* Check for FIFO Ready */
+ timeout = 0;
+ do {
+ read32_from_FPGA(fifoBuffer, tmp);
+ } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIMEOUT));
+
+ if (timeout >= MAX_TIMEOUT) {
+ fifo_flush(channel);
+ trb_errno = TRB_FIFO_TIMEOUT;
+ return -1;
}
#endif
/* Read FIFO-Buffer, copy to User-Buffer */
while ((*tmp & MASK_FIFO_VALID) != 0) {
-
+
fifoDebugCtr++;
if (((*tmp & MASK_FIFO_TYPE) >> SHIFT_FIFO_TYPE) == FIFO_TYPE_IS_HEADER) {
fprintf(stderr, "FIFO_%03d: 0x%08x\n",
fifoDebugCtr, *tmp);
}
-
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INCOMPLETE_PACKAGE;
return -1;
}
if (((*tmp & MASK_FIFO_TYPE) >> SHIFT_FIFO_TYPE) !=
(counter - 1) % 2) {
/* Error: invalid sequence (not 0, 1, .), flush FIFO-BUFFER, exit */
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_SEQUENZ;
return -1;
}
/* First package: headerType must be HDR or TRM */
if (packageCtr == 0) {
if (!((headerType == HEADER_HDR) || (headerType == HEADER_TRM))) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
!= channel)) {
/* Error Package inconsistencies, flush FIFO-BUFFER and exit */
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_HEADERS;
return -1;
}
switch (mode) {
case FIFO_MODE_TERM_ONLY:
if (packageCtr > 0) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_INVALID_PKG_NUMBER;
return -1;
}
if (headerType != HEADER_TRM) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
switch (headerType) {
case HEADER_HDR:
if ((packageCtr - endPointCtr * 2) != 0) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
case HEADER_DAT:
if ((packageCtr - endPointCtr * 2) != 1) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
break;
default:
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
switch (headerType) {
case HEADER_HDR:
if ((packageCtr - endPointCtr * 2) != 0) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
case HEADER_DAT:
if ((packageCtr - endPointCtr * 2) != 1) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
break;
default:
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
break;
default:
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
break;
default:
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
break;
default:
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
switch (headerType) {
case HEADER_HDR:
if (packageCtr != 0) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
case HEADER_TRM:
if ((packageCtr > 0) && (dataCtr != memLen)) {
/* Error invalid length */
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_HDR_DLEN;
return -1;
}
break;
default:
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
switch (headerType) {
case HEADER_HDR:
if ((packageCtr - endPointCtr * 3) != 0) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
break;
default:
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
case FIFO_MODE_SET_ADDRESS:
if (packageCtr > 2) {
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_INVALID_PKG_NUMBER;
return -1;
}
break;
default:
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_HEADER;
return -1;
}
break;
default:
+#ifndef PEXOR
fifo_flush(channel);
+#endif
trb_errno = TRB_FIFO_INVALID_MODE;
return -1;
}
}
#ifdef PEXOR
- if (pexor_dma != 0) {
- if (tmp - dataBuffer >= dataBufferSize) {
- trb_errno = TRB_PEXOR_DMA_ERROR;
- return -1;
- }
- tmp++;
- } else {
-#endif
- timeout = 0;
- do {
- read32_from_FPGA(fifoBuffer, tmp);
- } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIMEOUT));
-
- if (timeout >= MAX_TIMEOUT) {
- fifo_flush(channel);
- trb_errno = TRB_FIFO_TIMEOUT;
- return -1;
- }
-#ifdef PEXOR
+ if (tmp - dataBuffer >= dataBufferSize) {
+ trb_errno = TRB_PEXOR_DMA_ERROR;
+ return -1;
+ }
+ tmp++;
+#else
+ timeout = 0;
+ fprintf(stderr, "call\n");
+ do {
+ read32_from_FPGA(fifoBuffer, tmp);
+ } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIMEOUT));
+ fprintf(stderr, "last val: %x timeout %d\n", *tmp, timeout);
+
+ if (timeout >= MAX_TIMEOUT) {
+ fifo_flush(channel);
+ trb_errno = TRB_FIFO_TIMEOUT;
+ return -1;
}
#endif
- }
+
+ } /* end while () */
/* Copy StatusBits and Sequenze of TerminationPackage */
trb_term.status_common = package.F2;
int trb_fifo_flush(uint8_t channel)
{
-#ifdef PEXOR
- int dma;
-#endif
-
trb_errno = TRB_NONE;
if (channel >= 4) {
}
if (lockPorts(0) == -1) return -1;
-#ifdef PEXOR
- dma = pexor_dma;
- pexor_dma = 0;
-#endif
fifo_flush(channel);
-#ifdef PEXO
- pexor_dma = dma;
-#endif
if (unlockPorts(0) == -1) return -1;
fprintf(stderr, "Init_Transfer done.\n");
}
-#ifdef PEXOR
- if (pexor_dma == 0) {
-#endif
- /* Build package and start transfer */
#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
-#endif
- write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
-#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ);
+ /* Build package and start transfer */
+ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ);
#else
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
- (uint32_t)trb_address << 16 | CMD_REGISTER_READ);
- } else {
- /* Send command to pexor driver */
- pexorDescriptor.trb_address = trb_address;
- pexorDescriptor.reg_address = reg_address;
- pexorDescriptor.dma_addr = (unsigned long)dataBuffer;
- pexorDescriptor.dma_size = DATA_BUFFER_SIZE * 4;
- pexorDescriptor.command = PEXOR_TRBNETCOM_REG_READ;
-
- status = ioctl(pexorFileHandle,
- PEXOR_IOC_TRBNET_REQUEST,
- &pexorDescriptor);
-
- if (status != 0) {
- unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
- return -1;
- }
- dataBufferSize = pexorDescriptor.dma_size;
+ /* Send command to pexor driver */
+ pexorDescriptor.trb_address = trb_address;
+ pexorDescriptor.reg_address = reg_address;
+ pexorDescriptor.command = PEXOR_TRBNETCOM_REG_READ;
+ pexorDescriptor.dma = pexor_dma;
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
}
+ dataBufferSize = status;
#endif
-
+
/* DEBUG INFO */
if (trb_debug > 0) {
fprintf(stderr, "CMD_REGISTER_READ started.\n");
fprintf(stderr, "Init_Transfer done.\n");
}
-#ifdef PEXOR
- if (pexor_dma == 0) {
-#endif
- /* Build package and start transfer */
-#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
-#endif
- write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ);
+ /* Build package and start transfer */
+ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ);
#else
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
- (uint32_t)trb_address << 16 | CMD_REGISTER_READ);
- } else {
- /* Send command to pexor driver */
- pexorDescriptor.trb_address = trb_address;
- pexorDescriptor.reg_address = reg_address;
- pexorDescriptor.dma_addr = (unsigned long)dataBuffer;
- pexorDescriptor.dma_size = DATA_BUFFER_SIZE * 4;
- pexorDescriptor.command = PEXOR_TRBNETCOM_REG_READ;
- status = ioctl(pexorFileHandle,
- PEXOR_IOC_TRBNET_REQUEST,
- &pexorDescriptor);
- if (status != 0) {
- unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
- return -1;
- }
- dataBufferSize = pexorDescriptor.dma_size;
+ /* Send command to pexor driver */
+ pexorDescriptor.trb_address = trb_address;
+ pexorDescriptor.reg_address = reg_address;
+ pexorDescriptor.command = PEXOR_TRBNETCOM_REG_READ;
+ pexorDescriptor.dma = pexor_dma;
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
}
+ dataBufferSize = status;
#endif
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "CMD_REGISTER_READ started.\n");
+ fprintf(stderr, "CMD_REGISTERTIME_READ started.\n");
}
status = trb_fifo_read(3, FIFO_MODE_REGTIME_READ, data, dsize);
unsigned int dsize)
{
uint16_t length;
- int status;
+ int status = 0;
const uint32_t *p = NULL;
const uint32_t *end = NULL;
if (trb_debug > 0) {
fprintf(stderr, "Init_Transfer done.\n");
}
-#ifdef PEXOR
- if (pexor_dma == 0) {
-#endif
- /* Build package and start transfer */
-#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
-#endif
- write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, length);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+
#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM);
+ /* Build package and start transfer */
+ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, length);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM);
#else
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
- (uint32_t)trb_address << 16 | CMD_REGISTER_READ_MEM);
- } else {
- /* Send command to pexor driver */
- pexorDescriptor.trb_address = trb_address;
- pexorDescriptor.reg_address = reg_address;
- pexorDescriptor.arg0 = length;
- pexorDescriptor.dma_addr = (unsigned long)dataBuffer;
- pexorDescriptor.dma_size = DATA_BUFFER_SIZE * 4;
- pexorDescriptor.command = PEXOR_TRBNETCOM_REG_READ_MEM;
- status = ioctl(pexorFileHandle, PEXOR_IOC_TRBNET_REQUEST,
- &pexorDescriptor);
- if (status != 0) {
-
- unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
- return -1;
- }
- dataBufferSize = pexorDescriptor.dma_size;
+ /* Send command to pexor driver */
+ pexorDescriptor.trb_address = trb_address;
+ pexorDescriptor.reg_address = reg_address;
+ pexorDescriptor.arg0 = length;
+ pexorDescriptor.command = PEXOR_TRBNETCOM_REG_READ_MEM;
+ pexorDescriptor.dma = pexor_dma;
+ status = ioctl(pexorFileHandle, PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
}
+ dataBufferSize = status;
#endif
-
+
/* DEBUG INFO */
if (trb_debug > 0) {
fprintf(stderr, "CMD_REGISTER_READ_MEM started.\n");
}
-
+
status = trb_fifo_read(3, FIFO_MODE_REG_READ_MEM, data, dsize);
-
+
if (unlockPorts(0) == -1) return -1;
-
+
if (status == -1) return status;
/* Check size */
if (trb_debug > 0) {
fprintf(stderr, "Init_Transfer done.\n");
}
-#ifdef PEXOR
- if (pexor_dma == 0) {
-#endif
- /* Build package and start transfer */
-#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
-#endif
- write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, length);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+
#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM);
+ /* Build package and start transfer */
+ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, length);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM);
#else
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
- (uint32_t)trb_address << 16 | CMD_REGISTER_READ_MEM);
- } else {
- /* Send command to pexor driver */
- pexorDescriptor.trb_address = trb_address;
- pexorDescriptor.reg_address = reg_address;
- pexorDescriptor.arg0 = length;
- pexorDescriptor.dma_addr = (unsigned long)dataBuffer;
- pexorDescriptor.dma_size = DATA_BUFFER_SIZE * 4;
- pexorDescriptor.command = PEXOR_TRBNETCOM_REG_READ_MEM;
- status = ioctl(pexorFileHandle,
- PEXOR_IOC_TRBNET_REQUEST,
- &pexorDescriptor);
- if (status != 0) {
- unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
- return -1;
- }
- dataBufferSize = pexorDescriptor.dma_size;
+ /* Send command to pexor driver */
+ pexorDescriptor.trb_address = trb_address;
+ pexorDescriptor.reg_address = reg_address;
+ pexorDescriptor.arg0 = length;
+ pexorDescriptor.command = PEXOR_TRBNETCOM_REG_READ_MEM;
+ pexorDescriptor.dma = pexor_dma;
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
}
+ dataBufferSize = status;
#endif
-
+
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "CMD_REGISTER_READ_MEM started.\n");
+ fprintf(stderr, "CMD_REGISTERTIME_READ_MEM started.\n");
}
status = trb_fifo_read(3, FIFO_MODE_REGTIME_READ_MEM, data, dsize);
-
+
if (unlockPorts(0) == -1) return -1;
-
+
if (status == -1) {
return status;
}
fprintf(stderr, "Init_Transfer done.\n");
}
-#ifdef PEXOR
- if (pexor_dma == 0) {
-#endif
- /* Build package */
-#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
-#endif
- write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, (value >> 16) & 0xffff);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, value & 0xffff);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE);
+ /* Build package */
+ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, (value >> 16) & 0xffff);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, value & 0xffff);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE);
#else
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
- (uint32_t)trb_address << 16 | CMD_REGISTER_WRITE);
- } else {
- /* Send command to pexor driver */
- pexorDescriptor.trb_address = trb_address;
- pexorDescriptor.reg_address = reg_address;
- pexorDescriptor.arg0 = value;
- pexorDescriptor.dma_addr = (unsigned long)dataBuffer;
- pexorDescriptor.dma_size = DATA_BUFFER_SIZE * 4;
- pexorDescriptor.command = PEXOR_TRBNETCOM_REG_WRITE;
- status = ioctl(pexorFileHandle,
- PEXOR_IOC_TRBNET_REQUEST,
- &pexorDescriptor);
- if (status != 0) {
- unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
- return -1;
- }
- dataBufferSize = pexorDescriptor.dma_size;
+ /* Send command to pexor driver */
+ pexorDescriptor.trb_address = trb_address;
+ pexorDescriptor.reg_address = reg_address;
+ pexorDescriptor.arg0 = value;
+ pexorDescriptor.command = PEXOR_TRBNETCOM_REG_WRITE;
+ pexorDescriptor.dma = pexor_dma;
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
}
+ dataBufferSize = status;
#endif
/* DEBUG INFO */
{
static const uint16_t blockSize = 128;
uint16_t config;
- uint16_t i;
uint16_t ctr = 0;
int status = -1;
+#ifndef PEXOR
+ uint16_t i;
+#endif
trb_errno = TRB_NONE;
fprintf(stderr, "Init_Transfer done.\n");
}
-#ifdef PEXOR
- if (pexor_dma == 0) {
-#endif
- /* Build package */
-#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
-#endif
- write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
- if (option == 0) {
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address + ctr);
- } else {
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
- }
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, config);
+#ifndef PEXOR
+ /* Build package */
+ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
+ if (option == 0) {
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address + ctr);
+ } else {
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
+ }
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, config);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ for (i = 0; i < len; i++, ctr++) {
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, (data[ctr] >> 16) & 0xffff);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, data[ctr] & 0xffff);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- for (i = 0; i < len; i++, ctr++) {
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, (data[ctr] >> 16) & 0xffff);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, data[ctr] & 0xffff);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- }
-#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE_MEM);
+ }
+ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE_MEM);
#else
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
- (uint32_t)trb_address << 16 | CMD_REGISTER_WRITE_MEM);
+ /* Send command to pexor driver */
+ pexorDescriptor.trb_address = trb_address;
+ if (option == 0) {
+ pexorDescriptor.reg_address = reg_address + ctr;
} else {
- /* Send command to pexor driver */
- pexorDescriptor.trb_address = trb_address;
- if (option == 0) {
- pexorDescriptor.reg_address = reg_address + ctr;
- } else {
- pexorDescriptor.reg_address = reg_address;
- }
- pexorDescriptor.arg0 = config;
- pexorDescriptor.arg1 = (unsigned long)data;
- pexorDescriptor.arg2 = len;
- pexorDescriptor.dma_addr = (unsigned long)dataBuffer;
- pexorDescriptor.dma_size = DATA_BUFFER_SIZE * 4;
- pexorDescriptor.command = PEXOR_TRBNETCOM_REG_WRITE_MEM;
-
- status = ioctl(pexorFileHandle,
- PEXOR_IOC_TRBNET_REQUEST,
- &pexorDescriptor);
- if (status != 0) {
- unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
- return -1;
- }
- dataBufferSize = pexorDescriptor.dma_size;
- ctr += len;
+ pexorDescriptor.reg_address = reg_address;
}
+ pexorDescriptor.arg0 = config;
+ pexorDescriptor.arg1 = (unsigned long)data;
+ pexorDescriptor.arg2 = len;
+ pexorDescriptor.command = PEXOR_TRBNETCOM_REG_WRITE_MEM;
+ pexorDescriptor.dma = pexor_dma;
+
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
+ }
+ dataBufferSize = status;
+ ctr += len;
#endif
-
+
/* DEBUG INFO */
if (trb_debug > 0) {
fprintf(stderr, "CMD_REGISTER_WRITE_MEM started %d.\n", len);
if (trb_debug > 0) {
fprintf(stderr, "Init_Transfer done.\n");
}
-
-#ifdef PEXOR
- if (pexor_dma == 0) {
-#endif
- /* Build package and start transfer */
-#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
-#endif
- write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, NET_READUNIQUEID);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+
#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION);
+ /* Build package and start transfer */
+ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, NET_READUNIQUEID);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION);
#else
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
- (uint32_t)trb_address << 16| CMD_NETADMINISTRATION);
- } else {
- /* Send command to pexor driver */
- pexorDescriptor.trb_address = trb_address;
- pexorDescriptor.dma_addr = (unsigned long)dataBuffer;
- pexorDescriptor.dma_size = DATA_BUFFER_SIZE * 4;
- pexorDescriptor.command = PEXOR_TRBNETCOM_READ_UID;
- status = ioctl(pexorFileHandle,
- PEXOR_IOC_TRBNET_REQUEST,
- &pexorDescriptor);
- if (status != 0) {
- unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
- return -1;
- }
- dataBufferSize = pexorDescriptor.dma_size;
+ /* Send command to pexor driver */
+ pexorDescriptor.trb_address = trb_address;
+ pexorDescriptor.command = PEXOR_TRBNETCOM_READ_UID;
+ pexorDescriptor.dma = pexor_dma;
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
}
+ dataBufferSize = status;
#endif
-
+
/* DEBUG INFO */
if (trb_debug > 0) {
fprintf(stderr, "CMD_READ_UNIQUE_ID started.\n");
}
status = trb_fifo_read(3, FIFO_MODE_UID, (uint32_t*)data, dsize);
-
+
if (unlockPorts(0) == -1) return -1;
-
+
if ((status > 0) && (status % 4 != 0)) {
trb_errno = TRB_INVALID_PKG_NUMBER;
return -1;
}
-
+
return status;
}
-
int trb_set_address(uint64_t uid,
uint8_t endpoint,
uint16_t trb_address)
fprintf(stderr, "Init_Transfer done.\n");
}
-#ifdef PEXOR
- if (pexor_dma == 0) {
-#endif
- /* Build package and start transfer */
#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0xffff); /* always broadcast */
-#endif
- write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, NET_SETADDRESS);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, (uint16_t)(uid));
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, (uint16_t)(uid >> 16));
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, (uint16_t)(uid >> 32));
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, (uint16_t)(uid >> 48));
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, endpoint);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, trb_address);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
-#ifndef PEXOR
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION);
+ /* Build package and start transfer */
+ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0xffff); /* always broadcast */
+ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, NET_SETADDRESS);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, (uint16_t)(uid));
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, (uint16_t)(uid >> 16));
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, (uint16_t)(uid >> 32));
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, (uint16_t)(uid >> 48));
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, endpoint);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, trb_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION);
#else
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
- 0xffff0000 | CMD_NETADMINISTRATION); /* always broadcast */
- } else {
- /* Send command to pexor driver */
- pexorDescriptor.trb_address = trb_address;
- pexorDescriptor.arg0 = (unsigned long)(uid & 0xffffffff);
- pexorDescriptor.arg1 = (unsigned long)(uid >> 32 & 0xffffffff);
- pexorDescriptor.arg2 = endpoint;
- pexorDescriptor.dma_addr = (unsigned long)dataBuffer;
- pexorDescriptor.dma_size = DATA_BUFFER_SIZE * 4;
- pexorDescriptor.command = PEXOR_TRBNETCOM_SET_ADDRESS;
- status = ioctl(pexorFileHandle,
- PEXOR_IOC_TRBNET_REQUEST,
- &pexorDescriptor);
- if (status != 0) {
- unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
- return -1;
- }
- dataBufferSize = pexorDescriptor.dma_size;
+ /* Send command to pexor driver */
+ pexorDescriptor.trb_address = trb_address;
+ pexorDescriptor.arg0 = (unsigned long)(uid & 0xffffffff);
+ pexorDescriptor.arg1 = (unsigned long)(uid >> 32 & 0xffffffff);
+ pexorDescriptor.arg2 = endpoint;
+ pexorDescriptor.command = PEXOR_TRBNETCOM_SET_ADDRESS;
+ pexorDescriptor.dma = pexor_dma;
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
}
+ dataBufferSize = status;
#endif
/* DEBUG INFO */
uint32_t *data,
unsigned int dsize)
{
-#ifdef PEXOR
- int dma = pexor_dma;
-#endif
int status;
trb_errno = TRB_NONE;
fprintf(stderr, "Init_Transfer done.\n");
}
+#ifndef PEXOR
/* Prepare IPU channel */
write32_to_FPGA(CHANNEL_1_SENDER_ERROR, (((uint32_t)trg_info << 24) |
((uint32_t)trg_random << 16) |
));
write32_to_FPGA(CHANNEL_1_SENDER_CONTROL,
SHORT_TRANSFER | (uint32_t)(type & 0x0f));
+#else
+ pexorDescriptor.arg0 = (unsigned long)(type);
+ pexorDescriptor.arg1 = (unsigned long)(trg_info);
+ pexorDescriptor.arg2 = (unsigned long)(((uint32_t)trg_random << 16) |
+ ((uint32_t)trg_number)
+ );
+ pexorDescriptor.command = PEXOR_TRBNETCOM_IPU_DATA_READ;
+ pexorDescriptor.dma = pexor_dma;
+
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
+ }
+ dataBufferSize = status;
+#endif
/* DEBUG INFO */
if (trb_debug > 0) {
fprintf(stderr, "CMD_IPU_DATA_READ started.\n");
}
-#ifdef PEXOR
- pexor_dma = 0;
-#endif
-
/* Get IPU Data */
status = trb_fifo_read(1, FIFO_MODE_IPU_DATA, data, dsize);
-#ifdef PEXOR
- pexor_dma = dma;
-#endif
-
if (unlockPorts(0) == -1) return -1;
return status;
uint8_t trg_random,
uint16_t trg_number)
{
-#ifdef PEXOR
- int dma = pexor_dma;
-#endif
int status;
trb_errno = TRB_NONE;
fprintf(stderr, "Init_Transfer done.\n");
}
+#ifndef PEXOR
/* Prepare trigger channel */
write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((trg_info & 0xff) << 24) |
((uint32_t)trg_random << 16) |
/* Send trigger */
write32_to_FPGA(CHANNEL_0_SENDER_CONTROL,
SHORT_TRANSFER | (uint32_t)(type & 0x0f));
+#else
+ pexorDescriptor.arg0 = (unsigned long)(type);
+ pexorDescriptor.arg1 = (unsigned long)(trg_info);
+ pexorDescriptor.arg2 = (unsigned long)(((uint32_t)trg_random << 16) |
+ ((uint32_t)trg_number)
+ );
+ pexorDescriptor.command = PEXOR_TRBNETCOM_SEND_TRIGGER;
+ pexorDescriptor.dma = pexor_dma;
+
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
+ }
+ dataBufferSize = status;
+#endif
if (trb_debug > 0) {
fprintf(stderr, "trigger started.\n");
}
-
-
-#ifdef PEXOR
- pexor_dma = 0;
-#endif
-
+
/* Check for replay packets (trigger) */
status = trb_fifo_read(0, FIFO_MODE_TERM_ONLY, NULL, 0);
-#ifdef PEXOR
- pexor_dma = dma;
-#endif
-
if (unlockPorts(0) == -1) return -1;
if (status == -1) return -1;
uint8_t trg_random,
uint16_t trg_number)
{
-#ifdef PEXOR
- int dma = pexor_dma;
-#endif
int status;
trb_errno = TRB_NONE;
fprintf(stderr, "Init_Transfer done.\n");
}
- /* Prepare trigger channel */
- write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((trg_info & 0xff) << 24) |
- ((uint32_t)trg_random << 16) |
- ((uint32_t)trg_number)
- ));
-
- write32_to_FPGA(CHANNEL_0_SENDER_TRIGGER_INFO, (trg_info >> 8) & 0xffff);
-
- /* Prepare slowcontrol channel */
#ifndef PEXOR
+ /* Prepare slowcontrol channel */
write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0x0000fffb); /* RICH Subnet only */
-#endif
write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0020);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000 | (0x01 << trg_input));
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, (0x01 << trg_input));
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
-
- /* Send both fake trigger and LVL1 information */
-#ifndef PEXOR
write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE);
#else
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
- 0xfffb | CMD_REGISTER_WRITE); /* RICH Subnet only */
+ pexorDescriptor.trb_address = 0xfffb; /* RICH Subnet only */
+ pexorDescriptor.reg_address = 0x0020;
+ pexorDescriptor.arg0 = (0x01 << trg_input);
+ pexorDescriptor.command = PEXOR_TRBNETCOM_REG_WRITE;
+ pexorDescriptor.dma = pexor_dma;
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
+ }
+ dataBufferSize = status;
#endif
- usleep(1000);
+
+ /* Check for reply packets (slowcontrol) */
+ status = trb_fifo_read(3, FIFO_MODE_TERM_ONLY, NULL, 0);
+ if (status == -1) {
+ fifo_flush(0);
+ unlockPorts(0);
+ return -1;
+ }
+
+#ifndef PEXOR
+ /* Prepare trigger channel */
+ write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((trg_info & 0xff) << 24) |
+ ((uint32_t)trg_random << 16) |
+ ((uint32_t)trg_number)
+ ));
+ write32_to_FPGA(CHANNEL_0_SENDER_TRIGGER_INFO, (trg_info >> 8) & 0xffff);
write32_to_FPGA(CHANNEL_0_SENDER_CONTROL,
SHORT_TRANSFER | (uint32_t)(type & 0x0f));
+#else
+ pexorDescriptor.arg0 = (unsigned long)(type);
+ pexorDescriptor.arg1 = (unsigned long)(trg_info);
+ pexorDescriptor.arg2 = (unsigned long)(((uint32_t)trg_random << 16) |
+ ((uint32_t)trg_number)
+ );
+ pexorDescriptor.command = PEXOR_TRBNETCOM_SEND_TRIGGER;
+ pexorDescriptor.dma = pexor_dma;
+
+ status = ioctl(pexorFileHandle,
+ PEXOR_IOC_TRBNET_REQUEST,
+ &pexorDescriptor);
+ if (status < 0) {
+ unlockPorts(0);
+ trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ return -1;
+ }
+ dataBufferSize = status;
+#endif
if (trb_debug > 0) {
fprintf(stderr, "trigger started.\n");
}
-
-#ifdef PEXOR
- pexor_dma = 0;
-#endif
-
- /* Check for reply packets (slowcontrol) */
- status = trb_fifo_read(3, FIFO_MODE_TERM_ONLY, NULL, 0);
-
-#ifdef PEXOR
- pexor_dma = dma;
-#endif
-
+ /* Check for replay packets (trigger) */
+ status = trb_fifo_read(0, FIFO_MODE_TERM_ONLY, NULL, 0);
if (status == -1) {
fifo_flush(0);
unlockPorts(0);
return -1;
}
-
- /* Check for replay packets (trigger) */
- status = trb_fifo_read(0, FIFO_MODE_TERM_ONLY, NULL, 0);
-
+
if (unlockPorts(0) == -1) return -1;
if (status == -1) return -1;
jspc29 / trbnettools.git / commitdiff