-- 2002/05/31 : corrected TrigBus sequence, implemented BSY;
-- 2007/01/12 : change in libraries to adapt to trbnet: numeric -> arith
-- CLK_10 removed. Now DTU code is much faster than TRIGGERBUS.
+-- 2007/02/23 : DVAL is not being produced. ???
-------------------------------------------------------------------------------
library ieee;
signal TSTR_REG, TSTR_REG_REG : std_logic;
signal DSTR_REG, DSTR_REG_REG : std_logic;
-- signal DVAL_REG, DVAL_REG_LONG, DVAL_sync : std_logic;
- signal DVAL_REG : std_logic;
+ signal DVAL_REG, DVAL_REG_REG : std_logic;
signal DIN_REG : std_logic_vector(3 downto 0);
-- signal counter_for_DVAL : integer range 0 to 3;
if NIBCNT >= 3 then
NIBCNT <= 0;
DVAL_REG <= '1';
- elsif (DSTR_REG = '1') and (DSTR_REG_REG = '0') then
+ elsif (DSTR_REG = '0') and (DSTR_REG_REG = '1') then
NIBCNT <= NIBCNT + 1;
end if;
end if;
TRIGBUFF(1) <= (others => '0');
TRIGBUFF(2) <= (others => '0');
elsif CLK'event and CLK = '1' then -- rising clock edge
- if (DSTR_REG = '0') and (DSTR_REG_REG = '1') then
+ if (DSTR_REG = '0') and (DSTR_REG_REG = '1') then -- falling edge of DSTR
TRIGBUFF(2) <= TRIGBUFF(1);
TRIGBUFF(1) <= TRIGBUFF(0);
TRIGBUFF(0) <= DIN_REG; -- shift register
end if;
end process Shift_Reg;
--- -- purpose: stretch DVAL_REG by four so it can be synchronised by CLK_10
--- -- type : sequential
--- -- inputs : CLK, RES, DVAL_REG
--- -- outputs: DVAL_REG_LONG
--- lenghten_DVAL_REG: process (CLK, RES)
--- begin -- process lenghten_DVAL_REG
--- if RES = '1' then -- asynchronous reset (active low)
--- DVAL_REG_LONG <= '0';
--- counter_for_DVAL <= 3;
--- elsif CLK'event and CLK = '1' then -- rising clock edge
--- DVAL_REG_LONG <= '0';
--- if DVAL_REG='1' then
--- counter_for_DVAL <= 0;
--- DVAL_REG_LONG <= '1';
--- end if;
--- if counter_for_DVAL < 3 then
--- counter_for_DVAL <= counter_for_DVAL + 1;
--- DVAL_REG_LONG <= '1';
--- end if;
--- end if;
--- end process lenghten_DVAL_REG;
-
--- synchronise_DVAL_REG_LONG_to_CLK_10_1: process (CLK_10, RES)
--- begin -- process synchronise_DVAL_REG_LONG to CLK_10
--- if RES = '1' then -- asynchronous reset (active low)
--- DVAL_sync <= '0';
--- elsif CLK_10'event and CLK_10 = '1' then -- rising clock edge
--- DVAL_sync <= DVAL_REG_LONG;
--- end if;
--- end process synchronise_DVAL_REG_LONG_to_CLK_10_1;
-
--- synchronise_DVAL_REG_LONG_to_CLK_10_2: process (CLK_10, RES)
--- begin -- process synchronise_DVAL_REG_LONG to CLK_10
--- if RES = '1' then -- asynchronous reset (active low)
--- DVAL <= '0';
--- elsif CLK_10'event and CLK_10 = '1' then -- rising clock edge
--- DVAL <= DVAL_sync;
--- end if;
--- end process synchronise_DVAL_REG_LONG_to_CLK_10_2;
-- purpose: register DVAL
-- type : sequential
-- inputs : CLK, RES, DVAL
-- outputs: DVAL_sync
- DVAL_OUT : process (CLK, RES)
+ DVAL_OUT : process (CLK, RES, DVAL_REG)
begin -- process DVAL_reg
- if RES = '0' then -- asynchronous reset (active low)
+ if RES = '1' then -- asynchronous reset (active low)
+ DVAL_REG_REG <= '0';
DVAL <= '0';
elsif CLK'event and CLK = '1' then -- rising clock edge
- DVAL <= DVAL_reg;
+ DVAL_REG_REG <= DVAL_REG;
+ DVAL <= DVAL_REG or DVAL_REG_REG;
end if;
end process DVAL_OUT;
+
SynchBSY : process(RES, CLK)
begin
-- File : trb_net_old_to_new.vhd
-- Author : Tiago Perez (tiago.perez@uni-giessen.de)
-- Created : 2007/01/12
--- Last modified : 2007/01/12 T. Perez
+-- Last modified : 2007/02/26 T. Perez
-------------------------------------------------------------------------------
-- Description : Interace between "old" and "new" trigger nets
--
-- trigger bus, but now, samplig at ca. 400MHz we may sample T and
-- TS sereval times while falling and still not set. We should
-- chek the quality and "sharpness" of the Triggerbus with a scope
--- and eventually downscale the main clock to sample slower.
+-- and eventually downscale the main clock to sample slower.
+-- 2007/02/26: T. Perez (tiago.perez@uni-giessen.de)
+-- Change FSM so that all outouts are registered. OUTPUTS are
+-- decoded from the next_state to avoid losing CLK cycles. There
+-- is an external counter to do the sendig procedure.
-------------------------------------------------------------------------------
library IEEE;
end component;
-- SIGNALS
- signal TRIGTAG_i, TRIGTAG_ii : std_logic_vector(7 downto 0);
--- signal TRIGCODE_i : std_logic_vector(3 downto 0);
- signal DVAL_i, TRIGTAG_MISMATCH_i : std_logic;
--- signal OLD_CLK, OLD_CLK_10 : std_logic;
+ signal TRIGTAG_i, TRIGTAG_ii : std_logic_vector(7 downto 0);
+ signal TRIGCODE_i : std_logic_vector(3 downto 0);
+ signal DVAL_i : std_logic;
+ signal TRIGTAG_MISMATCH_reg : std_logic;
- type State_Type is (idle, compare, send, error_1);
+ type State_Type is (idle, check_code, compare, send, error_1);
signal present_state, next_state : State_Type;
- signal do_send_cnt : unsigned(3 downto 0);
- signal RESET_STATE : std_logic;
-
+ signal do_send_cnt : unsigned(3 downto 0);
+
+
begin
APL_DATA_OUT(7 downto 0) <= TRIGTAG_ii;
-----------------------------------------------------------------------------
CLK => CLK,
DVAL => DVAL_i,
TRIGTAG => TRIGTAG_i,
- TRIGCODE => APL_DTYPE_OUT,
- TRIGTAG_MISMATCH => TRIGTAG_MISMATCH_i,
+ TRIGCODE => TRIGCODE_i,
+ TRIGTAG_MISMATCH => TRIGTAG_MISMATCH_reg,
BUSY => APL_RUN_IN);
-----------------------------------------------------------------------------
end if;
end process state_clocked;
- -- purpose: Finite State Machine
+ -- purpose: Calculates the next_state of the FSM.
-- type : combinational
- -- inputs : present_state
- -- outputs:
- FSM : process (present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, APL_RUN_IN)
+ -- inputs : present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, APL_RUN_IN
+ -- outputs: next_state
+ FSM : process (present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, APL_RUN_IN, TRIGCODE_i, do_send_cnt)
begin -- process FSM
next_state <= present_state;
case present_state is
- when idle =>
+ when idle =>
if DVAL_i = '1' then
+ next_state <= check_code;
+ end if;
+ when check_code =>
+ -- Check for BEGIN_RUN
+ if TRIGCODE_i = x"d" then
+ next_state <= idle;
+ else
next_state <= compare;
end if;
- when compare =>
+ when compare =>
if TRIGTAG_ii = APL_SEQNR_IN then
next_state <= send;
else
next_state <= error_1;
end if;
- when send =>
- if APL_RUN_IN = '1' then
- next_state <= idle;
- end if;
- when others => null;
+ when send =>
+ if do_send_cnt = 5 then
+ --if APL_RUN_IN = '1' then
+ next_state <= idle;
+ end if;
+ when others => null;
end case;
end process FSM;
- -- purpose: decode the output signals of FSM
- -- type : combinational
- -- inputs : present_state
- -- outputs:
- decode_output : process (present_state, CLK, RESET_STATE)
+ -- purpose: decode and register the output signals of FSM
+ -- type : sequentia
+ -- inputs : next_state
+ -- outputs: TRIGTAG
+ decode_output : process (CLK, RESET, CLK_EN, next_state, do_send_cnt)
begin -- process decode_output
- TRIGTAG_MISMATCH_i <= '0';
- APL_SEND_OUT <= '0';
- APL_READ_OUT <= '0';
- RESET_STATE <= '0';
- case present_state is
- when idle =>
- TRIGTAG_MISMATCH_i <= '1';
- RESET_STATE <= '1';
- when compare =>
- APL_READ_OUT <= '1';
- when send =>
- if RESET_STATE='1' then
- do_send_cnt <= "0000";
- elsif CLK'event and CLK='1' then
- do_send_cnt <= do_send_cnt+1;
- end if;
+ if RESET = '1' then
+ TRIGTAG_MISMATCH_reg <= '0';
+ APL_SEND_OUT <= '0';
+ APL_READ_OUT <= '0';
- if do_send_cnt = 1 then
- APL_SEND_OUT <= '1';
- elsif do_send_cnt=3 or do_send_cnt=4 then
- APL_READ_OUT <= '1';
- end if;
-
- when error_1 =>
- TRIGTAG_MISMATCH_i <= '1';
- when others => null;
- end case;
+ APL_DTYPE_OUT <= (others => '0');
+ elsif CLK'event and CLK = '1' and CLK_EN = '1' then
+ TRIGTAG_MISMATCH_reg <= '0';
+ APL_SEND_OUT <= '0';
+ APL_READ_OUT <= '0';
+
+ APL_DTYPE_OUT <= (others => '0');
+
+ case next_state is
+ when idle =>
+ --when check_code =>
+
+ when compare =>
+ APL_DTYPE_OUT <= TRIGCODE_i;
+
+ when send =>
+ APL_DTYPE_OUT <= TRIGCODE_i;
+ if do_send_cnt = 1 then
+ APL_SEND_OUT <= '1';
+ end if;
+ if (do_send_cnt = 3) or (do_send_cnt = 4) then
+ APL_READ_OUT <= '1';
+ end if;
+ when error_1 =>
+ TRIGTAG_MISMATCH_reg <= '1';
+ when others => null;
+ end case;
+ end if;
end process decode_output;
-
+
+ send_counter : process (CLK, RESET, next_state)
+ begin -- process send
+ if RESET = '1' or present_state = idle then -- asynchronous reset (active low)
+ do_send_cnt <= (others => '0');
+ elsif CLK'event and CLK = '1' and present_state = send then -- rising clock edge
+ do_send_cnt <= do_send_cnt+1;
+ end if;
+ end process send_counter;
+
end behavioral;
jspc29 / trbnet.git / commitdiff