-# LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-# LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-# LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-# LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC" ;
-# LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD" ;
-LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB";
-LOCATE COMP "gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB";
-LOCATE COMP "gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC";
+#LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB";
+LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB";
+LOCATE COMP "gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB";
+LOCATE COMP "gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC";
LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
BLOCK PATH FROM CELL THE_TDC/calibration_o*;
REGION "MEDIA_C" "R102C128" 13 40;
REGION "MEDIA_B" "R102C55" 13 40;
REGION "MEDIA_DOWN1" "R102C20D" 13 120;
-#LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ;
LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_B" ;
LOCATE UGROUP "gen_PCSC.THE_MEDIA_PCSC/media_interface_group" REGION "MEDIA_C" ;
LOCATE UGROUP "gen_PCSB_ADDON.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_B" ;
-# UGROUP "GBE_GROUP" BBOX 44 60
-# # BLKNAME GBE;
-# BLKNAME GBE/physical_impl_gen.physical
-# ;
-# LOCATE UGROUP "GBE_GROUP" SITE "R71C2D"; #114 54
-
FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz;
FREQUENCY NET "GBE/clk_125_rx_from_pcs[3]" 125 MHz;
-#MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns;
-#MULTICYCLE FROM CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns;
-#MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/PROC_SCI_CTRL.wa*" 20 ns;
-#BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i";
-#BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i";
-#BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i";
-#BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i";
-#
MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns;
MULTICYCLE FROM CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns;
MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns;
BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i";
BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i";
BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i";
-#
+
MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns;
MULTICYCLE FROM CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns;
MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns;
BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_write_i";
BLOCK PATH TO CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i";
BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i";
-#
+
MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns;
MULTICYCLE FROM CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns;
MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/PROC_SCI_CTRL.wa*" 20 ns;
BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i";
BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i";
BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i";
-#MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns;
-#MULTICYCLE FROM CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns;
-#MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/PROC_SCI_CTRL.wa*" 20 ns;
-#BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i";
-#BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i";
-#BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i";
-#BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i";
-#
-#MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/sci*" 20 ns;
-#MULTICYCLE FROM CELL "THE_MEDIA_4_PCSC/sci*" 20 ns;
-#MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/PROC_SCI_CTRL.wa*" 20 ns;
-#BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_write_i";
-#BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_write_i";
-#BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_read_i";
-#BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_read_i";
-#
-#MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns;
-#MULTICYCLE FROM CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns;
-#MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/PROC_SCI_CTRL.wa*" 20 ns;
-#BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i";
-#BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i";
-#BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i";
-#BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i";
-
-#MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#MAXDELAY TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#
MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
MAXDELAY TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#
+
MULTICYCLE TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
MAXDELAY TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#
+
MULTICYCLE TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#MAXDELAY TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#
-#MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#MAXDELAY TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#
-#MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-#MAXDELAY TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-
PROHIBIT SECONDARY NET "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/reset_cnt" ;
-
-# PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ;
-# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps
-# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps
use work.trb_net16_hub_func.all;
use work.version.all;
use work.trb_net_gbe_components.all;
-use work.med_sync_define.all;
+use work.med_sync_define_RS.all;
entity trb3sc_hub is
port(
CLK_EXT_PLL_LEFT : in std_logic; --External Clock
--Additional IO
- HDR_IO : inout std_logic_vector(10 downto 1);
+-- HDR_IO : inout std_logic_vector(10 downto 1);
BACK_LVDS : inout std_logic_vector( 1 downto 0);
BACK_GPIO : inout std_logic_vector( 3 downto 0);
--Test Connectors
TEST_LINE : out std_logic_vector(15 downto 0)
- );
+ );
attribute syn_useioff : boolean;
attribute syn_useioff of FLASH_IN : signal is true;
attribute syn_useioff of FLASH_OUT : signal is true;
-
-
end entity;
architecture trb3sc_arch of trb3sc_hub is
signal trig_gen_out_i : std_logic_vector(3 downto 0);
signal monitor_inputs_i : std_logic_vector(17 downto 0);
-
-
+
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
attribute syn_keep of bussci1_rx : signal is true;
attribute syn_keep of bustc_rx : signal is true;
attribute syn_preserve of bustc_rx : signal is true;
-begin
-
+ signal word_sync_i : std_logic;
+ signal master_clk_i : std_logic;
+ signal master_reset_i : std_logic;
+ signal tx_pll_lol_qd_a_i : std_logic;
+ signal tx_pll_lol_qd_b_i : std_logic;
+ signal tx_pll_lol_qd_c_i : std_logic;
+ signal tx_pll_lol_qd_d_i : std_logic;
+ signal tx_pll_lol_all_i : std_logic;
+ signal tx_clk_avail_i : std_logic;
+ signal tx_pcs_rst_i : std_logic;
+ signal sync_tx_quad_i : std_logic;
+ signal link_tx_ready_i : std_logic;
+ signal rx_dlm_i : std_logic;
+ signal tx_reset_state : std_logic_vector(3 downto 0);
+ signal debug_i : std_logic_vector(31 downto 0);
+begin
---------------------------------------------------------------------------
-- Clock & Reset Handling
---------------------------------------------------------------------------
NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half,
RESET_FROM_NET => med2int(INTERFACE_NUM-1).stat_op(13),
SEND_RESET_IN => med2int(INTERFACE_NUM-1).stat_op(15),
-
+ --
BUS_RX => bustc_rx,
BUS_TX => bustc_tx,
-
+ --
RESET_OUT => reset_i,
CLEAR_OUT => clear_i,
GSR_OUT => GSR_N,
-
+ --
FULL_CLK_OUT => clk_full,
SYS_CLK_OUT => clk_sys,
REF_CLK_OUT => clk_full_osc,
-
+ --
ENPIRION_CLOCK => ENPIRION_CLOCK,
LED_RED_OUT => LED_RJ_RED,
LED_GREEN_OUT => LED_RJ_GREEN,
DEBUG_OUT => debug_clock_reset
- );
+ );
---------------------------------------------------------------------------
-- PCSA Uplink when backplane is used
---------------------------------------------------------------------------
gen_PCSA : if USE_BACKPLANE = c_YES generate
- THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync
- generic map(
- SERDES_NUM => 0,
- IS_SYNC_SLAVE => c_YES
- )
- port map(
- CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,
- CLK_INTERNAL_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection
- MEDIA_MED2INT => med2int(INTERFACE_NUM-1), --10 or 8
- MEDIA_INT2MED => int2med(INTERFACE_NUM-1),
-
- --Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
- --SFP Connection
- SD_PRSNT_N_IN => BACK_GPIO(1),
- SD_LOS_IN => BACK_GPIO(1),
- SD_TXDIS_OUT => BACK_GPIO(0),
- --Control Interface
- BUS_RX => bussci1_rx,
- BUS_TX => bussci1_tx,
- -- Status and control port
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => open
- );
+-- THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync
+-- generic map(
+-- SERDES_NUM => 0,
+-- IS_SYNC_SLAVE => c_YES
+-- )
+-- port map(
+-- CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,
+-- CLK_INTERNAL_FULL => clk_full_osc,
+-- SYSCLK => clk_sys,
+-- RESET => reset_i,
+-- CLEAR => clear_i,
+-- --Internal Connection
+-- MEDIA_MED2INT => med2int(INTERFACE_NUM-1), --10 or 8
+-- MEDIA_INT2MED => int2med(INTERFACE_NUM-1),
+-- --Sync operation
+-- RX_DLM => open,
+-- RX_DLM_WORD => open,
+-- TX_DLM => open,
+-- TX_DLM_WORD => open,
+-- --SFP Connection
+-- SD_PRSNT_N_IN => BACK_GPIO(1),
+-- SD_LOS_IN => BACK_GPIO(1),
+-- SD_TXDIS_OUT => BACK_GPIO(0),
+-- --Control Interface
+-- BUS_RX => bussci1_rx,
+-- BUS_TX => bussci1_tx,
+-- -- Status and control port
+-- STAT_DEBUG => med_stat_debug(63 downto 0),
+-- CTRL_DEBUG => open
+-- );
end generate;
---------------------------------------------------------------------------
-- PCSB Uplink without backplane and 3/4 downlinks
---------------------------------------------------------------------------
gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate
- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4
- generic map(
- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
- )
- port map(
- CLK_REF_FULL => clk_full_osc,
- CLK_INTERNAL_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear_i,
-
- --Internal Connection
- MEDIA_MED2INT(0) => med2int(4),
- MEDIA_MED2INT(1) => med2int(5),
- MEDIA_MED2INT(2) => med2int(6),
- MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE),
- MEDIA_INT2MED(0) => int2med(4),
- MEDIA_INT2MED(1) => int2med(5),
- MEDIA_INT2MED(2) => int2med(6),
- MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE),
-
- --Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
- --SFP Connection
- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
- SD_PRSNT_N_IN(2) => HUB_MOD0(7),
- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
-
- SD_LOS_IN(0) => HUB_LOS(5),
- SD_LOS_IN(1) => HUB_LOS(6),
- SD_LOS_IN(2) => HUB_LOS(7),
- SD_LOS_IN(3) => SFP_LOS(1),
-
- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
-
- --Control Interface
- BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
-
- -- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
- CTRL_DEBUG => open
- );
+-- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4
+-- generic map(
+-- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+-- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
+-- )
+-- port map(
+-- CLK_REF_FULL => clk_full_osc,
+-- CLK_INTERNAL_FULL => clk_full_osc,
+-- SYSCLK => clk_sys,
+-- RESET => reset_i,
+-- CLEAR => clear_i,
+-- --Internal Connection
+-- MEDIA_MED2INT(0) => med2int(4),
+-- MEDIA_MED2INT(1) => med2int(5),
+-- MEDIA_MED2INT(2) => med2int(6),
+-- MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE),
+-- MEDIA_INT2MED(0) => int2med(4),
+-- MEDIA_INT2MED(1) => int2med(5),
+-- MEDIA_INT2MED(2) => int2med(6),
+-- MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE),
+-- --Sync operation
+-- RX_DLM => open,
+-- RX_DLM_WORD => open,
+-- TX_DLM => open,
+-- TX_DLM_WORD => open,
+-- --SFP Connection
+-- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
+-- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
+-- SD_PRSNT_N_IN(2) => HUB_MOD0(7),
+-- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
+-- SD_LOS_IN(0) => HUB_LOS(5),
+-- SD_LOS_IN(1) => HUB_LOS(6),
+-- SD_LOS_IN(2) => HUB_LOS(7),
+-- SD_LOS_IN(3) => SFP_LOS(1),
+-- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
+-- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
+-- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
+-- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
+-- --Control Interface
+-- BUS_RX => bussci2_rx,
+-- BUS_TX => bussci2_tx,
+-- -- Status and control port
+-- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+-- CTRL_DEBUG => open
+-- );
end generate;
gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate
- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4_slave3
+ THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS
generic map(
- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_YES),
- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
- )
+ SERDES_NUM => 3,
+ SIM_MODE => 0,
+ IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_SLAVE),
+ IS_WAP_ZERO => 1
+ )
port map(
+ -- Clocks and reset
CLK_REF_FULL => clk_full_osc,
- CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
CLEAR => clear_i,
-
- --Internal Connection
- MEDIA_MED2INT(0) => med2int(4),
- MEDIA_MED2INT(1) => med2int(5),
- MEDIA_MED2INT(2) => med2int(6),
- MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1),
- MEDIA_INT2MED(0) => int2med(4),
- MEDIA_INT2MED(1) => int2med(5),
- MEDIA_INT2MED(2) => int2med(6),
- MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1),
-
- --Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
+ -- Media Interface TX/RX
+ MEDIA_MED2INT(0) => med2int(4),
+ MEDIA_MED2INT(1) => med2int(5),
+ MEDIA_MED2INT(2) => med2int(6),
+ MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1),
+ MEDIA_INT2MED(0) => int2med(4),
+ MEDIA_INT2MED(1) => int2med(5),
+ MEDIA_INT2MED(2) => int2med(6),
+ MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1),
+ -- komma operation
+-- RX_DLM_OUT => open, --: out std_logic_vector(3 downto 0); -- DLM received, one clock cycle active
+ RX_DLM_OUT(0) => open,
+ RX_DLM_OUT(1) => open,
+ RX_DLM_OUT(2) => open,
+ RX_DLM_OUT(3) => rx_dlm_i,
+ RX_DLM_WORD_OUT => open, --: out std_logic_vector(4*8-1 downto 0); -- DLM data byte, registered
+ TX_DLM_IN => rx_dlm_i, --'0', --: in std_logic;
+ TX_DLM_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
+ RX_RST_OUT => open, --: out std_logic; -- RST received, one clock cycle active
+ RX_RST_WORD_OUT => open, --: out std_logic_vector(7 downto 0); -- RST data byte, registered
+ TX_RST_IN => '0', --: in std_logic;
+ TX_RST_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
+ -- sync operation
+ WORD_SYNC_IN => word_sync_i,
+ WORD_SYNC_OUT => word_sync_i,
+ MASTER_CLK_IN => master_clk_i,
+ MASTER_CLK_OUT => master_clk_i,
+ GLOBAL_RESET_IN => '0',
+ GLOBAL_RESET_OUT => master_reset_i,
+ TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
+ TX_CLK_AVAIL_OUT => tx_clk_avail_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ SYNC_TX_PLL_IN => sync_tx_quad_i,
+ LINK_TX_READY_IN => link_tx_ready_i,
+ DESTROY_LINK_IN => x"0", -- BUG
--SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(5),
SD_PRSNT_N_IN(1) => HUB_MOD0(6),
SD_PRSNT_N_IN(2) => HUB_MOD0(7),
SD_PRSNT_N_IN(3) => SFP_MOD0(1),
-
- SD_LOS_IN(0) => HUB_LOS(5),
- SD_LOS_IN(1) => HUB_LOS(6),
- SD_LOS_IN(2) => HUB_LOS(7),
- SD_LOS_IN(3) => SFP_LOS(1),
-
- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
-
+ SD_LOS_IN(0) => HUB_LOS(5),
+ SD_LOS_IN(1) => HUB_LOS(6),
+ SD_LOS_IN(2) => HUB_LOS(7),
+ SD_LOS_IN(3) => SFP_LOS(1),
+ SD_TXDIS_OUT(0) => HUB_TXDIS(5),
+ SD_TXDIS_OUT(1) => HUB_TXDIS(6),
+ SD_TXDIS_OUT(2) => HUB_TXDIS(7),
+ SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
--Control Interface
BUS_RX => bussci2_rx,
BUS_TX => bussci2_tx,
-
-- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
- CTRL_DEBUG => open
- );
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open,
+ DEBUG_OUT => debug_i
+ );
end generate;
+ tx_pll_lol_qd_a_i <= '0'; -- BUG
+
+ THE_MAIN_TX_RST: main_tx_reset_RS
+ generic map(
+ SIM_MODE => 0
+ )
+ port map (
+ CLEAR => '0',
+ LOCALCLK => clk_full_osc,
+ TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i,
+ TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i,
+ TX_PLL_LOL_QD_C_IN => tx_pll_lol_qd_c_i,
+ TX_PLL_LOL_QD_D_IN => tx_pll_lol_qd_d_i,
+ TX_PLL_LOL_OUT => tx_pll_lol_all_i,
+ TX_CLOCK_AVAIL_IN => tx_clk_avail_i,
+ TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i,
+ SYNC_TX_QUAD_OUT => sync_tx_quad_i,
+ LINK_TX_READY_OUT => link_tx_ready_i,
+ STATE_OUT => tx_reset_state
+ );
+
+ --HDR_IO(10 downto 1) <= (others => '0');
+ --HDR_IO(10) <= debug_i(17);
+ --HDR_IO(9) <= debug_i(16);
+ --HDR_IO(8) <= '0';
+ --HDR_IO(7) <= '0';
+ --HDR_IO(6) <= '0';
+ --HDR_IO(5) <= '0';
+ --HDR_IO(4) <= '0';
+ --HDR_IO(3) <= '0';
+ --HDR_IO(2) <= rx_dlm_i;
+ --HDR_IO(1) <= '0';
+
+-- TEST_LINE(11 downto 0) <= debug_i(11 downto 0);
+-- TEST_LINE(15 downto 12) <= debug_i(19 downto 16);
+-- TEST_LINE(15 downto 12) <= tx_reset_state;
+
+-- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4_slave3
+-- generic map(
+-- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_YES),
+-- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
+-- )
+-- port map(
+-- CLK_REF_FULL => clk_full_osc,
+-- CLK_INTERNAL_FULL => clk_full_osc,
+-- SYSCLK => clk_sys,
+-- RESET => reset_i,
+-- CLEAR => clear_i,
+-- --Internal Connection
+-- MEDIA_MED2INT(0) => med2int(4),
+-- MEDIA_MED2INT(1) => med2int(5),
+-- MEDIA_MED2INT(2) => med2int(6),
+-- MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1),
+-- MEDIA_INT2MED(0) => int2med(4),
+-- MEDIA_INT2MED(1) => int2med(5),
+-- MEDIA_INT2MED(2) => int2med(6),
+-- MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1),
+-- --Sync operation
+-- RX_DLM => open,
+-- RX_DLM_WORD => open,
+-- TX_DLM => open,
+-- TX_DLM_WORD => open,
+-- --SFP Connection
+-- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
+-- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
+-- SD_PRSNT_N_IN(2) => HUB_MOD0(7),
+-- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
+-- SD_LOS_IN(0) => HUB_LOS(5),
+-- SD_LOS_IN(1) => HUB_LOS(6),
+-- SD_LOS_IN(2) => HUB_LOS(7),
+-- SD_LOS_IN(3) => SFP_LOS(1),
+-- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
+-- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
+-- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
+-- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
+-- --Control Interface
+-- BUS_RX => bussci2_rx,
+-- BUS_TX => bussci2_tx,
+-- -- Status and control port
+-- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+-- CTRL_DEBUG => open
+-- );
+
---------------------------------------------------------------------------
-- PCSC 4 downlinks
---------------------------------------------------------------------------
- THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_4
+ THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_RS
generic map(
- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
- )
+ SERDES_NUM => 3,
+ SIM_MODE => 0,
+ IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER),
+ IS_WAP_ZERO => 1
+ )
port map(
+ -- Clocks and reset
CLK_REF_FULL => clk_full_osc,
- CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
CLEAR => clear_i,
-
- --Internal Connection
+ -- Media Interface TX/RX
MEDIA_MED2INT(0) => med2int(2),
MEDIA_MED2INT(1) => med2int(3),
MEDIA_MED2INT(2) => med2int(0),
MEDIA_INT2MED(1) => int2med(3),
MEDIA_INT2MED(2) => int2med(0),
MEDIA_INT2MED(3) => int2med(1),
-
- --Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
+ -- komma operation
+ RX_DLM_OUT => open, --: out std_logic_vector(3 downto 0); -- DLM received, one clock cycle active
+ RX_DLM_WORD_OUT => open, --: out std_logic_vector(4*8-1 downto 0); -- DLM data byte, registered
+ TX_DLM_IN => rx_dlm_i, --'0', --: in std_logic;
+ TX_DLM_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
+ RX_RST_OUT => open, --: out std_logic; -- RST received, one clock cycle active
+ RX_RST_WORD_OUT => open, --: out std_logic_vector(7 downto 0); -- RST data byte, registered
+ TX_RST_IN => '0', --: in std_logic;
+ TX_RST_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
+ -- sync operation
+ WORD_SYNC_IN => word_sync_i,
+ WORD_SYNC_OUT => open,
+ MASTER_CLK_IN => master_clk_i,
+ MASTER_CLK_OUT => open,
+ GLOBAL_RESET_IN => '0',
+ GLOBAL_RESET_OUT => master_reset_i,
+ TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ TX_PLL_LOL_OUT => tx_pll_lol_qd_c_i,
+ TX_CLK_AVAIL_OUT => tx_clk_avail_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ SYNC_TX_PLL_IN => sync_tx_quad_i,
+ LINK_TX_READY_IN => link_tx_ready_i,
+ DESTROY_LINK_IN => x"0", -- BUG
--SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(3),
SD_PRSNT_N_IN(1) => HUB_MOD0(4),
SD_PRSNT_N_IN(2) => HUB_MOD0(1),
SD_PRSNT_N_IN(3) => HUB_MOD0(2),
-
- SD_LOS_IN(0) => HUB_LOS(3),
- SD_LOS_IN(1) => HUB_LOS(4),
- SD_LOS_IN(2) => HUB_LOS(1),
- SD_LOS_IN(3) => HUB_LOS(2),
-
- SD_TXDIS_OUT(0) => HUB_TXDIS(3),
- SD_TXDIS_OUT(1) => HUB_TXDIS(4),
- SD_TXDIS_OUT(2) => HUB_TXDIS(1),
- SD_TXDIS_OUT(3) => HUB_TXDIS(2),
-
+ SD_LOS_IN(0) => HUB_LOS(3),
+ SD_LOS_IN(1) => HUB_LOS(4),
+ SD_LOS_IN(2) => HUB_LOS(1),
+ SD_LOS_IN(3) => HUB_LOS(2),
+ SD_TXDIS_OUT(0) => HUB_TXDIS(3),
+ SD_TXDIS_OUT(1) => HUB_TXDIS(4),
+ SD_TXDIS_OUT(2) => HUB_TXDIS(1),
+ SD_TXDIS_OUT(3) => HUB_TXDIS(2),
--Control Interface
BUS_RX => bussci3_rx,
BUS_TX => bussci3_tx,
-
-- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
- CTRL_DEBUG => open
- );
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open,
+ DEBUG_OUT => open
+ );
+
+-- THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_4
+-- generic map(
+-- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+-- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
+-- )
+-- port map(
+-- CLK_REF_FULL => clk_full_osc,
+-- CLK_INTERNAL_FULL => clk_full_osc,
+-- SYSCLK => clk_sys,
+-- RESET => reset_i,
+-- CLEAR => clear_i,
+-- --Internal Connection
+-- MEDIA_MED2INT(0) => med2int(2),
+-- MEDIA_MED2INT(1) => med2int(3),
+-- MEDIA_MED2INT(2) => med2int(0),
+-- MEDIA_MED2INT(3) => med2int(1),
+-- MEDIA_INT2MED(0) => int2med(2),
+-- MEDIA_INT2MED(1) => int2med(3),
+-- MEDIA_INT2MED(2) => int2med(0),
+-- MEDIA_INT2MED(3) => int2med(1),
+-- --Sync operation
+-- RX_DLM => open,
+-- RX_DLM_WORD => open,
+-- TX_DLM => open,
+-- TX_DLM_WORD => open,
+-- --SFP Connection
+-- SD_PRSNT_N_IN(0) => HUB_MOD0(3),
+-- SD_PRSNT_N_IN(1) => HUB_MOD0(4),
+-- SD_PRSNT_N_IN(2) => HUB_MOD0(1),
+-- SD_PRSNT_N_IN(3) => HUB_MOD0(2),
+-- SD_LOS_IN(0) => HUB_LOS(3),
+-- SD_LOS_IN(1) => HUB_LOS(4),
+-- SD_LOS_IN(2) => HUB_LOS(1),
+-- SD_LOS_IN(3) => HUB_LOS(2),
+-- SD_TXDIS_OUT(0) => HUB_TXDIS(3),
+-- SD_TXDIS_OUT(1) => HUB_TXDIS(4),
+-- SD_TXDIS_OUT(2) => HUB_TXDIS(1),
+-- SD_TXDIS_OUT(3) => HUB_TXDIS(2),
+-- --Control Interface
+-- BUS_RX => bussci3_rx,
+-- BUS_TX => bussci3_tx,
+-- -- Status and control port
+-- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+-- CTRL_DEBUG => open
+-- );
---------------------------------------------------------------------------
-- PCSD GBE or 2 downlinks
---------------------------------------------------------------------------
gen_PCSD : if INCLUDE_GBE = c_NO generate
- THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_4
- generic map(
- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
- IS_USED => (c_YES,c_YES ,c_NO ,c_NO)
+ THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_RS
+ generic map(
+ SERDES_NUM => 3,
+ SIM_MODE => 0,
+ IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_UNUSED, c_IS_UNUSED),
+ IS_WAP_ZERO => 1
)
- port map(
- CLK_REF_FULL => clk_full_osc,
- CLK_INTERNAL_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear_i,
-
- --Internal Connection
- MEDIA_MED2INT(0) => med2int(8),
- MEDIA_MED2INT(1) => med2int(7),
- MEDIA_INT2MED(0) => int2med(8),
- MEDIA_INT2MED(1) => int2med(7),
-
- --Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
- --SFP Connection
- SD_PRSNT_N_IN(0) => SFP_MOD0(0),
- SD_PRSNT_N_IN(1) => HUB_MOD0(8),
-
- SD_LOS_IN(0) => SFP_LOS(0),
- SD_LOS_IN(1) => HUB_LOS(8),
-
- SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
- SD_TXDIS_OUT(1) => HUB_TXDIS(8),
-
- --Control Interface
- BUS_RX => bussci4_rx,
- BUS_TX => bussci4_tx,
-
- -- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
- CTRL_DEBUG => open
- );
+ port map(
+ -- Clocks and reset
+ CLK_REF_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ -- Media Interface TX/RX
+ MEDIA_MED2INT(0) => med2int(8),
+ MEDIA_MED2INT(1) => med2int(7),
+ MEDIA_MED2INT(2) => open,
+ MEDIA_MED2INT(3) => open,
+ MEDIA_INT2MED(0) => int2med(8),
+ MEDIA_INT2MED(1) => int2med(7),
+ MEDIA_INT2MED(2) => open,
+ MEDIA_INT2MED(3) => open,
+ -- komma operation
+ RX_DLM_OUT => open, --: out std_logic_vector(3 downto 0); -- DLM received, one clock cycle active
+ RX_DLM_WORD_OUT => open, --: out std_logic_vector(4*8-1 downto 0); -- DLM data byte, registered
+ TX_DLM_IN => rx_dlm_i, --'0', --: in std_logic;
+ TX_DLM_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
+ RX_RST_OUT => open, --: out std_logic; -- RST received, one clock cycle active
+ RX_RST_WORD_OUT => open, --: out std_logic_vector(7 downto 0); -- RST data byte, registered
+ TX_RST_IN => '0', --: in std_logic;
+ TX_RST_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
+ -- sync operation
+ WORD_SYNC_IN => word_sync_i,
+ WORD_SYNC_OUT => open,
+ MASTER_CLK_IN => master_clk_i,
+ MASTER_CLK_OUT => open,
+ GLOBAL_RESET_IN => '0',
+ GLOBAL_RESET_OUT => master_reset_i,
+ TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ TX_PLL_LOL_OUT => tx_pll_lol_qd_d_i,
+ TX_CLK_AVAIL_OUT => tx_clk_avail_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ SYNC_TX_PLL_IN => sync_tx_quad_i,
+ LINK_TX_READY_IN => link_tx_ready_i,
+ DESTROY_LINK_IN => x"0", -- BUG
+ --SFP Connection
+
+ SD_PRSNT_N_IN(0) => SFP_MOD0(0),
+ SD_PRSNT_N_IN(1) => HUB_MOD0(8),
+ SD_PRSNT_N_IN(2) => '1',
+ SD_PRSNT_N_IN(3) => '1',
+ SD_LOS_IN(0) => SFP_LOS(0),
+ SD_LOS_IN(1) => HUB_LOS(8),
+ SD_LOS_IN(2) => '1',
+ SD_LOS_IN(3) => '1',
+ SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
+ SD_TXDIS_OUT(1) => HUB_TXDIS(8),
+ SD_TXDIS_OUT(2) => open,
+ SD_TXDIS_OUT(3) => open,
+ --Control Interface
+ BUS_RX => bussci4_rx,
+ BUS_TX => bussci4_tx,
+ -- Status and control port
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open,
+ DEBUG_OUT => open
+ );
end generate;
+-- THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_4
+-- generic map(
+-- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+-- IS_USED => (c_YES,c_YES ,c_NO ,c_NO)
+-- )
+-- port map(
+-- CLK_REF_FULL => clk_full_osc,
+-- CLK_INTERNAL_FULL => clk_full_osc,
+-- SYSCLK => clk_sys,
+-- RESET => reset_i,
+-- CLEAR => clear_i,
+-- --Internal Connection
+-- MEDIA_MED2INT(0) => med2int(8),
+-- MEDIA_MED2INT(1) => med2int(7),
+-- MEDIA_INT2MED(0) => int2med(8),
+-- MEDIA_INT2MED(1) => int2med(7),
+-- --Sync operation
+-- RX_DLM => open,
+-- RX_DLM_WORD => open,
+-- TX_DLM => open,
+-- TX_DLM_WORD => open,
+-- --SFP Connection
+-- SD_PRSNT_N_IN(0) => SFP_MOD0(0),
+-- SD_PRSNT_N_IN(1) => HUB_MOD0(8),
+-- SD_LOS_IN(0) => SFP_LOS(0),
+-- SD_LOS_IN(1) => HUB_LOS(8),
+-- SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
+-- SD_TXDIS_OUT(1) => HUB_TXDIS(8),
+-- --Control Interface
+-- BUS_RX => bussci4_rx,
+-- BUS_TX => bussci4_tx,
+-- -- Status and control port
+-- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+-- CTRL_DEBUG => open
+-- );
+
---------------------------------------------------------------------------
-- GbE
---------------------------------------------------------------------------
SPI_MISO_IN => spi_miso,
SPI_CLK_OUT => spi_clk,
--Header
- HEADER_IO => HDR_IO,
+ HEADER_IO => open, --HDR_IO,
--LCD
LCD_DATA_IN => open,
--ADC
---------------------------------------------------------------------------
--- Switches
+-- Switchesadding signal probes
---------------------------------------------------------------------------
--Serdes Select
PCSSW_ENSMB <= '0';
not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else
'1';
- TEST_LINE(0) <= med2int(INTERFACE_NUM-1).stat_op(13);
- TEST_LINE(1) <= med2int(INTERFACE_NUM-1).stat_op(15);
- TEST_LINE(2) <= clear_i;
- TEST_LINE(3) <= reset_i;
+-- TEST_LINE(0) <= med2int(INTERFACE_NUM-1).stat_op(13);
+-- TEST_LINE(1) <= med2int(INTERFACE_NUM-1).stat_op(15);
+-- TEST_LINE(2) <= clear_i;
+-- TEST_LINE(3) <= reset_i;
-- TEST_LINE(4) <= time_counter(26);
-- TEST_LINE(5) <= BACK_GPIO(1);
-- TEST_LINE(6) <= sfp_txdis_i;
- TEST_LINE(7) <= med2int(INTERFACE_NUM-1).stat_op(9);
+-- TEST_LINE(7) <= med2int(INTERFACE_NUM-1).stat_op(9);
end architecture;
jspc29 / trb3sc.git / commitdiff