--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net_gbe_components.all;
+use work.med_sync_define_RS.all;
+
+entity gbe_med_interface_single is
+ generic(
+ NUMBER_OF_GBE_LINKS : integer range 1 to 4 := 4;
+ LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111"
+ );
+ port(
+ RESET : in std_logic;
+ GSR_N : in std_logic;
+ CLK_SYS_IN : in std_logic;
+ CLK_125_OUT : out std_logic;
+ CLK_125_IN : in std_logic;
+ CLK_125_RX_OUT : out std_logic;
+ -- MAC status and config
+ MAC_READY_CONF_OUT : out std_logic;
+ MAC_RECONF_IN : in std_logic;
+ MAC_AN_READY_OUT : out std_logic;
+ -- MAC data interface
+ MAC_FIFOAVAIL_IN : in std_logic;
+ MAC_FIFOEOF_IN : in std_logic;
+ MAC_FIFOEMPTY_IN : in std_logic;
+ MAC_RX_FIFOFULL_IN : in std_logic;
+ -- MAC TX interface
+ MAC_TX_DATA_IN : in std_logic_vector(7 downto 0);
+ MAC_TX_READ_OUT : out std_logic;
+ MAC_TX_DISCRFRM_OUT : out std_logic;
+ MAC_TX_STAT_EN_OUT : out std_logic;
+ MAC_TX_STATS_OUT : out std_logic_vector(30 downto 0);
+ MAC_TX_DONE_OUT : out std_logic;
+ -- MAC RX interface
+ MAC_RX_FIFO_ERR_OUT : out std_logic;
+ MAC_RX_STATS_OUT : out std_logic_vector(31 downto 0);
+ MAC_RX_DATA_OUT : out std_logic_vector(7 downto 0);
+ MAC_RX_WRITE_OUT : out std_logic;
+ MAC_RX_STAT_EN_OUT : out std_logic;
+ MAC_RX_EOF_OUT : out std_logic;
+ MAC_RX_ERROR_OUT : out std_logic;
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_RXD_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_TXD_P_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_TXD_N_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable
+ -- Debug
+ STATUS_OUT : out std_logic_vector(7 downto 0);
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+ );
+end entity gbe_med_interface_single;
+
+architecture RTL of gbe_med_interface_single is
+
+ component sgmii_gbe_pcs42
+ port(
+ rst_n : in std_logic;
+ signal_detect : in std_logic;
+ gbe_mode : in std_logic;
+ sgmii_mode : in std_logic;
+ operational_rate : in std_logic_vector(1 downto 0);
+ debug_link_timer_short : in std_logic;
+
+ force_isolate : in std_logic;
+ force_loopback : in std_logic;
+ force_unidir : in std_logic;
+
+ rx_compensation_err : out std_logic;
+
+ ctc_drop_flag : out std_logic;
+ ctc_add_flag : out std_logic;
+ an_link_ok : out std_logic;
+
+ tx_clk_125 : in std_logic;
+ tx_clock_enable_source : out std_logic;
+ tx_clock_enable_sink : in std_logic;
+ tx_d : in std_logic_vector(7 downto 0);
+ tx_en : in std_logic;
+ tx_er : in std_logic;
+ rx_clk_125 : in std_logic;
+ rx_clock_enable_source : out std_logic;
+ rx_clock_enable_sink : in std_logic;
+ rx_d : out std_logic_vector(7 downto 0);
+ rx_dv : out std_logic;
+ rx_er : out std_logic;
+ col : out std_logic;
+ crs : out std_logic;
+ tx_data : out std_logic_vector(7 downto 0);
+ tx_kcntl : out std_logic;
+ tx_disparity_cntl : out std_logic;
+
+ xmit_autoneg : out std_logic;
+
+ serdes_recovered_clk : in std_logic;
+ rx_data : in std_logic_vector(7 downto 0);
+ rx_even : in std_logic;
+ rx_kcntl : in std_logic;
+ rx_disp_err : in std_logic;
+ rx_cv_err : in std_logic;
+ rx_err_decode_mode : in std_logic;
+ mr_an_complete : out std_logic;
+ mr_page_rx : out std_logic;
+ mr_lp_adv_ability : out std_logic_vector(15 downto 0);
+ mr_main_reset : in std_logic;
+ mr_an_enable : in std_logic;
+ mr_restart_an : in std_logic;
+ mr_adv_ability : in std_logic_vector(15 downto 0)
+ );
+ end component;
+
+ component tsmac41
+ port(
+ --------------- clock and reset port declarations ------------------
+ hclk : in std_logic;
+ txmac_clk : in std_logic;
+ rxmac_clk : in std_logic;
+ reset_n : in std_logic;
+ ------------------- Input signals to the GMII ----------------
+ rxd : in std_logic_vector(7 downto 0);
+ rx_dv : in std_logic;
+ rx_er : in std_logic;
+ -------------------- Input signals to the CPU I/F -------------------
+ haddr : in std_logic_vector(7 downto 0);
+ hdatain : in std_logic_vector(7 downto 0);
+ hcs_n : in std_logic;
+ hwrite_n : in std_logic;
+ hread_n : in std_logic;
+ ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+ tx_fifodata : in std_logic_vector(7 downto 0);
+ tx_fifoavail : in std_logic;
+ tx_fifoeof : in std_logic;
+ tx_fifoempty : in std_logic;
+ tx_sndpaustim : in std_logic_vector(15 downto 0);
+ tx_sndpausreq : in std_logic;
+ tx_fifoctrl : in std_logic;
+ ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+ rx_fifo_full : in std_logic;
+ ignore_pkt : in std_logic;
+ -------------------- Output signals from the GMII -----------------------
+ txd : out std_logic_vector(7 downto 0);
+ tx_en : out std_logic;
+ tx_er : out std_logic;
+ -------------------- Output signals from the CPU I/F -------------------
+ hdataout : out std_logic_vector(7 downto 0);
+ hdataout_en_n : out std_logic;
+ hready_n : out std_logic;
+ cpu_if_gbit_en : out std_logic;
+ ---------------- Output signals from the Tx MAC FIFO I/F ---------------
+ tx_macread : out std_logic;
+ tx_discfrm : out std_logic;
+ tx_staten : out std_logic;
+ tx_done : out std_logic;
+ tx_statvec : out std_logic_vector(30 downto 0);
+ ---------------- Output signals from the Rx MAC FIFO I/F ---------------
+ rx_fifo_error : out std_logic;
+ rx_stat_vector : out std_logic_vector(31 downto 0);
+ rx_dbout : out std_logic_vector(7 downto 0);
+ rx_write : out std_logic;
+ rx_stat_en : out std_logic;
+ rx_eof : out std_logic;
+ rx_error : out std_logic
+ );
+ end component;
+
+ signal sd_rx_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_tx_kcntl : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_tx_data : std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal xmit : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_tx_correct_disp : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_rx_data : std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_rx_kcntl : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_rx_disp_error : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_rx_cv_error : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal lsm_status : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_clk_en : std_logic;
+ signal tx_clk_en : std_logic;
+ signal operational_rate : std_logic_vector(1 downto 0);
+ signal an_complete : std_logic;
+ signal mr_page_rx : std_logic;
+ signal mr_lp_adv_ability : std_logic_vector(15 downto 0);
+ signal mr_main_reset : std_logic;
+ signal mr_restart_an : std_logic;
+ signal mr_adv_ability : std_logic_vector(15 downto 0);
+ signal mr_an_enable : std_logic;
+ signal an_link_ok : std_logic;
+ signal pcs_rxd : std_logic_vector(7 downto 0);
+ signal pcs_rx_en : std_logic;
+ signal pcs_rx_er : std_logic;
+ signal pcs_txd : std_logic_vector(7 downto 0);
+ signal pcs_tx_en : std_logic;
+ signal pcs_tx_er : std_logic;
+ signal tsm_hdataout_en_n : std_logic;
+ signal tsm_hready_n : std_logic;
+ signal tsm_hread_n : std_logic;
+ signal tsm_hwrite_n : std_logic;
+ signal tsm_hcs_n : std_logic;
+ signal tsm_hdata : std_logic_vector(7 downto 0);
+ signal tsm_haddr : std_logic_vector(7 downto 0);
+
+ signal synced_rst : std_logic;
+
+ signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic;
+
+ signal powerup_ch : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal link_rx_ready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_los_low : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_cdr_lol : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_pcs_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_pcs_rst_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_serdes_rst_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rst_quad : std_logic;
+ signal tx_pcs_rst : std_logic;
+ signal link_tx_ready : std_logic;
+ signal tx_plol_lol : std_logic;
+
+ signal debug : std_logic_vector(63 downto 0);
+
+ -- for replacing register interface
+ signal delay_q : std_logic_vector(7 downto 0);
+ signal pulse : std_logic;
+
+ signal led_timer : unsigned(19 downto 0);
+ signal led_timer_done_x : std_logic;
+ signal led_timer_done : std_logic;
+ signal led_activity_x : std_logic;
+ signal led_activity : std_logic_vector(1 downto 0);
+
+begin
+
+ -- We allow only one GbE in ECP5 for now
+ assert not (LINKS_ACTIVE = b"0000") report "Error: no GbE interface selected" severity error;
+
+ assert ((LINKS_ACTIVE = b"0001") or (LINKS_ACTIVE = b"0010") or (LINKS_ACTIVE = b"0100") or (LINKS_ACTIVE = b"1000"))
+ report "Error: only one GbE interface allowed" severity error;
+
+ --------------------------------------------------------------------
+ --------------------------------------------------------------------
+ DEBUG_OUT <= debug;
+ -- debug(19..0) are on INTCOM
+ -- debug(33..20) are on GPIO
+ -- 33 = CLK2 (white/green)
+ -- 32 = CLK1 (white/blue)
+ --------------------------------------------------------------------
+ --------------------------------------------------------------------
+
+ synced_rst <= GSR_N;
+ rst_quad <= not GSR_N;
+
+ SD_TXDIS_OUT <= (others => '0'); --- BUG
+
+ CLK_125_OUT <= CLK_125_IN;
+
+ gbe_serdes: entity serdes_gbe_4ch_ds
+ port map(
+ -- CH0 --
+ hdinp_ch0 => SD_RXD_P_IN(0),
+ hdinn_ch0 => SD_RXD_N_IN(0),
+ hdoutp_ch0 => SD_TXD_P_OUT(0),
+ hdoutn_ch0 => SD_TXD_N_OUT(0),
+ rxiclk_ch0 => sd_rx_clk(0),
+ txiclk_ch0 => CLK_125_IN,
+ rx_full_clk_ch0 => sd_rx_clk(0),
+ rx_half_clk_ch0 => open,
+ tx_full_clk_ch0 => open,
+ tx_half_clk_ch0 => open,
+ fpga_rxrefclk_ch0 => CLK_125_IN,
+ txdata_ch0 => sd_tx_data(7 downto 0),
+ tx_k_ch0 => sd_tx_kcntl(0),
+ xmit_ch0 => xmit(0),
+ tx_disp_correct_ch0 => sd_tx_correct_disp(0),
+ rxdata_ch0 => sd_rx_data(7 downto 0),
+ rx_k_ch0 => sd_rx_kcntl(0),
+ rx_disp_err_ch0 => sd_rx_disp_error(0),
+ rx_cv_err_ch0 => sd_rx_cv_error(0),
+ rx_serdes_rst_ch0_c => rx_serdes_rst(0),
+ sb_felb_ch0_c => '0',
+ sb_felb_rst_ch0_c => '0',
+ tx_pcs_rst_ch0_c => tx_pcs_rst,
+ tx_pwrup_ch0_c => powerup_ch(0),
+ rx_pcs_rst_ch0_c => rx_pcs_rst(0),
+ rx_pwrup_ch0_c => powerup_ch(0),
+ rx_los_low_ch0_s => rx_los_low(0),
+ lsm_status_ch0_s => lsm_status(0),
+ rx_cdr_lol_ch0_s => rx_cdr_lol(0),
+ -- CH1 --
+ hdinp_ch1 => SD_RXD_P_IN(1),
+ hdinn_ch1 => SD_RXD_N_IN(1),
+ hdoutp_ch1 => SD_TXD_P_OUT(1),
+ hdoutn_ch1 => SD_TXD_N_OUT(1),
+ rxiclk_ch1 => sd_rx_clk(1),
+ txiclk_ch1 => CLK_125_IN,
+ rx_full_clk_ch1 => sd_rx_clk(1),
+ rx_half_clk_ch1 => open,
+ tx_full_clk_ch1 => open,
+ tx_half_clk_ch1 => open,
+ fpga_rxrefclk_ch1 => CLK_125_IN,
+ txdata_ch1 => sd_tx_data(15 downto 8),
+ tx_k_ch1 => sd_tx_kcntl(1),
+ xmit_ch1 => xmit(1),
+ tx_disp_correct_ch1 => sd_tx_correct_disp(1),
+ rxdata_ch1 => sd_rx_data(15 downto 8),
+ rx_k_ch1 => sd_rx_kcntl(1),
+ rx_disp_err_ch1 => sd_rx_disp_error(1),
+ rx_cv_err_ch1 => sd_rx_cv_error(1),
+ rx_serdes_rst_ch1_c => rx_serdes_rst(1),
+ sb_felb_ch1_c => '0',
+ sb_felb_rst_ch1_c => '0',
+ tx_pcs_rst_ch1_c => tx_pcs_rst,
+ tx_pwrup_ch1_c => powerup_ch(1),
+ rx_pcs_rst_ch1_c => rx_pcs_rst(1),
+ rx_pwrup_ch1_c => powerup_ch(1),
+ rx_los_low_ch1_s => rx_los_low(1),
+ lsm_status_ch1_s => lsm_status(1),
+ rx_cdr_lol_ch1_s => rx_cdr_lol(1),
+ -- CH2 --
+ hdinp_ch2 => SD_RXD_P_IN(2),
+ hdinn_ch2 => SD_RXD_N_IN(2),
+ hdoutp_ch2 => SD_TXD_P_OUT(2),
+ hdoutn_ch2 => SD_TXD_N_OUT(2),
+ rxiclk_ch2 => sd_rx_clk(2),
+ txiclk_ch2 => CLK_125_IN,
+ rx_full_clk_ch2 => sd_rx_clk(2),
+ rx_half_clk_ch2 => open,
+ tx_full_clk_ch2 => open,
+ tx_half_clk_ch2 => open,
+ fpga_rxrefclk_ch2 => CLK_125_IN,
+ txdata_ch2 => sd_tx_data(23 downto 16),
+ tx_k_ch2 => sd_tx_kcntl(2),
+ xmit_ch2 => xmit(2),
+ tx_disp_correct_ch2 => sd_tx_correct_disp(2),
+ rxdata_ch2 => sd_rx_data(23 downto 16),
+ rx_k_ch2 => sd_rx_kcntl(2),
+ rx_disp_err_ch2 => sd_rx_disp_error(2),
+ rx_cv_err_ch2 => sd_rx_cv_error(2),
+ rx_serdes_rst_ch2_c => rx_serdes_rst(2),
+ sb_felb_ch2_c => '0',
+ sb_felb_rst_ch2_c => '0',
+ tx_pcs_rst_ch2_c => tx_pcs_rst,
+ tx_pwrup_ch2_c => powerup_ch(2),
+ rx_pcs_rst_ch2_c => rx_pcs_rst(2),
+ rx_pwrup_ch2_c => powerup_ch(2),
+ rx_los_low_ch2_s => rx_los_low(2),
+ lsm_status_ch2_s => lsm_status(2),
+ rx_cdr_lol_ch2_s => rx_cdr_lol(2),
+ -- CH3 --
+ hdinp_ch3 => SD_RXD_P_IN(3),
+ hdinn_ch3 => SD_RXD_N_IN(3),
+ hdoutp_ch3 => SD_TXD_P_OUT(3),
+ hdoutn_ch3 => SD_TXD_N_OUT(3),
+ rxiclk_ch3 => sd_rx_clk(3),
+ txiclk_ch3 => CLK_125_IN,
+ rx_full_clk_ch3 => sd_rx_clk(3),
+ rx_half_clk_ch3 => open,
+ tx_full_clk_ch3 => open,
+ tx_half_clk_ch3 => open,
+ fpga_rxrefclk_ch3 => CLK_125_IN,
+ txdata_ch3 => sd_tx_data(31 downto 24),
+ tx_k_ch3 => sd_tx_kcntl(3),
+ xmit_ch3 => xmit(3),
+ tx_disp_correct_ch3 => sd_tx_correct_disp(3),
+ rxdata_ch3 => sd_rx_data(31 downto 24),
+ rx_k_ch3 => sd_rx_kcntl(3),
+ rx_disp_err_ch3 => sd_rx_disp_error(3),
+ rx_cv_err_ch3 => sd_rx_cv_error(3),
+ rx_serdes_rst_ch3_c => rx_serdes_rst(3),
+ sb_felb_ch3_c => '0',
+ sb_felb_rst_ch3_c => '0',
+ tx_pcs_rst_ch3_c => tx_pcs_rst,
+ tx_pwrup_ch3_c => powerup_ch(3),
+ rx_pcs_rst_ch3_c => rx_pcs_rst(3),
+ rx_pwrup_ch3_c => powerup_ch(3),
+ rx_los_low_ch3_s => rx_los_low(3),
+ lsm_status_ch3_s => lsm_status(3),
+ rx_cdr_lol_ch3_s => rx_cdr_lol(3),
+ ---- Miscallaneous ports
+ fpga_txrefclk => CLK_125_IN,
+ tx_serdes_rst_c => '0',
+ tx_pll_lol_qd_s => tx_plol_lol,
+ rst_qd_c => rst_quad,
+ serdes_rst_qd_c => '0',
+ tx_sync_qd_c => '0'
+ );
+
+ -- RSL for TX of SerDes, based on extRSL logic
+ THE_MAIN_TX_RST: main_tx_reset_RS
+ port map (
+ CLEAR => rst_quad,
+ CLK_REF => CLK_125_IN,
+ TX_PLL_LOL_IN => tx_plol_lol,
+ TX_CLOCK_AVAIL_IN => '1', -- not needed here
+ TX_PCS_RST_CH_C_OUT => tx_pcs_rst,
+ SYNC_TX_QUAD_OUT => open, --not needed here
+ LINK_TX_READY_OUT => link_tx_ready,
+ STATE_OUT => open
+ );
+
+ CHANNEL_GEN : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate
+
+ CHANNEL_ACTIVE_GEN : if LINKS_ACTIVE(i) = '1' generate
+
+ powerup_ch(i) <= '1';
+
+ -- RSL for RX of SerDes, based on extRSL logic
+ -- CAVEAT: reset signals MUST BE sync'ed to recovered RX clock!
+ THE_MAIN_RX_RST: main_rx_reset_RS
+ port map(
+ CLEAR => rst_quad,
+ CLK_REF => CLK_125_IN,
+ CDR_LOL_IN => rx_cdr_lol(i),
+ CV_IN => sd_rx_cv_error(i),
+ LSM_IN => lsm_status(i),
+ LOS_IN => rx_los_low(i),
+ WAP_ZERO_IN => '1', -- not needed here
+ -- outputs
+ WAP_REQ_OUT => open, -- not needed here
+ RX_SERDES_RST_OUT => rx_serdes_rst(i), -- CLK_REF based
+ RX_PCS_RST_OUT => rx_pcs_rst(i), -- CLK_REF based
+ LINK_RX_READY_OUT => link_rx_ready(i), -- CLK_REF based
+ STATE_OUT => open
+ );
+
+ -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
+ SYNC_RST_SIGS: entity work.signal_sync
+ generic map( WIDTH => 2 )
+ port map(
+ RESET => '0',
+ CLK0 => sd_rx_clk(i),
+ CLK1 => sd_rx_clk(i),
+ D_IN(0) => rx_pcs_rst(i),
+ D_IN(1) => rx_serdes_rst(i),
+ D_OUT(0) => rx_pcs_rst_q(i),
+ D_OUT(1) => rx_serdes_rst_q(i)
+ );
+
+ CLK_125_RX_OUT <= sd_rx_clk(i);
+
+ -- SGMII core
+ SGMII_GBE_PCS : sgmii_gbe_pcs42
+ port map(
+ rst_n => synced_rst,
+ signal_detect => link_rx_ready(i),
+ gbe_mode => '1',
+ sgmii_mode => '0',
+ operational_rate => operational_rate,
+ debug_link_timer_short => '0',
+ force_isolate => '0',
+ force_loopback => '0',
+ force_unidir => '0',
+ rx_compensation_err => open,
+ ctc_drop_flag => open,
+ ctc_add_flag => open,
+ an_link_ok => open,
+ -- MAC interface
+ tx_clk_125 => CLK_125_IN,
+ tx_clock_enable_source => tx_clk_en,
+ tx_clock_enable_sink => tx_clk_en,
+ tx_d => pcs_txd, -- TX data from MAC
+ tx_en => pcs_tx_en, -- TX data enable from MAC
+ tx_er => pcs_tx_er, -- TX error from MAC
+ rx_clk_125 => CLK_125_IN,
+ rx_clock_enable_source => rx_clk_en,
+ rx_clock_enable_sink => rx_clk_en,
+ rx_d => pcs_rxd, -- RX data to MAC
+ rx_dv => pcs_rx_en, -- RX data enable to MAC
+ rx_er => pcs_rx_er, -- RX error to MAC
+ col => open,
+ crs => open,
+ -- SerDes interface
+ tx_data => sd_tx_data((i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes
+ tx_kcntl => sd_tx_kcntl(i), -- TX komma control to SerDes
+ tx_disparity_cntl => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes)
+ xmit_autoneg => xmit(i),
+ serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream
+ rx_data => sd_rx_data((i+1) * 8 - 1 downto i * 8), -- RX data from SerDes
+ rx_kcntl => sd_rx_kcntl(i), -- RX komma control from SerDes
+ rx_err_decode_mode => '0', -- receive error control mode fixed to normal
+ rx_even => '0', -- unused (receive error control mode = normal, tie to GND)
+ rx_disp_err => sd_rx_disp_error(i), -- RX disparity error from SerDes
+ rx_cv_err => sd_rx_cv_error(i), -- RX code violation error from SerDes
+ -- Autonegotiation stuff
+ mr_an_complete => an_complete,
+ mr_page_rx => mr_page_rx,
+ mr_lp_adv_ability => mr_lp_adv_ability,
+ mr_main_reset => mr_main_reset,
+ mr_an_enable => mr_an_enable,
+ mr_restart_an => mr_restart_an,
+ mr_adv_ability => mr_adv_ability
+ );
+
+ MAC_AN_READY_OUT <= an_complete;
+
+ --- SIMPLE ---
+ operational_rate <= b"10";
+ --- /SIMPLE ---
+
+ --- SIMPLE ---
+ mr_main_reset <= rst_quad;
+ mr_restart_an <= pulse;
+ mr_an_enable <= link_rx_ready(i);
+ mr_adv_ability <= x"0020";
+
+ SYNC_PROC: process( CLK_125_IN )
+ begin
+ if( rising_edge(CLK_125_IN) ) then
+ delay_q <= delay_q(6 downto 0) & link_rx_ready(i);
+ end if;
+ end process SYNC_PROC;
+
+ pulse <= not delay_q(7) and delay_q(6);
+ --- /SIMPLE ---
+
+ MAC: tsmac41
+ port map(
+ ----------------- clock and reset port declarations ------------------
+ hclk => CLK_SYS_IN,
+ txmac_clk => CLK_125_IN,
+ rxmac_clk => CLK_125_IN,
+ reset_n => synced_rst, -- was GSR_N
+ ------------------- Input signals to the GMII ----------------
+ rxd => pcs_rxd,
+ rx_dv => pcs_rx_en,
+ rx_er => pcs_rx_er,
+ -------------------- Input signals to the CPU I/F -------------------
+ haddr => tsm_haddr,
+ hdatain => tsm_hdata,
+ hcs_n => tsm_hcs_n,
+ hwrite_n => tsm_hwrite_n,
+ hread_n => tsm_hread_n,
+ ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+ tx_fifodata => MAC_TX_DATA_IN,
+ tx_fifoavail => MAC_FIFOAVAIL_IN,
+ tx_fifoeof => MAC_FIFOEOF_IN,
+ tx_fifoempty => MAC_FIFOEMPTY_IN,
+ tx_sndpaustim => x"0000",
+ tx_sndpausreq => '0',
+ tx_fifoctrl => '0', -- always data frame
+ ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+ rx_fifo_full => MAC_RX_FIFOFULL_IN,
+ ignore_pkt => '0',
+ ---------------- Output signals from the GMII -----------------------
+ txd => pcs_txd,
+ tx_en => pcs_tx_en,
+ tx_er => pcs_tx_er,
+ ----------------- Output signals from the CPU I/F -------------------
+ hdataout => open,
+ hdataout_en_n => tsm_hdataout_en_n,
+ hready_n => tsm_hready_n,
+ cpu_if_gbit_en => open,
+ ------------- Output signals from the Tx MAC FIFO I/F ---------------
+ tx_macread => MAC_TX_READ_OUT,
+ tx_discfrm => MAC_TX_DISCRFRM_OUT,
+ tx_staten => MAC_TX_STAT_EN_OUT,
+ tx_statvec => MAC_TX_STATS_OUT,
+ tx_done => MAC_TX_DONE_OUT,
+ ------------- Output signals from the Rx MAC FIFO I/F ---------------
+ rx_fifo_error => MAC_RX_FIFO_ERR_OUT,
+ rx_stat_vector => MAC_RX_STATS_OUT,
+ rx_dbout => MAC_RX_DATA_OUT,
+ rx_write => MAC_RX_WRITE_OUT,
+ rx_stat_en => MAC_RX_STAT_EN_OUT,
+ rx_eof => MAC_RX_EOF_OUT,
+ rx_error => MAC_RX_ERROR_OUT
+ );
+
+ TSMAC_CONTROLLER : trb_net16_gbe_mac_control
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => RESET,
+ -- signals to/from main controller
+ MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT,
+ MC_RECONF_IN => MAC_RECONF_IN,
+ MC_GBE_EN_IN => '1',
+ MC_RX_DISCARD_FCS => '0',
+ MC_PROMISC_IN => '1',
+ MC_MAC_ADDR_IN => (others => '0'),
+ -- signal to/from Host interface of TriSpeed MAC
+ TSM_HADDR_OUT => tsm_haddr,
+ TSM_HDATA_OUT => tsm_hdata,
+ TSM_HCS_N_OUT => tsm_hcs_n,
+ TSM_HWRITE_N_OUT => tsm_hwrite_n,
+ TSM_HREAD_N_OUT => tsm_hread_n,
+ TSM_HREADY_N_IN => tsm_hready_n,
+ TSM_HDATA_EN_N_IN => tsm_hdataout_en_n,
+ -- Debug
+ DEBUG_OUT => open
+ );
+
+ -- Status signals
+ STATUS_OUT(7) <= '0';
+ STATUS_OUT(6) <= '0';
+ STATUS_OUT(5) <= led_activity(1); -- long LED signal for activity
+ STATUS_OUT(4) <= pcs_rx_en; -- SerDes RX activity
+ STATUS_OUT(3) <= pcs_tx_en; -- SerDes TX activity
+ STATUS_OUT(2) <= an_complete; -- GbE Autonegotiation completed
+ STATUS_OUT(1) <= link_rx_ready(i); -- SerDes Rx channel operational
+ STATUS_OUT(0) <= link_tx_ready; -- SerDes TX channel operational
+
+ end generate CHANNEL_ACTIVE_GEN;
+
+ CHANNEL_INACTIVE_GEN : if LINKS_ACTIVE(i) = '0' generate
+
+ powerup_ch(i) <= '0';
+ rx_pcs_rst_q(i) <= '1';
+ rx_serdes_rst_q(i) <= '1';
+
+ end generate CHANNEL_INACTIVE_GEN;
+
+ end generate CHANNEL_GEN;
+
+ THE_LED_TIMER_PROC: process( CLK_125_IN )
+ begin
+ if( rising_edge(CLK_125_IN) ) then
+ led_timer_done <= led_timer_done_x;
+ led_timer <= led_timer + 1;
+ end if;
+ end process THE_LED_TIMER_PROC;
+
+ led_timer_done_x <= '1' when (std_logic_vector(led_timer) = x"fffff") else '0';
+
+ led_activity_x <= pcs_rx_en or pcs_tx_en;
+
+ THE_LED_ACT_PROC: process( CLK_125_IN )
+ begin
+ if( rising_edge(CLK_125_IN) ) then
+ if( led_activity_x = '1' ) then
+ led_activity(0) <= '1';
+ end if;
+ if( led_timer_done = '1' ) then
+ led_activity <= led_activity(0) & '0';
+ end if;
+ end if;
+ end process THE_LED_ACT_PROC;
+
+end architecture RTL;
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_ARITH.all;
+use IEEE.std_logic_UNSIGNED.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+use work.trb_net_gbe_components.all;
+use work.trb_net_gbe_protocols.all;
+
+
+entity gbe_wrapper_single is
+ generic(
+ DO_SIMULATION : integer range 0 to 1 := 0;
+ INCLUDE_DEBUG : integer range 0 to 1 := 0;
+ USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; -- only for debugging
+ USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; -- only for debugging
+ RX_PATH_ENABLE : integer range 0 to 1 := 1; --
+ FIXED_SIZE_MODE : integer range 0 to 1 := 1; -- only for debugging
+ INCREMENTAL_MODE : integer range 0 to 1 := 0; -- only for debugging
+ FIXED_SIZE : integer range 0 to 65535 := 10; -- only for debugging
+ FIXED_DELAY_MODE : integer range 0 to 1 := 1; -- only for debugging
+ UP_DOWN_MODE : integer range 0 to 1 := 0; -- only for debugging
+ UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; -- only for debugging
+ FIXED_DELAY : integer range 0 to 16777215 := 16777215; -- only for debugging
+ NUMBER_OF_GBE_LINKS : integer range 1 to 4 := 4;
+ LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_PING : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_ARP : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_DHCP : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_READOUT : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_SLOWCTRL : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_FWD : std_logic_vector(3 downto 0) := "1111"
+ );
+ port(
+ CLK_SYS_IN : in std_logic;
+ CLK_125_IN : in std_logic;
+ RESET : in std_logic;
+ GSR_N : in std_logic;
+ SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable
+ --
+ TRIGGER_IN : in std_logic; -- for debug purpose only
+ -- CTS interface
+ CTS_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ CTS_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ CTS_INFORMATION_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0');
+ CTS_START_READOUT_IN : in std_logic := '0';
+ CTS_DATA_OUT : out std_logic_vector(31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic;
+ CTS_READ_IN : in std_logic := '0';
+ CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ -- Data payload interface
+ FEE_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ FEE_DATAREADY_IN : in std_logic := '0';
+ FEE_READ_OUT : out std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ FEE_BUSY_IN : in std_logic := '0';
+ -- SlowControl
+ MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
+ ISSUE_REBOOT_OUT : out std_logic;
+ MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+ -- IP configuration
+ BUS_IP_RX : in CTRLBUS_RX;
+ BUS_IP_TX : out CTRLBUS_TX;
+ -- Registers config
+ BUS_REG_RX : in CTRLBUS_RX;
+ BUS_REG_TX : out CTRLBUS_TX;
+ -- Forwarder
+ FWD_DST_MAC_IN : in std_logic_vector(48 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_DST_IP_IN : in std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_DST_UDP_IN : in std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0) := (others => '0');
+ FWD_DATA_VALID_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_SOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_EOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ FWD_FULL_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ --
+ MAKE_RESET_OUT : out std_logic;
+ --
+ STATUS_OUT : out std_logic_vector(15 downto 0);
+ DEBUG_OUT : out std_logic_vector(127 downto 0)
+ );
+end entity gbe_wrapper_single;
+
+architecture RTL of gbe_wrapper_single is
+ signal mac_ready_conf : std_logic;
+ signal mac_reconf : std_logic;
+ signal mac_an_ready : std_logic;
+ signal mac_fifoavail : std_logic;
+ signal mac_fifoeof : std_logic;
+ signal mac_fifoempty : std_logic;
+ signal mac_rx_fifofull : std_logic;
+ signal mac_tx_data : std_logic_vector(7 downto 0);
+ signal mac_tx_read : std_logic;
+ signal mac_tx_discrfrm : std_logic;
+ signal mac_tx_stat_en : std_logic;
+ signal mac_tx_stats : std_logic_vector(30 downto 0);
+ signal mac_tx_done : std_logic;
+ signal mac_rx_fifo_err : std_logic;
+ signal mac_rx_stats : std_logic_vector(31 downto 0);
+ signal mac_rx_data : std_logic_vector(7 downto 0);
+ signal mac_rx_write : std_logic;
+ signal mac_rx_stat_en : std_logic;
+ signal mac_rx_eof : std_logic;
+ signal mac_rx_err : std_logic;
+
+ signal cfg_gbe_enable : std_logic;
+ signal cfg_ipu_enable : std_logic;
+ signal cfg_mult_enable : std_logic;
+ signal cfg_subevent_id : std_logic_vector(31 downto 0);
+ signal cfg_subevent_dec : std_logic_vector(31 downto 0);
+ signal cfg_queue_dec : std_logic_vector(31 downto 0);
+ signal cfg_readout_ctr : std_logic_vector(23 downto 0);
+ signal cfg_readout_ctr_valid : std_logic;
+ signal cfg_insert_ttype : std_logic;
+ signal cfg_max_sub : std_logic_vector(15 downto 0);
+ signal cfg_max_queue : std_logic_vector(15 downto 0);
+ signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0);
+ signal cfg_max_single_sub : std_logic_vector(15 downto 0);
+ signal cfg_additional_hdr : std_logic;
+ signal cfg_soft_rst : std_logic;
+ signal cfg_allow_rx : std_logic;
+ signal cfg_max_frame : std_logic_vector(15 downto 0);
+
+ signal dbg_hist, dbg_hist2 : hist_array;
+
+ signal mac_0 : std_logic_vector(47 downto 0);
+ signal cfg_max_reply : std_logic_vector(31 downto 0);
+
+ signal mlt_cts_number : std_logic_vector(15 downto 0);
+ signal mlt_cts_code : std_logic_vector(7 downto 0);
+ signal mlt_cts_information : std_logic_vector(7 downto 0);
+ signal mlt_cts_readout_type : std_logic_vector(3 downto 0);
+ signal mlt_cts_start_readout : std_logic_vector(0 downto 0);
+ signal mlt_cts_data : std_logic_vector(31 downto 0);
+ signal mlt_cts_dataready : std_logic_vector(0 downto 0);
+ signal mlt_cts_readout_finished : std_logic_vector(0 downto 0);
+ signal mlt_cts_read : std_logic_vector(0 downto 0);
+ signal mlt_cts_length : std_logic_vector(15 downto 0);
+ signal mlt_cts_error_pattern : std_logic_vector(31 downto 0);
+ signal mlt_fee_data : std_logic_vector(15 downto 0);
+ signal mlt_fee_dataready : std_logic_vector(0 downto 0);
+ signal mlt_fee_read : std_logic_vector(0 downto 0);
+ signal mlt_fee_status : std_logic_vector(31 downto 0);
+ signal mlt_fee_busy : std_logic_vector(0 downto 0);
+
+ signal mlt_gsc_clk : std_logic;
+ signal mlt_gsc_init_dataready : std_logic;
+ signal mlt_gsc_init_data : std_logic_vector(15 downto 0);
+ signal mlt_gsc_init_packet : std_logic_vector(2 downto 0);
+ signal mlt_gsc_init_read : std_logic;
+ signal mlt_gsc_reply_dataready : std_logic;
+ signal mlt_gsc_reply_data : std_logic_vector(15 downto 0);
+ signal mlt_gsc_reply_packet : std_logic_vector(2 downto 0);
+ signal mlt_gsc_reply_read : std_logic;
+ signal mlt_gsc_busy : std_logic;
+
+ signal local_cts_number : std_logic_vector(15 downto 0);
+ signal local_cts_code : std_logic_vector(7 downto 0);
+ signal local_cts_information : std_logic_vector(7 downto 0);
+ signal local_cts_readout_type : std_logic_vector(3 downto 0);
+ signal local_cts_start_readout : std_logic;
+ signal local_cts_readout_finished : std_logic;
+ signal local_cts_status_bits : std_logic_vector(31 downto 0);
+ signal local_fee_data : std_logic_vector(15 downto 0);
+ signal local_fee_dataready : std_logic;
+ signal local_fee_read : std_logic;
+ signal local_fee_status_bits : std_logic_vector(31 downto 0);
+ signal local_fee_busy : std_logic;
+ signal dhcp_done : std_logic;
+ signal all_links_ready : std_logic;
+ signal monitor_rx_frames : std_logic_vector(31 downto 0);
+ signal monitor_rx_bytes : std_logic_vector(31 downto 0);
+ signal monitor_tx_frames : std_logic_vector(31 downto 0);
+ signal monitor_tx_bytes : std_logic_vector(31 downto 0);
+ signal monitor_tx_packets : std_logic_vector(31 downto 0);
+ signal monitor_dropped : std_logic_vector(31 downto 0);
+ signal sum_rx_frames : std_logic_vector(31 downto 0);
+ signal sum_rx_bytes : std_logic_vector(31 downto 0);
+ signal sum_tx_frames : std_logic_vector(31 downto 0);
+ signal sum_tx_bytes : std_logic_vector(31 downto 0);
+ signal sum_tx_packets : std_logic_vector(31 downto 0);
+ signal sum_dropped : std_logic_vector(31 downto 0);
+
+ signal busip0 : CTRLBUS_TX;
+ signal SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ --attribute nopad : string;
+ --attribute nopad of SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : signal is "true";
+
+ signal dummy_event : std_logic_vector(15 downto 0);
+ signal dummy_mode : std_logic;
+ signal make_reset0 : std_logic := '0';
+ signal monitor_gen_dbg : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
+
+ signal cfg_autothrottle : std_logic;
+ signal cfg_throttle_pause : std_logic_vector(15 downto 0);
+
+ signal issue_reboot : std_logic;
+ signal my_ip : std_logic_vector(127 downto 0);
+ signal debug : std_logic_vector(127 downto 0);
+
+begin
+
+-- assert hits if condition in brackets is true, or overall condition is false
+ assert not (LINKS_ACTIVE = b"0000") report "Error: no GbE interface selected" severity error;
+
+ assert ((LINKS_ACTIVE = b"0001") or (LINKS_ACTIVE = b"0010") or (LINKS_ACTIVE = b"0100") or (LINKS_ACTIVE = b"1000"))
+ report "Error: only one GbE interface allowed" severity error;
+
+ -- debug(127 downto 64) are local
+ -- debug(63 downto 0) are media interface
+ DEBUG_OUT <= debug;
+
+ mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
+
+ all_links_ready <= '1' when dhcp_done = '1' else '0';
+
+ MAKE_RESET_OUT <= '1' when make_reset0 = '1' else '0';
+
+ ISSUE_REBOOT_OUT <= '0' when issue_reboot = '0' else '1';
+
+ physical : entity work.gbe_med_interface_single
+ generic map(
+ NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS,
+ LINKS_ACTIVE => LINKS_ACTIVE
+ )
+ port map(
+ RESET => RESET,
+ GSR_N => GSR_N,
+ CLK_SYS_IN => CLK_SYS_IN,
+ CLK_125_OUT => open, -- not needed
+ CLK_125_IN => CLK_125_IN,
+ CLK_125_RX_OUT => open, -- not needed
+ MAC_READY_CONF_OUT => mac_ready_conf,
+ MAC_RECONF_IN => mac_reconf,
+ MAC_AN_READY_OUT => mac_an_ready,
+ MAC_FIFOAVAIL_IN => mac_fifoavail,
+ MAC_FIFOEOF_IN => mac_fifoeof,
+ MAC_FIFOEMPTY_IN => mac_fifoempty,
+ MAC_RX_FIFOFULL_IN => mac_rx_fifofull,
+ MAC_TX_DATA_IN => mac_tx_data,
+ MAC_TX_READ_OUT => mac_tx_read,
+ MAC_TX_DISCRFRM_OUT => mac_tx_discrfrm,
+ MAC_TX_STAT_EN_OUT => mac_tx_stat_en,
+ MAC_TX_STATS_OUT => mac_tx_stats,
+ MAC_TX_DONE_OUT => mac_tx_done,
+ MAC_RX_FIFO_ERR_OUT => mac_rx_fifo_err,
+ MAC_RX_STATS_OUT => mac_rx_stats,
+ MAC_RX_DATA_OUT => mac_rx_data,
+ MAC_RX_WRITE_OUT => mac_rx_write,
+ MAC_RX_STAT_EN_OUT => mac_rx_stat_en,
+ MAC_RX_EOF_OUT => mac_rx_eof,
+ MAC_RX_ERROR_OUT => mac_rx_err,
+ SD_RXD_P_IN => SD_RXD_P_IN,
+ SD_RXD_N_IN => SD_RXD_N_IN,
+ SD_TXD_P_OUT => SD_TXD_P_OUT,
+ SD_TXD_N_OUT => SD_TXD_N_OUT,
+ SD_PRSNT_N_IN => SD_PRSNT_N_IN,
+ SD_LOS_IN => SD_LOS_IN,
+ SD_TXDIS_OUT => SD_TXDIS_OUT,
+ STATUS_OUT => STATUS_OUT(7 downto 0),
+ DEBUG_OUT => debug(63 downto 0) --open
+ );
+
+ STATUS_OUT(8) <= dhcp_done; -- DHCP has completed
+ STATUS_OUT(15 downto 9) <= (others => '0');
+
+ gbe_inst : entity work.gbe_logic_wrapper
+ generic map(DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
+ RX_PATH_ENABLE => RX_PATH_ENABLE,
+ INCLUDE_READOUT => LINK_HAS_READOUT(0),
+ INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(0),
+ INCLUDE_DHCP => LINK_HAS_DHCP(0),
+ INCLUDE_ARP => LINK_HAS_ARP(0),
+ INCLUDE_PING => LINK_HAS_PING(0),
+ INCLUDE_FWD => LINK_HAS_FWD(0),
+ FRAME_BUFFER_SIZE => 1,
+ READOUT_BUFFER_SIZE => 4,
+ SLOWCTRL_BUFFER_SIZE => 2,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY => FIXED_DELAY)
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ CLK_125_IN => CLK_125_IN,
+ CLK_RX_125_IN => CLK_125_IN,
+ RESET => RESET,
+ GSR_N => GSR_N,
+ MY_MAC_IN => mac_0,
+ DHCP_DONE_OUT => dhcp_done,
+ MY_IP_OUT => my_ip(31 downto 0),
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => issue_reboot,
+ MAC_READY_CONF_IN => mac_ready_conf,
+ MAC_RECONF_OUT => mac_reconf,
+ MAC_AN_READY_IN => mac_an_ready,
+ MAC_FIFOAVAIL_OUT => mac_fifoavail,
+ MAC_FIFOEOF_OUT => mac_fifoeof,
+ MAC_FIFOEMPTY_OUT => mac_fifoempty,
+ MAC_RX_FIFOFULL_OUT => mac_rx_fifofull,
+ MAC_TX_DATA_OUT => mac_tx_data,
+ MAC_TX_READ_IN => mac_tx_read,
+ MAC_TX_DISCRFRM_IN => mac_tx_discrfrm,
+ MAC_TX_STAT_EN_IN => mac_tx_stat_en,
+ MAC_TX_STATS_IN => mac_tx_stats,
+ MAC_TX_DONE_IN => mac_tx_done,
+ MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err,
+ MAC_RX_STATS_IN => mac_rx_stats,
+ MAC_RX_DATA_IN => mac_rx_data,
+ MAC_RX_WRITE_IN => mac_rx_write,
+ MAC_RX_STAT_EN_IN => mac_rx_stat_en,
+ MAC_RX_EOF_IN => mac_rx_eof,
+ MAC_RX_ERROR_IN => mac_rx_err,
+ CTS_NUMBER_IN => mlt_cts_number,
+ CTS_CODE_IN => mlt_cts_code,
+ CTS_INFORMATION_IN => mlt_cts_information,
+ CTS_READOUT_TYPE_IN => mlt_cts_readout_type,
+ CTS_START_READOUT_IN => mlt_cts_start_readout(0),
+ CTS_DATA_OUT => mlt_cts_data,
+ CTS_DATAREADY_OUT => mlt_cts_dataready(0),
+ CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0),
+ CTS_READ_IN => mlt_cts_read(0),
+ CTS_LENGTH_OUT => mlt_cts_length,
+ CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern,
+ FEE_DATA_IN => mlt_fee_data,
+ FEE_DATAREADY_IN => mlt_fee_dataready(0),
+ FEE_READ_OUT => mlt_fee_read(0),
+ FEE_STATUS_BITS_IN => mlt_fee_status,
+ FEE_BUSY_IN => mlt_fee_busy(0),
+ GSC_CLK_IN => mlt_gsc_clk,
+ GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready,
+ GSC_INIT_DATA_OUT => mlt_gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet,
+ GSC_INIT_READ_IN => mlt_gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => mlt_gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet,
+ GSC_REPLY_READ_OUT => mlt_gsc_reply_read,
+ GSC_BUSY_IN => mlt_gsc_busy,
+ SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
+ SLV_READ_IN => BUS_IP_RX.read,
+ SLV_WRITE_IN => BUS_IP_RX.write,
+ SLV_BUSY_OUT => busip0.nack,
+ SLV_ACK_OUT => busip0.ack,
+ SLV_DATA_IN => BUS_IP_RX.data,
+ SLV_DATA_OUT => busip0.data,
+ CFG_GBE_ENABLE_IN => cfg_gbe_enable,
+ CFG_IPU_ENABLE_IN => cfg_ipu_enable,
+ CFG_MULT_ENABLE_IN => cfg_mult_enable,
+ CFG_MAX_FRAME_IN => cfg_max_frame,
+ CFG_ALLOW_RX_IN => cfg_allow_rx,
+ CFG_SOFT_RESET_IN => cfg_soft_rst,
+ CFG_SUBEVENT_ID_IN => cfg_subevent_id,
+ CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
+ CFG_QUEUE_DEC_IN => cfg_queue_dec,
+ CFG_READOUT_CTR_IN => cfg_readout_ctr,
+ CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
+ CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
+ CFG_MAX_SUB_IN => cfg_max_sub,
+ CFG_MAX_QUEUE_IN => cfg_max_queue,
+ CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
+ CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
+ CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
+ CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
+ CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
+ CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+ FWD_DST_MAC_IN => FWD_DST_MAC_IN(47 downto 0),
+ FWD_DST_IP_IN => FWD_DST_IP_IN(31 downto 0),
+ FWD_DST_UDP_IN => FWD_DST_UDP_IN(15 downto 0),
+ FWD_DATA_IN => FWD_DATA_IN(7 downto 0),
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN(0),
+ FWD_SOP_IN => FWD_SOP_IN(0),
+ FWD_EOP_IN => FWD_EOP_IN(0),
+ FWD_READY_OUT => FWD_READY_OUT(0),
+ FWD_FULL_OUT => FWD_FULL_OUT(0),
+ MONITOR_RX_FRAMES_OUT => monitor_rx_frames,
+ MONITOR_RX_BYTES_OUT => monitor_rx_bytes,
+ MONITOR_TX_FRAMES_OUT => monitor_tx_frames,
+ MONITOR_TX_BYTES_OUT => monitor_tx_bytes,
+ MONITOR_TX_PACKETS_OUT => monitor_tx_packets,
+ MONITOR_DROPPED_OUT => monitor_dropped,
+ MONITOR_GEN_DBG_OUT => monitor_gen_dbg,
+ MAKE_RESET_OUT => make_reset0
+ );
+
+ BUS_IP_TX.ack <= busip0.ack when rising_edge(CLK_SYS_IN);
+ BUS_IP_TX.nack <= busip0.nack when rising_edge(CLK_SYS_IN);
+ BUS_IP_TX.data <= busip0.data when rising_edge(CLK_SYS_IN);
+
+ real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate
+ ipu_mult : entity work.gbe_ipu_multiplexer
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ LINK_HAS_READOUT => LINK_HAS_READOUT,
+-- NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
+ NUMBER_OF_GBE_LINKS => 1
+ )
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ RESET => RESET,
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ MLT_CTS_NUMBER_OUT => mlt_cts_number,
+ MLT_CTS_CODE_OUT => mlt_cts_code,
+ MLT_CTS_INFORMATION_OUT => mlt_cts_information,
+ MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
+ MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
+ MLT_CTS_DATA_IN => mlt_cts_data,
+ MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
+ MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+ MLT_CTS_READ_OUT => mlt_cts_read,
+ MLT_CTS_LENGTH_IN => mlt_cts_length,
+ MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
+ MLT_FEE_DATA_OUT => mlt_fee_data,
+ MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
+ MLT_FEE_READ_IN => mlt_fee_read,
+ MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
+ MLT_FEE_BUSY_OUT => mlt_fee_busy,
+ DEBUG_OUT => open
+ );
+ end generate real_ipu_gen;
+
+ dummy_ipu_gen : if (USE_EXTERNAL_TRBNET_DUMMY = 1) generate
+ ipu_mult : entity work.gbe_ipu_multiplexer
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ LINK_HAS_READOUT => LINK_HAS_READOUT,
+ NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
+ )
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ RESET => RESET,
+ CTS_NUMBER_IN => local_cts_number,
+ CTS_CODE_IN => local_cts_code,
+ CTS_INFORMATION_IN => local_cts_information,
+ CTS_READOUT_TYPE_IN => local_cts_readout_type,
+ CTS_START_READOUT_IN => local_cts_start_readout,
+ CTS_DATA_OUT => open,
+ CTS_DATAREADY_OUT => open,
+ CTS_READOUT_FINISHED_OUT => local_cts_readout_finished,
+ CTS_READ_IN => '1',
+ CTS_LENGTH_OUT => open,
+ CTS_ERROR_PATTERN_OUT => local_cts_status_bits,
+ FEE_DATA_IN => local_fee_data,
+ FEE_DATAREADY_IN => local_fee_dataready,
+ FEE_READ_OUT => local_fee_read,
+ FEE_STATUS_BITS_IN => local_fee_status_bits,
+ FEE_BUSY_IN => local_fee_busy,
+ MLT_CTS_NUMBER_OUT => mlt_cts_number,
+ MLT_CTS_CODE_OUT => mlt_cts_code,
+ MLT_CTS_INFORMATION_OUT => mlt_cts_information,
+ MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
+ MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
+ MLT_CTS_DATA_IN => mlt_cts_data,
+ MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
+ MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+ MLT_CTS_READ_OUT => mlt_cts_read,
+ MLT_CTS_LENGTH_IN => mlt_cts_length,
+ MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
+ MLT_FEE_DATA_OUT => mlt_fee_data,
+ MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
+ MLT_FEE_READ_IN => mlt_fee_read,
+ MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
+ MLT_FEE_BUSY_OUT => mlt_fee_busy,
+ DEBUG_OUT => open
+ );
+
+ dummy : entity work.gbe_ipu_dummy
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ FIXED_DELAY => FIXED_DELAY
+ )
+ port map(
+ clk => CLK_SYS_IN,
+ rst => RESET,
+ GBE_READY_IN => all_links_ready,
+ CFG_EVENT_SIZE_IN => dummy_event,
+ CFG_TRIGGERED_MODE_IN => '0',
+ TRIGGER_IN => TRIGGER_IN,
+ CTS_NUMBER_OUT => local_cts_number,
+ CTS_CODE_OUT => local_cts_code,
+ CTS_INFORMATION_OUT => local_cts_information,
+ CTS_READOUT_TYPE_OUT => local_cts_readout_type,
+ CTS_START_READOUT_OUT => local_cts_start_readout,
+ CTS_DATA_IN => (others => '0'),
+ CTS_DATAREADY_IN => '0',
+ CTS_READOUT_FINISHED_IN => local_cts_readout_finished,
+ CTS_READ_OUT => open,
+ CTS_LENGTH_IN => (others => '0'),
+ CTS_ERROR_PATTERN_IN => local_cts_status_bits,
+ -- Data payload interface
+ FEE_DATA_OUT => local_fee_data,
+ FEE_DATAREADY_OUT => local_fee_dataready,
+ FEE_READ_IN => local_fee_read,
+ FEE_STATUS_BITS_OUT => local_fee_status_bits,
+ FEE_BUSY_OUT => local_fee_busy
+ );
+
+ -- handler for triggers
+ DUMMY_HANDLER : entity work.trb_net16_gbe_ipu_interface
+ port map(
+ CLK_IPU => CLK_SYS_IN,
+ CLK_GBE => CLK_125_IN,
+ RESET => RESET,
+ --Event information coming from CTS
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ -- Data from Frontends
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ -- slow control interface
+ START_CONFIG_OUT => open,
+ BANK_SELECT_OUT => open,
+ CONFIG_DONE_IN => '1',
+ DATA_GBE_ENABLE_IN => '1',
+ DATA_IPU_ENABLE_IN => '1',
+ MULT_EVT_ENABLE_IN => '1',
+ MAX_SUBEVENT_SIZE_IN => (others => '0'),
+ MAX_QUEUE_SIZE_IN => (others => '0'),
+ MAX_SUBS_IN_QUEUE_IN => (others => '0'),
+ MAX_SINGLE_SUB_SIZE_IN => (others => '0'),
+ READOUT_CTR_IN => (others => '0'),
+ READOUT_CTR_VALID_IN => '0',
+ CFG_AUTO_THROTTLE_IN => '0',
+ CFG_THROTTLE_PAUSE_IN => (others => '0'),
+ -- PacketConstructor interface
+ PC_WR_EN_OUT => open,
+ PC_DATA_OUT => open,
+ PC_READY_IN => '1',
+ PC_SOS_OUT => open,
+ PC_EOS_OUT => open,
+ PC_EOQ_OUT => open,
+ PC_SUB_SIZE_OUT => open,
+ PC_TRIG_NR_OUT => open,
+ PC_TRIGGER_TYPE_OUT => open,
+ MONITOR_OUT => open,
+ DEBUG_OUT => open
+ );
+ end generate dummy_ipu_gen;
+
+ SETUP : gbe_setup
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => RESET,
+ -- interface to regio bus
+ BUS_ADDR_IN => BUS_REG_RX.addr(7 downto 0),
+ BUS_DATA_IN => BUS_REG_RX.data,
+ BUS_DATA_OUT => BUS_REG_TX.data,
+ BUS_WRITE_EN_IN => BUS_REG_RX.write,
+ BUS_READ_EN_IN => BUS_REG_RX.read,
+ BUS_ACK_OUT => BUS_REG_TX.ack,
+ -- output to gbe_buf
+ GBE_SUBEVENT_ID_OUT => cfg_subevent_id,
+ GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec,
+ GBE_QUEUE_DEC_OUT => cfg_queue_dec,
+ GBE_MAX_FRAME_OUT => cfg_max_frame,
+ GBE_USE_GBE_OUT => cfg_gbe_enable,
+ GBE_USE_TRBNET_OUT => cfg_ipu_enable,
+ GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable,
+ GBE_READOUT_CTR_OUT => cfg_readout_ctr,
+ GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid,
+ GBE_ALLOW_RX_OUT => cfg_allow_rx,
+ GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr,
+ GBE_INSERT_TTYPE_OUT => cfg_insert_ttype,
+ GBE_SOFT_RESET_OUT => cfg_soft_rst,
+ GBE_MAX_REPLY_OUT => cfg_max_reply,
+ GBE_MAX_SUB_OUT => cfg_max_sub,
+ GBE_MAX_QUEUE_OUT => cfg_max_queue,
+ GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue,
+ GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub,
+ GBE_AUTOTHROTTLE_OUT => cfg_autothrottle,
+ GBE_THROTTLE_PAUSE_OUT => cfg_throttle_pause,
+ MONITOR_RX_BYTES_IN => sum_rx_bytes,
+ MONITOR_RX_FRAMES_IN => sum_rx_frames,
+ MONITOR_TX_BYTES_IN => sum_tx_bytes,
+ MONITOR_TX_FRAMES_IN => sum_tx_frames,
+ MONITOR_TX_PACKETS_IN => sum_tx_packets,
+ MONITOR_DROPPED_IN => sum_dropped,
+ MONITOR_SELECT_REC_IN => (others => '0'),
+ MONITOR_SELECT_REC_BYTES_IN => (others => '0'),
+ MONITOR_SELECT_SENT_BYTES_IN => (others => '0'),
+ MONITOR_SELECT_SENT_IN => (others => '0'),
+ MONITOR_SELECT_DROP_IN_IN => (others => '0'),
+ MONITOR_SELECT_DROP_OUT_IN => (others => '0'),
+ MONITOR_SELECT_GEN_DBG_IN => monitor_gen_dbg,
+ MONITOR_IP_IN => my_ip,
+ DUMMY_EVENT_SIZE_OUT => dummy_event,
+ DUMMY_TRIGGERED_MODE_OUT => dummy_mode,
+ DATA_HIST_IN => (others => (others => '0')),
+ SCTRL_HIST_IN => (others => (others => '0'))
+ );
+
+ NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = "0000") generate
+ GSC_INIT_DATAREADY_OUT <= '0';
+ GSC_INIT_DATA_OUT <= (others => '0');
+ GSC_INIT_PACKET_NUM_OUT <= (others => '0');
+ GSC_REPLY_READ_OUT <= '1';
+ mlt_gsc_clk <= (others => '0');
+ mlt_gsc_init_read <= (others => '0');
+ mlt_gsc_reply_dataready <= (others => '0');
+ mlt_gsc_reply_data <= (others => '0');
+ mlt_gsc_reply_packet <= (others => '0');
+ mlt_gsc_busy <= (others => '0');
+ end generate NOSCTRL_MAP_GEN;
+
+ SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL /= "0000") generate
+ ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(0) = '1') generate
+ mlt_gsc_clk <= GSC_CLK_IN;
+ GSC_INIT_DATAREADY_OUT <= mlt_gsc_init_dataready;
+ GSC_INIT_DATA_OUT <= mlt_gsc_init_data;
+ GSC_INIT_PACKET_NUM_OUT <= mlt_gsc_init_packet;
+ mlt_gsc_init_read <= GSC_INIT_READ_IN;
+ mlt_gsc_reply_dataready <= GSC_REPLY_DATAREADY_IN;
+ mlt_gsc_reply_data <= GSC_REPLY_DATA_IN;
+ mlt_gsc_reply_packet <= GSC_REPLY_PACKET_NUM_IN;
+ GSC_REPLY_READ_OUT <= mlt_gsc_reply_read;
+ mlt_gsc_busy <= GSC_BUSY_IN;
+ end generate ACTIVE_MAP_GEN;
+
+ INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(0) = '0') generate
+ mlt_gsc_clk <= '0';
+ mlt_gsc_init_read <= '0';
+ mlt_gsc_reply_dataready <= '0';
+ mlt_gsc_reply_data <= (others => '0');
+ mlt_gsc_reply_packet <= (others => '0');
+ mlt_gsc_busy <= '0';
+ end generate INACTIVE_MAP_GEN;
+ end generate SCTRL_MAP_GEN;
+
+ sum_rx_bytes <= monitor_rx_bytes;
+ sum_rx_frames <= monitor_rx_frames;
+ sum_tx_bytes <= monitor_tx_bytes;
+ sum_tx_frames <= monitor_tx_frames;
+ sum_tx_packets <= monitor_tx_packets;
+ sum_dropped <= monitor_dropped;
+
+end architecture RTL;
--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "serdes_gbe_4ch_ds.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH1_CDR_SRC : String := "REFCLK_CORE";
+-- CH2_CDR_SRC : String := "REFCLK_CORE";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_gbe_4ch_ds is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_4ch_ds.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (7 downto 0);
+ tx_k_ch0 : in std_logic;
+ xmit_ch0 : in std_logic;
+ tx_disp_correct_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ rx_serdes_rst_ch0_c : in std_logic;
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pcs_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pcs_rst_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (7 downto 0);
+ tx_k_ch1 : in std_logic;
+ xmit_ch1 : in std_logic;
+ tx_disp_correct_ch1 : in std_logic;
+ rxdata_ch1 : out std_logic_vector (7 downto 0);
+ rx_k_ch1 : out std_logic;
+ rx_disp_err_ch1 : out std_logic;
+ rx_cv_err_ch1 : out std_logic;
+ rx_serdes_rst_ch1_c : in std_logic;
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pcs_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pcs_rst_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ rxiclk_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (7 downto 0);
+ tx_k_ch2 : in std_logic;
+ xmit_ch2 : in std_logic;
+ tx_disp_correct_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ rx_serdes_rst_ch2_c : in std_logic;
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pcs_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pcs_rst_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ rxiclk_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (7 downto 0);
+ tx_k_ch3 : in std_logic;
+ xmit_ch3 : in std_logic;
+ tx_disp_correct_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ rx_serdes_rst_ch3_c : in std_logic;
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pcs_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pcs_rst_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+---- Miscillaneous ports
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ rst_qd_c : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end serdes_gbe_4ch_ds;
+
+
+architecture serdes_gbe_4ch_ds_arch of serdes_gbe_4ch_ds is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH0_CDR_SRC: string;
+ attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH1_CDR_SRC: string;
+ attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH2_CDR_SRC: string;
+ attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH3_CDR_SRC: string;
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal tx_full_clk_ch0_sig : std_logic;
+signal tx_full_clk_ch1_sig : std_logic;
+signal tx_full_clk_ch2_sig : std_logic;
+signal tx_full_clk_ch3_sig : std_logic;
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ rx_los_low_ch0_s <= rx_los_low_ch0_sig;
+ rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+ rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+ rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+ rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+ rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+ rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
+ rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+ tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+ tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
+ tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+ tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
+ tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH0_CDR_SRC => "REFCLK_CORE",
+ CH1_CDR_SRC => "REFCLK_CORE",
+ CH2_CDR_SRC => "REFCLK_CORE",
+ CH3_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => hdoutp_ch0,
+ HDOUTN0 => hdoutn_ch0,
+ HDINP0 => hdinp_ch0,
+ HDINN0 => hdinn_ch0,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => rxiclk_ch0,
+ FF_TXI_CLK_0 => txiclk_ch0,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => rx_full_clk_ch0,
+ FF_RX_H_CLK_0 => rx_half_clk_ch0,
+ FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
+ FF_TX_H_CLK_0 => tx_half_clk_ch0,
+ FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
+ FF_TX_D_0_0 => txdata_ch0(0),
+ FF_TX_D_0_1 => txdata_ch0(1),
+ FF_TX_D_0_2 => txdata_ch0(2),
+ FF_TX_D_0_3 => txdata_ch0(3),
+ FF_TX_D_0_4 => txdata_ch0(4),
+ FF_TX_D_0_5 => txdata_ch0(5),
+ FF_TX_D_0_6 => txdata_ch0(6),
+ FF_TX_D_0_7 => txdata_ch0(7),
+ FF_TX_D_0_8 => tx_k_ch0,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => xmit_ch0,
+ FF_TX_D_0_11 => tx_disp_correct_ch0,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => rxdata_ch0(0),
+ FF_RX_D_0_1 => rxdata_ch0(1),
+ FF_RX_D_0_2 => rxdata_ch0(2),
+ FF_RX_D_0_3 => rxdata_ch0(3),
+ FF_RX_D_0_4 => rxdata_ch0(4),
+ FF_RX_D_0_5 => rxdata_ch0(5),
+ FF_RX_D_0_6 => rxdata_ch0(6),
+ FF_RX_D_0_7 => rxdata_ch0(7),
+ FF_RX_D_0_8 => rx_k_ch0,
+ FF_RX_D_0_9 => rx_disp_err_ch0,
+ FF_RX_D_0_10 => rx_cv_err_ch0,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => rx_serdes_rst_ch0_c,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
+ FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
+ FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
+ FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
+ FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
+ FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => fpsc_vlo,
+
+----- CH1 -----
+ HDOUTP1 => hdoutp_ch1,
+ HDOUTN1 => hdoutn_ch1,
+ HDINP1 => hdinp_ch1,
+ HDINN1 => hdinn_ch1,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => fpsc_vlo,
+ SCIENCH1 => fpsc_vlo,
+ FF_RXI_CLK_1 => rxiclk_ch1,
+ FF_TXI_CLK_1 => txiclk_ch1,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => rx_full_clk_ch1,
+ FF_RX_H_CLK_1 => rx_half_clk_ch1,
+ FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+ FF_TX_H_CLK_1 => tx_half_clk_ch1,
+ FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+ FF_TX_D_1_0 => txdata_ch1(0),
+ FF_TX_D_1_1 => txdata_ch1(1),
+ FF_TX_D_1_2 => txdata_ch1(2),
+ FF_TX_D_1_3 => txdata_ch1(3),
+ FF_TX_D_1_4 => txdata_ch1(4),
+ FF_TX_D_1_5 => txdata_ch1(5),
+ FF_TX_D_1_6 => txdata_ch1(6),
+ FF_TX_D_1_7 => txdata_ch1(7),
+ FF_TX_D_1_8 => tx_k_ch1,
+ FF_TX_D_1_9 => fpsc_vlo,
+ FF_TX_D_1_10 => xmit_ch1,
+ FF_TX_D_1_11 => tx_disp_correct_ch1,
+ FF_TX_D_1_12 => fpsc_vlo,
+ FF_TX_D_1_13 => fpsc_vlo,
+ FF_TX_D_1_14 => fpsc_vlo,
+ FF_TX_D_1_15 => fpsc_vlo,
+ FF_TX_D_1_16 => fpsc_vlo,
+ FF_TX_D_1_17 => fpsc_vlo,
+ FF_TX_D_1_18 => fpsc_vlo,
+ FF_TX_D_1_19 => fpsc_vlo,
+ FF_TX_D_1_20 => fpsc_vlo,
+ FF_TX_D_1_21 => fpsc_vlo,
+ FF_TX_D_1_22 => fpsc_vlo,
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => rxdata_ch1(0),
+ FF_RX_D_1_1 => rxdata_ch1(1),
+ FF_RX_D_1_2 => rxdata_ch1(2),
+ FF_RX_D_1_3 => rxdata_ch1(3),
+ FF_RX_D_1_4 => rxdata_ch1(4),
+ FF_RX_D_1_5 => rxdata_ch1(5),
+ FF_RX_D_1_6 => rxdata_ch1(6),
+ FF_RX_D_1_7 => rxdata_ch1(7),
+ FF_RX_D_1_8 => rx_k_ch1,
+ FF_RX_D_1_9 => rx_disp_err_ch1,
+ FF_RX_D_1_10 => rx_cv_err_ch1,
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => open,
+ FF_RX_D_1_13 => open,
+ FF_RX_D_1_14 => open,
+ FF_RX_D_1_15 => open,
+ FF_RX_D_1_16 => open,
+ FF_RX_D_1_17 => open,
+ FF_RX_D_1_18 => open,
+ FF_RX_D_1_19 => open,
+ FF_RX_D_1_20 => open,
+ FF_RX_D_1_21 => open,
+ FF_RX_D_1_22 => open,
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => rx_serdes_rst_ch1_c,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+ FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
+ FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+ FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+ FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+ FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => fpsc_vlo,
+
+----- CH2 -----
+ HDOUTP2 => hdoutp_ch2,
+ HDOUTN2 => hdoutn_ch2,
+ HDINP2 => hdinp_ch2,
+ HDINN2 => hdinn_ch2,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => rxiclk_ch2,
+ FF_TXI_CLK_2 => txiclk_ch2,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => rx_full_clk_ch2,
+ FF_RX_H_CLK_2 => rx_half_clk_ch2,
+ FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
+ FF_TX_H_CLK_2 => tx_half_clk_ch2,
+ FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+ FF_TX_D_2_0 => txdata_ch2(0),
+ FF_TX_D_2_1 => txdata_ch2(1),
+ FF_TX_D_2_2 => txdata_ch2(2),
+ FF_TX_D_2_3 => txdata_ch2(3),
+ FF_TX_D_2_4 => txdata_ch2(4),
+ FF_TX_D_2_5 => txdata_ch2(5),
+ FF_TX_D_2_6 => txdata_ch2(6),
+ FF_TX_D_2_7 => txdata_ch2(7),
+ FF_TX_D_2_8 => tx_k_ch2,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => xmit_ch2,
+ FF_TX_D_2_11 => tx_disp_correct_ch2,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => rxdata_ch2(0),
+ FF_RX_D_2_1 => rxdata_ch2(1),
+ FF_RX_D_2_2 => rxdata_ch2(2),
+ FF_RX_D_2_3 => rxdata_ch2(3),
+ FF_RX_D_2_4 => rxdata_ch2(4),
+ FF_RX_D_2_5 => rxdata_ch2(5),
+ FF_RX_D_2_6 => rxdata_ch2(6),
+ FF_RX_D_2_7 => rxdata_ch2(7),
+ FF_RX_D_2_8 => rx_k_ch2,
+ FF_RX_D_2_9 => rx_disp_err_ch2,
+ FF_RX_D_2_10 => rx_cv_err_ch2,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => rx_serdes_rst_ch2_c,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
+ FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
+ FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
+ FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+ FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
+ FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => fpsc_vlo,
+
+----- CH3 -----
+ HDOUTP3 => hdoutp_ch3,
+ HDOUTN3 => hdoutn_ch3,
+ HDINP3 => hdinp_ch3,
+ HDINN3 => hdinn_ch3,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => fpsc_vlo,
+ SCIENCH3 => fpsc_vlo,
+ FF_RXI_CLK_3 => rxiclk_ch3,
+ FF_TXI_CLK_3 => txiclk_ch3,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => rx_full_clk_ch3,
+ FF_RX_H_CLK_3 => rx_half_clk_ch3,
+ FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+ FF_TX_H_CLK_3 => tx_half_clk_ch3,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+ FF_TX_D_3_0 => txdata_ch3(0),
+ FF_TX_D_3_1 => txdata_ch3(1),
+ FF_TX_D_3_2 => txdata_ch3(2),
+ FF_TX_D_3_3 => txdata_ch3(3),
+ FF_TX_D_3_4 => txdata_ch3(4),
+ FF_TX_D_3_5 => txdata_ch3(5),
+ FF_TX_D_3_6 => txdata_ch3(6),
+ FF_TX_D_3_7 => txdata_ch3(7),
+ FF_TX_D_3_8 => tx_k_ch3,
+ FF_TX_D_3_9 => fpsc_vlo,
+ FF_TX_D_3_10 => xmit_ch3,
+ FF_TX_D_3_11 => tx_disp_correct_ch3,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => rxdata_ch3(0),
+ FF_RX_D_3_1 => rxdata_ch3(1),
+ FF_RX_D_3_2 => rxdata_ch3(2),
+ FF_RX_D_3_3 => rxdata_ch3(3),
+ FF_RX_D_3_4 => rxdata_ch3(4),
+ FF_RX_D_3_5 => rxdata_ch3(5),
+ FF_RX_D_3_6 => rxdata_ch3(6),
+ FF_RX_D_3_7 => rxdata_ch3(7),
+ FF_RX_D_3_8 => rx_k_ch3,
+ FF_RX_D_3_9 => rx_disp_err_ch3,
+ FF_RX_D_3_10 => rx_cv_err_ch3,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => rx_serdes_rst_ch3_c,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+ FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+ FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+ FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+ FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+ FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => fpsc_vlo,
+
+----- Auxilliary ----
+ SCIWDATA7 => fpsc_vlo,
+ SCIWDATA6 => fpsc_vlo,
+ SCIWDATA5 => fpsc_vlo,
+ SCIWDATA4 => fpsc_vlo,
+ SCIWDATA3 => fpsc_vlo,
+ SCIWDATA2 => fpsc_vlo,
+ SCIWDATA1 => fpsc_vlo,
+ SCIWDATA0 => fpsc_vlo,
+ SCIADDR5 => fpsc_vlo,
+ SCIADDR4 => fpsc_vlo,
+ SCIADDR3 => fpsc_vlo,
+ SCIADDR2 => fpsc_vlo,
+ SCIADDR1 => fpsc_vlo,
+ SCIADDR0 => fpsc_vlo,
+ SCIRDATA7 => open,
+ SCIRDATA6 => open,
+ SCIRDATA5 => open,
+ SCIRDATA4 => open,
+ SCIRDATA3 => open,
+ SCIRDATA2 => open,
+ SCIRDATA1 => open,
+ SCIRDATA0 => open,
+ SCIENAUX => fpsc_vlo,
+ SCISELAUX => fpsc_vlo,
+ SCIRD => fpsc_vlo,
+ SCIWSTN => fpsc_vlo,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => rst_qd_c,
+ FFC_TRST => tx_serdes_rst_c,
+ FFS_PLOL => tx_pll_lol_qd_sig,
+ FFC_SYNC_TOGGLE => tx_sync_qd_c,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end serdes_gbe_4ch_ds_arch ;
jspc29 / trbnet.git / commitdiff