<Source name="source/med_ecp3_sfp_sync_up.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/serdes_sync_upstream.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/serdes_sync_client_upstream.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
<Options/>
</Source>
- <Source name="source/serdes_sync_upstream.lpc" type="LPC_Module" type_short="LPC">
+ <Source name="source/serdes_sync_client_upstream.lpc" type="LPC_Module" type_short="LPC" excluded="TRUE">
<Options/>
</Source>
- <Source name="source/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
+ <Source name="source/serdes_sync_client_upstream.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
<Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
-rvl_alias "reveal_ist_458" "the_sync_link/clk_rx_full";
+rvl_alias "soda_rx_clock_full" "soda_rx_clock_full";
RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
USE PRIMARY NET "clk_sys_internal" ;
#USE SECONDARY NET "THE_SYNC_LINK/sci_read_i" ;
#USE SECONDARY NET "THE_SYNC_LINK/sci_write_i" ;
-USE PRIMARY PURE NET "CLK_PCLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-USE PRIMARY PURE NET "GPLL_CLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
+#USE PRIMARY PURE NET "CLK_PCLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
+USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
USE PRIMARY NET "soda_rx_clock_full" ;
USE PRIMARY NET "soda_rx_clock_half" ;
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-01-20">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-04-14">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_client"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2020146143" Name="trb3_periph_sodaclient_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2031949050" Name="trb3_periph_sodaclient_LA0" ID="0">
<Setting>
- <Clock SampleClk="the_sync_link/clk_rx_full" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="512"/>
+ <Clock SampleClk="soda_rx_clock_full" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="1024"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_client_LA0_net"/>
</Setting>
<Dataset Name="Base">
<Trace>
- <Sig Type="SIG" Name="the_sync_link/the_tx/rx_allow_qtx"/>
- <Sig Type="SIG" Name="the_sync_link/the_tx/tx_allow_qtx"/>
- <Bus Name="the_sync_link/the_tx/tx_data_out">
- <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:3"/>
- <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:4"/>
- <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:5"/>
- <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:6"/>
- <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:7"/>
+ <Bus Name="sfp_los">
+ <Sig Type="SIG" Name="sfp_los:1"/>
+ <Sig Type="SIG" Name="sfp_los:2"/>
+ <Sig Type="SIG" Name="sfp_los:3"/>
+ <Sig Type="SIG" Name="sfp_los:4"/>
+ <Sig Type="SIG" Name="sfp_los:5"/>
+ <Sig Type="SIG" Name="sfp_los:6"/>
+ </Bus>
+ <Bus Name="the_sync_link/watchdog_timer">
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:0"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:1"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:2"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:3"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:4"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:5"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:6"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:7"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:8"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:9"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:10"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:11"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:12"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:13"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:14"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:15"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:16"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:17"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:18"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:19"/>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_timer:20"/>
+ </Bus>
+ <Bus Name="sfp_txdis">
+ <Sig Type="SIG" Name="sfp_txdis:1"/>
+ <Sig Type="SIG" Name="sfp_txdis:2"/>
+ <Sig Type="SIG" Name="sfp_txdis:3"/>
+ <Sig Type="SIG" Name="sfp_txdis:4"/>
+ <Sig Type="SIG" Name="sfp_txdis:5"/>
+ <Sig Type="SIG" Name="sfp_txdis:6"/>
+ </Bus>
+ <Sig Type="SIG" Name="tx_dlm_i"/>
+ <Sig Type="SIG" Name="tx_dlm_preview_s"/>
+ <Bus Name="tx_dlm_word">
+ <Sig Type="SIG" Name="tx_dlm_word:0"/>
+ <Sig Type="SIG" Name="tx_dlm_word:1"/>
+ <Sig Type="SIG" Name="tx_dlm_word:2"/>
+ <Sig Type="SIG" Name="tx_dlm_word:3"/>
+ <Sig Type="SIG" Name="tx_dlm_word:4"/>
+ <Sig Type="SIG" Name="tx_dlm_word:5"/>
+ <Sig Type="SIG" Name="tx_dlm_word:6"/>
+ <Sig Type="SIG" Name="tx_dlm_word:7"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/rst"/>
+ <Sig Type="SIG" Name="the_sync_link/rst_n"/>
+ <Sig Type="SIG" Name="the_sync_link/rst_qd"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_allow"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_allow_q"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_cdr_lol"/>
+ <Bus Name="the_sync_link/rx_data">
+ <Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:2"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:3"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:4"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:5"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
</Bus>
- <Sig Type="SIG" Name="the_sync_link/link_phase_s"/>
<Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
<Bus Name="the_sync_link/rx_dlm_word">
<Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
<Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
<Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
</Bus>
+ <Sig Type="SIG" Name="the_sync_link/rx_error"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/tx_pll_lol_qd_s_int"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_los_low_int"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_lol_los"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_cdr_lol_ch_s"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_los_low_ch_s"/>
+ <Bus Name="the_sync_link/rx_fsm_state">
+ <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:0"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:1"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:2"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:3"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/rx_k"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_los_low"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_pcs_rst"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_serdes_rst"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_allow"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_allow_q"/>
+ <Bus Name="the_sync_link/tx_data">
+ <Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:2"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:3"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:4"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:5"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:6"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:7"/>
+ </Bus>
<Sig Type="SIG" Name="the_sync_link/tx_dlm"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_preview_in"/>
<Bus Name="the_sync_link/tx_dlm_word">
<Sig Type="SIG" Name="the_sync_link/tx_dlm_word:0"/>
<Sig Type="SIG" Name="the_sync_link/tx_dlm_word:1"/>
<Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
<Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
</Bus>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/start_of_superburst"/>
- <Bus Name="a_soda_client/reply_packet_builder/super_burst_nr_in">
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:0"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:1"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:2"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:3"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:4"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:5"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:6"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:7"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:8"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:9"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:10"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:11"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:12"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:13"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:14"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:15"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:16"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:17"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:18"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:19"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:20"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:21"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:22"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:23"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:24"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:25"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:26"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:27"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:28"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:29"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:30"/>
- </Bus>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_preview_out"/>
- <Sig Type="SIG" Name="the_sync_link/make_link_reset_i"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/got_link_ready"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/make_reset_out"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_dlm"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_write_out"/>
- <Bus Name="the_sync_link/start_timer">
- <Sig Type="SIG" Name="the_sync_link/start_timer:0"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:1"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:2"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:3"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:4"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:5"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:6"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:7"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:8"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:9"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:10"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:11"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:12"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:13"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:14"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:15"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:16"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:17"/>
- <Sig Type="SIG" Name="the_sync_link/start_timer:18"/>
- </Bus>
- <Bus Name="the_sync_link/rx_fsm_state">
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:3"/>
- </Bus>
- <Bus Name="the_sync_link/the_rx_control/rx_state">
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state:2"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/got_link_ready_i"/>
+ <Bus Name="the_sync_link/tx_fsm_state">
+ <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:0"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:1"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:2"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:3"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/tx_k"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_pcs_rst"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_pll_lol"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_serdes_rst"/>
+ <Sig Type="SIG" Name="the_sync_link/sd_los_in"/>
+ <Sig Type="SIG" Name="the_sync_link/sysclk"/>
<Bus Name="the_sync_link/the_rx_control/rx_state_bits">
<Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state_bits:0"/>
<Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state_bits:1"/>
<Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state_bits:2"/>
<Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state_bits:3"/>
</Bus>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_k_in"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_k_in"/>
- <Bus Name="the_sync_link/the_rx_control/rx_data_in">
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_data_in:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_data_in:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_data_in:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_data_in:3"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_data_in:4"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_data_in:5"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_data_in:6"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_data_in:7"/>
+ <Bus Name="the_sync_link/the_rx_control/rx_state">
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state:0"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state:1"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state:2"/>
</Bus>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_k_in"/>
<Bus Name="the_sync_link/the_rx_control/reg_rx_data_in">
<Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:0"/>
<Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:1"/>
<Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:6"/>
<Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:7"/>
</Bus>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/next_sop"/>
- <Bus Name="the_sync_link/the_rx_fsm/counter2">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:3"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:4"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:5"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:6"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:7"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:8"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:9"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:10"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:11"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:12"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:13"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:14"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:15"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:16"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:17"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:18"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:19"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rst_n"/>
- <Bus Name="the_sync_link/the_rx_fsm/cs">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:2"/>
- </Bus>
- <Bus Name="the_sync_link/the_rx_fsm/ns">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:2"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_cdr_lol_ch_s"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_los_low_ch_s"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_pcs_rst_ch_c"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_serdes_rst_ch_c"/>
- <Bus Name="the_sync_link/the_rx_fsm/state_out">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/tx_pll_lol_qd_s"/>
- <Bus Name="the_sync_link/the_rx_fsm/wa_position">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/wa_position:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/wa_position:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/wa_position:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/wa_position:3"/>
- </Bus>
- <Bus Name="the_sync_link/watchdog_timer">
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:0"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:1"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:2"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:3"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:4"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:5"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:6"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:7"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:8"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:9"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:10"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:11"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:12"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:13"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:14"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:15"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:16"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:17"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:18"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:19"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:20"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/watchdog_trigger"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_valid_s"/>
- <Bus Name="a_soda_client/soda_cmd_word_s">
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:0"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:1"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:2"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:3"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:4"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:5"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:6"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:7"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:8"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:9"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:10"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:11"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:12"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:13"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:14"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:15"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:16"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:17"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:18"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:19"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:20"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:21"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:22"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:23"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:24"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:25"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:26"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:27"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:28"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:29"/>
- <Sig Type="SIG" Name="a_soda_client/soda_cmd_word_s:30"/>
- </Bus>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/got_link_ready_i"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/got_link_ready"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/make_reset_i"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_dlm_i"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/send_link_reset_i"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_control/start_retr_i"/>
+ <Sig Type="SIG" Name="the_sync_link/lsm_status"/>
<Sig Type="SIG" Name="a_soda_client/start_of_superburst_s"/>
+ <Bus Name="a_soda_client/super_burst_nr_s">
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:0"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:1"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:2"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:3"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:4"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:5"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:6"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:7"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:8"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:9"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:10"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:11"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:12"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:13"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:14"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:15"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:16"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:17"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:18"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:19"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:20"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:21"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:22"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:23"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:24"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:25"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:26"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:27"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:28"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:29"/>
+ <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:30"/>
+ </Bus>
</Trace>
<Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_client/start_of_superburst_s,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="a_soda_client/rx_dlm_in,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="a_soda_client/tx_dlm_out,"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_link/make_link_reset_i,"/>
- <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_sync_link/the_rx_control/rx_state[2:0],"/>
- <TU Serialbits="0" Type="0" ID="6" Sig="the_sync_link/watchdog_trigger,"/>
+ <TU Serialbits="0" Type="0" ID="1" Sig="the_sync_link/watchdog_trigger,"/>
+ <TU Serialbits="0" Type="0" ID="2" Sig="the_sync_link/tx_k,"/>
+ <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/start_timer:18,"/>
+ <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_link/rx_error,"/>
+ <TU Serialbits="0" Type="0" ID="5" Sig="the_sync_link/rx_serdes_rst,"/>
+ <TU Serialbits="0" Type="0" ID="6" Sig="the_sync_link/rx_los_low,"/>
+ <TU Serialbits="0" Type="0" ID="7" Sig="the_sync_link/lsm_status,"/>
+ <TU Serialbits="0" Type="0" ID="8" Sig="the_sync_link/rx_cdr_lol,"/>
+ <TU Serialbits="0" Type="0" ID="9" Sig="the_sync_link/rst_qd,"/>
+ <TU Serialbits="0" Type="0" ID="10" Sig="the_sync_link/serdes_rst_qd,"/>
<TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="7" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="8" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="9" Resource="0"/>
</Trigger>
</Dataset>
</Core>
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-01-30">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-03-27">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2021452834" Name="trb3_periph_sodaclient_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2029450704" Name="trb3_periph_sodahub_LA0" ID="0">
<Setting>
- <Clock SampleClk="soda_rx_clock_full" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <Clock SampleClk="clk_soda_i" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
- <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_client_LA0_net"/>
+ <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_hub_LA0_net"/>
</Setting>
<Dataset Name="Base">
<Trace>
- <Sig Type="SIG" Name="rxup_dlm_i"/>
- <Bus Name="rxup_dlm_word">
- <Sig Type="SIG" Name="rxup_dlm_word:0"/>
- <Sig Type="SIG" Name="rxup_dlm_word:1"/>
- <Sig Type="SIG" Name="rxup_dlm_word:2"/>
- <Sig Type="SIG" Name="rxup_dlm_word:3"/>
- <Sig Type="SIG" Name="rxup_dlm_word:4"/>
- <Sig Type="SIG" Name="rxup_dlm_word:5"/>
- <Sig Type="SIG" Name="rxup_dlm_word:6"/>
- <Sig Type="SIG" Name="rxup_dlm_word:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/clk_rx_half_out"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/clk_tx_half"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/link_phase_out"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/lsm_status"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rst"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rst_n"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rst_qd"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_allow"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_allow_q"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_cdr_lol"/>
+ <Bus Name="the_hub_sync_uplink/rx_data">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:7"/>
</Bus>
- <Sig Type="SIG" Name="txup_dlm_i"/>
- <Sig Type="SIG" Name="txup_dlm_preview_s"/>
- <Bus Name="txup_dlm_word">
- <Sig Type="SIG" Name="txup_dlm_word:0"/>
- <Sig Type="SIG" Name="txup_dlm_word:1"/>
- <Sig Type="SIG" Name="txup_dlm_word:2"/>
- <Sig Type="SIG" Name="txup_dlm_word:3"/>
- <Sig Type="SIG" Name="txup_dlm_word:4"/>
- <Sig Type="SIG" Name="txup_dlm_word:5"/>
- <Sig Type="SIG" Name="txup_dlm_word:6"/>
- <Sig Type="SIG" Name="txup_dlm_word:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm"/>
+ <Bus Name="the_hub_sync_uplink/rx_dlm_word">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:7"/>
</Bus>
- <Sig Type="SIG" Name="uplink_phase_s"/>
- <Bus Name="rxdn_dlm_i">
- <Sig Type="SIG" Name="rxdn_dlm_i:0"/>
- <Sig Type="SIG" Name="rxdn_dlm_i:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_error"/>
+ <Bus Name="the_hub_sync_uplink/rx_fsm_state">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:3"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_los_low"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_pcs_rst"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_serdes_rst"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_allow"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_allow_q"/>
+ <Bus Name="the_hub_sync_uplink/tx_data">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:7"/>
</Bus>
- <Bus Name="rxdn_dlm_word[1:0]">
- <Sig Type="SIG" Name="rxdn_dlm_word:0:0"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:0:1"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:0:2"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:0:3"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:0:4"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:0:5"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:0:6"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:0:7"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:1:0"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:1:1"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:1:2"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:1:3"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:1:4"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:1:5"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:1:6"/>
- <Sig Type="SIG" Name="rxdn_dlm_word:1:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_preview_in"/>
+ <Bus Name="the_hub_sync_uplink/tx_dlm_word">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:7"/>
</Bus>
- <Bus Name="txdn_dlm_i">
- <Sig Type="SIG" Name="txdn_dlm_i:0"/>
- <Sig Type="SIG" Name="txdn_dlm_i:1"/>
+ <Bus Name="the_hub_sync_uplink/tx_fsm_state">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:3"/>
</Bus>
- <Bus Name="txdn_dlm_preview_s">
- <Sig Type="SIG" Name="txdn_dlm_preview_s:0"/>
- <Sig Type="SIG" Name="txdn_dlm_preview_s:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_k"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pcs_rst"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pll_lol"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_serdes_rst"/>
+ <Bus Name="sfp_los">
+ <Sig Type="SIG" Name="sfp_los:1"/>
+ <Sig Type="SIG" Name="sfp_los:2"/>
+ <Sig Type="SIG" Name="sfp_los:3"/>
+ <Sig Type="SIG" Name="sfp_los:4"/>
+ <Sig Type="SIG" Name="sfp_los:5"/>
+ <Sig Type="SIG" Name="sfp_los:6"/>
</Bus>
- <Bus Name="txdn_dlm_word[1:0]">
- <Sig Type="SIG" Name="txdn_dlm_word:0:0"/>
- <Sig Type="SIG" Name="txdn_dlm_word:0:1"/>
- <Sig Type="SIG" Name="txdn_dlm_word:0:2"/>
- <Sig Type="SIG" Name="txdn_dlm_word:0:3"/>
- <Sig Type="SIG" Name="txdn_dlm_word:0:4"/>
- <Sig Type="SIG" Name="txdn_dlm_word:0:5"/>
- <Sig Type="SIG" Name="txdn_dlm_word:0:6"/>
- <Sig Type="SIG" Name="txdn_dlm_word:0:7"/>
- <Sig Type="SIG" Name="txdn_dlm_word:1:0"/>
- <Sig Type="SIG" Name="txdn_dlm_word:1:1"/>
- <Sig Type="SIG" Name="txdn_dlm_word:1:2"/>
- <Sig Type="SIG" Name="txdn_dlm_word:1:3"/>
- <Sig Type="SIG" Name="txdn_dlm_word:1:4"/>
- <Sig Type="SIG" Name="txdn_dlm_word:1:5"/>
- <Sig Type="SIG" Name="txdn_dlm_word:1:6"/>
- <Sig Type="SIG" Name="txdn_dlm_word:1:7"/>
+ <Bus Name="sfp_txdis">
+ <Sig Type="SIG" Name="sfp_txdis:1"/>
+ <Sig Type="SIG" Name="sfp_txdis:2"/>
+ <Sig Type="SIG" Name="sfp_txdis:3"/>
+ <Sig Type="SIG" Name="sfp_txdis:4"/>
+ <Sig Type="SIG" Name="sfp_txdis:5"/>
+ <Sig Type="SIG" Name="sfp_txdis:6"/>
</Bus>
+ <Sig Type="SIG" Name="uplink_disable_s"/>
+ <Sig Type="SIG" Name="uplink_phase_s"/>
+ </Trace>
+ <Trigger>
+ <TU Serialbits="0" Type="0" ID="1" Sig="the_hub_sync_uplink/watchdog_trigger,"/>
+ <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
+ </Trigger>
+ </Dataset>
+ </Core>
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2029450705" Name="trb3_periph_sodahub_LA1" ID="1">
+ <Setting>
+ <Clock SampleClk="clk_raw_internal" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
+ <Capture Mode="0" MinSamplesPerTrig="8"/>
+ <Event CntEnable="0" MaxEventCnt="8"/>
+ <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_trb3_periph_sodahub_LA1_net"/>
+ </Setting>
+ <Dataset Name="Base">
+ <Trace>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/got_link_ready_i"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/clk_rx_half_out"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/clk_tx_half"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/link_phase_out"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/lsm_status"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pll_lol"/>
</Trace>
<Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_hub/start_of_calibration_s,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="the_sync_uplink/watchdog_trigger,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="(BUS)rxdn_dlm_i[1:0],"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="(BUS)txdn_dlm_i[1:0],"/>
- <TU Serialbits="0" Type="0" ID="5" Sig="a_soda_hub/start_of_calibration_s,"/>
- <TU Serialbits="0" Type="0" ID="6" Sig="(BUS)a_soda_hub/reply_valid_s[1:0],"/>
+ <TU Serialbits="0" Type="0" ID="1" Sig="gsr_n,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
</Trigger>
</Dataset>
</Core>
<Source name="source/soda_source.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_cmd_window_generator.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="source/med_ecp3_sfp_sync_down.vhd" type="VHDL" type_short="VHDL">
<Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb3_periph_sodasource"/>
- </Source>
<Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="trb3_periph_sodasource"/>
+ </Source>
+ <Source name="source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
<Source name="soda_source_probe.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
- <Source name="source/soda_source_syn_translated.fdc" type="Synplify Design Constraints File" type_short="SDC">
+ <Source name="source/soda_source_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
<Options/>
</Source>
<Source name="trb3_soda_source.xcf" type="Programming Project File" type_short="Programming">
-rvl_alias "rx_clock_full" "rx_clock_full";
+rvl_alias "clk_raw_internal" "clk_raw_internal";
RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
#################################################################
# Basic Settings
#################################################################
-SYSCONFIG MCCLK_FREQ=20 ;
+ SYSCONFIG MCCLK_FREQ=20 ;
+ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-#FREQUENCY NET "rx_clock_half" 100.000000 MHz ;
-#FREQUENCY NET "rx_clock_full" 200.000000 MHz ;
#################################################################
# Reset Nets
#################################################################
MULTICYCLE TO CELL "THE_SODA_SOURCE.packet_builder.soda_cmd_word_S*" 10.000000 ns ;
BLOCK JTAGPATHS ;
## IOBUF ALLPORTS ;
-#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;\r
+#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
+USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ;
FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ;
#-- Synopsys, Inc.
-#-- Version G-2012.09L-SP1
+#-- Version I-2013.09L
#-- Project file /local/lemmens/lattice/soda/soda_source/soda_source_syn.prj
-#-- Written on Mon Dec 23 12:02:08 2013
+#-- Written on Wed Apr 9 12:12:25 2014
#project files
-add_file -constraint "/local/lemmens/lattice/soda/source/soda_source_clock_constraints.sdc"
-add_file -vhdl -lib work "/usr/local/diamond/2.2_x64/cae_library/synthesis/vhdl/ecp3.vhd"
+add_file -fpga_constraint "/local/lemmens/lattice/soda/source/soda_source_synconstraints.fdc"
+add_file -vhdl -lib work "/usr/local/diamond/3.1_x64/cae_library/synthesis/vhdl/ecp3.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/version.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_components.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_source.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_superburst_gen.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_builder.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_cmd_window_generator.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_d8crc8.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/med_ecp3_sfp_sync_down.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_handler.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_reply_pkt_builder.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_superburst_gen.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/med_ecp3_sfp_sync_up.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/serdes_sync_downstream.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_SOB_faker.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_calibration_timer.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_reply_handler.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/posedge_to_pulse.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_tx_control.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/trb3_components.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_buf.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC8.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/trb3_components.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/cores/pll_in200_out100.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_lvl1.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_data.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_ipu.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf5.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf6.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_encoder.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regIO.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_encoder.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_ibuf.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_ibuf.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_arbiter.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_pattern_gen.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_obuf.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/med_sync_define.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_control.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_base.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_func.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/trb3_periph_sodasource.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_logic.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_flash_and_fpga_reload.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
-add_file -fpga_constraint "./FDC_constraints/soda_source/soda_source_syn_translated.fdc"
+add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/trb3_periph_sodasource.vhd"
+
#implementation: "soda_source"
set_option -vlog_std v2001
set_option -project_relative_includes 1
-#set constraint files
-set_option -constraint -clear
-
#device options
set_option -technology LATTICE-ECP3
set_option -part LFE3_150EA
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-01-30">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-04-14">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_source"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2021438704" Name="trb3_periph_sodasource_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2031948738" Name="trb3_periph_sodasource_LA0" ID="0">
<Setting>
- <Clock SampleClk="rx_clock_full" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="512"/>
+ <Clock SampleClk="clk_raw_internal" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="1024"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_source_LA0_net"/>
</Setting>
<Dataset Name="Base">
<Trace>
- <Sig Type="SIG" Name="the_soda_source/store_rd"/>
- <Sig Type="SIG" Name="the_soda_source/store_rd_x"/>
- <Sig Type="SIG" Name="the_soda_source/store_wr"/>
- <Sig Type="SIG" Name="the_soda_source/store_wr_x"/>
- <Bus Name="the_soda_source/calib_register_s">
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:7"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:8"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:9"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:10"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:11"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:12"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:13"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:14"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:15"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:16"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:17"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:18"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:19"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:20"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:21"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:22"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:23"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:24"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:25"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:26"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:27"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:28"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:29"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:30"/>
- <Sig Type="SIG" Name="the_soda_source/calib_register_s:31"/>
+ <Bus Name="the_sync_link/start_timer">
+ <Sig Type="SIG" Name="the_sync_link/start_timer:0"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:1"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:2"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:3"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:4"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:5"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:6"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:7"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:8"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:9"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:10"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:11"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:12"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:13"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:14"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:15"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:16"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:17"/>
+ <Sig Type="SIG" Name="the_sync_link/start_timer:18"/>
</Bus>
- <Bus Name="the_soda_source/calibration_time_s">
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:7"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:8"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:9"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:10"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:11"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:12"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:13"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:14"/>
- <Sig Type="SIG" Name="the_soda_source/calibration_time_s:15"/>
+ <Bus Name="the_sync_link/the_tx/current_state">
+ <Sig Type="SIG" Name="the_sync_link/the_tx/current_state:0"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/current_state:1"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/current_state:2"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/current_state:3"/>
</Bus>
- <Sig Type="SIG" Name="the_soda_source/calibration_valid_s"/>
- <Bus Name="the_soda_source/current_state">
- <Sig Type="SIG" Name="the_soda_source/current_state:0"/>
- <Sig Type="SIG" Name="the_soda_source/current_state:1"/>
- <Sig Type="SIG" Name="the_soda_source/current_state:2"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/reset_in"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/rx_allow_qtx"/>
+ <Bus Name="the_sync_link/the_tx/tx_data_out">
+ <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:0"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:1"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:2"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:3"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:4"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:5"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:6"/>
+ <Sig Type="SIG" Name="the_sync_link/the_tx/tx_data_out:7"/>
</Bus>
- <Sig Type="SIG" Name="the_sync_link/watchdog_trigger"/>
- <Bus Name="the_sync_link/watchdog_timer">
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:0"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:1"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:2"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:3"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:4"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:5"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:6"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:7"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:8"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:9"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:10"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:11"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:12"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:13"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:14"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:15"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:16"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:17"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:18"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:19"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:20"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rst_n"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_cdr_lol_ch_s"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_los_low_ch_s"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_pcs_rst_ch_c"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/tx_pll_lol_qd_s"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_serdes_rst_ch_c"/>
- <Bus Name="the_sync_link/the_rx_fsm/state_out">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:3"/>
- </Bus>
- <Bus Name="the_sync_link/the_rx_fsm/wa_position">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/wa_position:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/wa_position:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/wa_position:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/wa_position:3"/>
+ <Sig Type="SIG" Name="the_sync_link/clear"/>
+ <Sig Type="SIG" Name="the_sync_link/sd_los_in"/>
+ <Sig Type="SIG" Name="the_sync_link/sd_txdis_out"/>
+ <Bus Name="sfp_los">
+ <Sig Type="SIG" Name="sfp_los:1"/>
+ <Sig Type="SIG" Name="sfp_los:2"/>
+ <Sig Type="SIG" Name="sfp_los:3"/>
+ <Sig Type="SIG" Name="sfp_los:4"/>
+ <Sig Type="SIG" Name="sfp_los:5"/>
+ <Sig Type="SIG" Name="sfp_los:6"/>
</Bus>
+ <Sig Type="SIG" Name="the_sync_link/rx_allow"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_allow"/>
<Bus Name="the_sync_link/rx_fsm_state">
<Sig Type="SIG" Name="the_sync_link/rx_fsm_state:0"/>
<Sig Type="SIG" Name="the_sync_link/rx_fsm_state:1"/>
<Sig Type="SIG" Name="the_sync_link/rx_fsm_state:2"/>
<Sig Type="SIG" Name="the_sync_link/rx_fsm_state:3"/>
</Bus>
- <Sig Type="SIG" Name="the_sync_link/rx_k"/>
- <Sig Type="SIG" Name="the_sync_link/rx_los_low"/>
- <Sig Type="SIG" Name="the_sync_link/rx_pcs_rst"/>
- <Sig Type="SIG" Name="the_sync_link/rx_serdes_rst"/>
- <Sig Type="SIG" Name="the_sync_link/rx_error"/>
- <Sig Type="SIG" Name="the_sync_link/tx_k"/>
- <Sig Type="SIG" Name="the_sync_link/tx_pcs_rst"/>
+ <Bus Name="the_sync_link/tx_fsm_state">
+ <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:0"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:1"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:2"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:3"/>
+ </Bus>
<Sig Type="SIG" Name="the_sync_link/tx_pll_lol"/>
- <Sig Type="SIG" Name="the_sync_link/tx_serdes_rst"/>
+ <Sig Type="SIG" Name="the_sync_link/link_phase_out"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_preview_in"/>
+ <Bus Name="the_sync_link/tx_data">
+ <Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:2"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:3"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:4"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:5"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:6"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:7"/>
+ </Bus>
+ <Bus Name="the_sync_link/tx_dlm_word">
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:0"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:1"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:2"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:3"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:4"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:5"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/tx_k"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_k"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
+ <Bus Name="the_sync_link/rx_data">
+ <Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:2"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:3"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:4"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:5"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
+ </Bus>
+ <Bus Name="the_sync_link/rx_dlm_word">
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:1"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:2"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:3"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:4"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:5"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
+ </Bus>
+ <Bus Name="the_sync_link/the_rx_fsm/cs">
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:0"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:1"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:2"/>
+ </Bus>
+ <Bus Name="the_sync_link/the_rx_fsm/ns">
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:0"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:1"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:2"/>
+ </Bus>
<Bus Name="the_sync_link/wa_position">
<Sig Type="SIG" Name="the_sync_link/wa_position:0"/>
<Sig Type="SIG" Name="the_sync_link/wa_position:1"/>
<Sig Type="SIG" Name="the_sync_link/wa_position:14"/>
<Sig Type="SIG" Name="the_sync_link/wa_position:15"/>
</Bus>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_strobe_s"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_strobe_sodaclk_s"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_pending_s"/>
- <Sig Type="SIG" Name="the_soda_source/soda_send_cmd_s"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_window_s"/>
+ <Bus Name="the_sync_link/wa_position_rx">
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:0"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:1"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:2"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:3"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:4"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:5"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:6"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:7"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:8"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:9"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:10"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:11"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:12"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:13"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:14"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:15"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_soda_source/start_calibration_s"/>
+ <Sig Type="SIG" Name="the_soda_source/start_of_superburst_s"/>
+ <Sig Type="SIG" Name="the_soda_source/tx_dlm_preview_out"/>
</Trace>
<Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="the_soda_source/store_rd,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="the_soda_source/store_wr,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="the_soda_source/start_calibration_s,"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_link/watchdog_trigger,"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
+ <TU Serialbits="0" Type="0" ID="1" Sig="the_sync_link/tx_k,"/>
+ <TU Serialbits="0" Type="0" ID="2" Sig="the_sync_link/start_timer:18,"/>
+ <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/lsm_status,"/>
+ <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_link/rx_error,"/>
+ <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
entity TB_soda_chain is
end entity;
-\r
-architecture TestBench of TB_soda_chain is\r
-\r
+
+architecture TestBench of TB_soda_chain is
+
-- Clock period definitions
constant sysclk_period: time:= 10ns;
constant sodaclk_period: time:= 5ns;
-\r
-\r
+
+
--Inputs
signal rst_S : std_logic;
signal sys_clk_S : std_logic;
signal soda_clk_S : std_logic;
signal enable_S : std_logic := '0';
signal SOB_S : std_logic := '0';
- signal src_dnstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');\r
- signal src_dnstream_dlm_valid_S : std_logic;\r
- signal src_upstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');\r
- signal src_upstream_dlm_valid_S : std_logic;\r
+ signal src_dnstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
+ signal src_dnstream_dlm_valid_S : std_logic;
+ signal src_upstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
+ signal src_upstream_dlm_valid_S : std_logic;
- signal hub_dnstream_dlm_word_S : t_HUB_DLM_WORD;\r
- signal hub_dnstream_dlm_valid_S : t_HUB_DLM;\r
- signal hub_upstream_dlm_word_S : t_HUB_DLM_WORD;\r
- signal hub_upstream_dlm_valid_S : t_HUB_DLM;\r
+ signal hub_dnstream_dlm_word_S : t_HUB_WORD;
+ signal hub_dnstream_dlm_valid_S : t_HUB_BIT;
+ signal hub_upstream_dlm_word_S : t_HUB_WORD;
+ signal hub_upstream_dlm_valid_S : t_HUB_BIT;
--SODA
signal soda_ack : std_logic;
signal soda_hub_data_out : std_logic_vector(31 downto 0);
signal soda_clt_data_out : std_logic_vector(31 downto 0);
signal soda_addr : std_logic_vector(3 downto 0) := (others => '0');
- signal soda_leds : std_logic_vector(3 downto 0);\r
+ signal soda_leds : std_logic_vector(3 downto 0);
begin
THE_SOB_SOURCE : soda_start_of_burst_faker
RESET => rst_S,
SODA_BURST_PULSE_OUT => SOB_S
);
-\r
-\r
+
+
THE_SODA_SOURCE : soda_source
port map(
SYSCLK => sys_clk_S,
SODA_ADDR_IN => soda_addr,
SODA_READ_IN => soda_read,
SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,\r
+ SODA_ACK_OUT => soda_ack,
LEDS_OUT => soda_leds
);
SODA_ADDR_IN => soda_addr,
SODA_READ_IN => soda_read,
SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,\r
+ SODA_ACK_OUT => soda_ack,
STAT => open
);
channel : for i in c_HUB_CHILDREN-1 downto 0 generate
-\r
+
A_SODA_CLIENT : soda_client
port map(
SYSCLK => sys_clk_S,
SODA_ADDR_IN => soda_addr,
SODA_READ_IN => soda_read,
SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,\r
+ SODA_ACK_OUT => soda_ack,
LEDS_OUT => open,
LINK_DEBUG_IN => (others => '0')
);
end generate;
-\r
+
------------------------------------------------------------------------------------------------------------
-- SODA command packet
------------------------------------------------------------------------------------------------------------
rst_S <= '0';
wait;
end process;
-\r
-end TestBench;\r
-\r
+
+end TestBench;
+
signal sci_state : sci_ctrl;
signal sci_timer : unsigned(12 downto 0) := (others => '0');
signal start_timer : unsigned(18 downto 0) := (others => '0');
-signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
-signal watchdog_trigger : std_logic :='0';
+--signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
+--signal watchdog_trigger : std_logic :='0';
begin
--rst_n <= not CLEAR; PL!\r
-rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+--rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger);
+--rst <= (CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger);
+rst_n <= not(CLEAR or internal_make_link_reset_out);
+rst <= (CLEAR or internal_make_link_reset_out);
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
rx_half_clk_ch0 => clk_rx_half,
tx_full_clk_ch0 => clk_tx_full,
tx_half_clk_ch0 => clk_tx_half,
- fpga_rxrefclk_ch0 => clk_200_internal,
+ fpga_rxrefclk_ch0 => clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT
txdata_ch0 => tx_data,
tx_k_ch0 => tx_k,
tx_force_disp_ch0 => '0',
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
- fpga_txrefclk => clk_200_i,
+ fpga_txrefclk => clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT
tx_serdes_rst_c => tx_serdes_rst,
tx_pll_lol_qd_s => tx_pll_lol,
rst_qd_c => rst_qd,
begin
if rising_edge(clk_200_i) then
if got_link_ready_i = '1' then
- watchdog_timer <= (others => '0');
+-- watchdog_timer <= (others => '0');
if start_timer(start_timer'left) = '0' then
start_timer <= start_timer + 1;
end if;
else
start_timer <= (others => '0');
- if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 1) = '1')) then
- watchdog_trigger <= '1';
- else
- watchdog_trigger <= '0';
- end if;
- if watchdog_trigger = '0' then
- watchdog_timer <= watchdog_timer + 1;
- else
- watchdog_timer <= (others => '0');
- end if;
+-- if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 1) = '1')) then
+-- watchdog_trigger <= '1';
+-- else
+-- watchdog_trigger <= '0';
+-- end if;
+-- if watchdog_trigger = '0' then
+-- watchdog_timer <= watchdog_timer + 1;
+-- else
+-- watchdog_timer <= (others => '0');
+-- end if;
end if;
end if;
end process;
attribute syn_keep of sci_write_shift_i : signal is true;
attribute syn_preserve of sci_read_shift_i : signal is true;
attribute syn_keep of sci_read_shift_i : signal is true;
-\r
+
signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
signal tx_allow : std_logic;
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
+--SD_TXDIS_OUT <= not (rx_allow_q or not IS_SYNC_SLAVE); --slave only switches on when RX is ready
+SD_TXDIS_OUT <= '0'; --not (rx_allow_q); --slave only switches on when RX is ready
--rst_n <= not CLEAR; PL!
-------------------------------------------------
-- Serdes
-------------------------------------------------
-THE_SERDES : entity work.serdes_sync_upstream
+THE_SERDES : entity work.serdes_sync_client_upstream
port map(
- hdinp_ch3 => SD_RXD_P_IN,
- hdinn_ch3 => SD_RXD_N_IN,
- hdoutp_ch3 => SD_TXD_P_OUT,
- hdoutn_ch3 => SD_TXD_N_OUT,
--- rxiclk_ch3 => clk_200_i, -- no more RX-fifo
- txiclk_ch3 => clk_200_i,
- rx_full_clk_ch3 => clk_rx_full,
- rx_half_clk_ch3 => clk_rx_half,
- tx_full_clk_ch3 => clk_tx_full,
- tx_half_clk_ch3 => clk_tx_half,
- fpga_rxrefclk_ch3 => clk_200_internal,
- txdata_ch3 => tx_data,
- tx_k_ch3 => tx_k,
- tx_force_disp_ch3 => '0',
- tx_disp_sel_ch3 => '0',
- rxdata_ch3 => rx_data,
- rx_k_ch3 => rx_k,
- rx_disp_err_ch3 => open,
- rx_cv_err_ch3 => rx_error,
- rx_serdes_rst_ch3_c => rx_serdes_rst,
- sb_felb_ch3_c => '0',
- sb_felb_rst_ch3_c => '0',
- tx_pcs_rst_ch3_c => tx_pcs_rst,
- tx_pwrup_ch3_c => '1',
- rx_pcs_rst_ch3_c => rx_pcs_rst,
- rx_pwrup_ch3_c => '1',
- rx_los_low_ch3_s => rx_los_low,
- lsm_status_ch3_s => lsm_status,
- rx_cdr_lol_ch3_s => rx_cdr_lol,
- tx_div2_mode_ch3_c => '0',
- rx_div2_mode_ch3_c => '0',
+ hdinp_ch0 => SD_RXD_P_IN,
+ hdinn_ch0 => SD_RXD_N_IN,
+ hdoutp_ch0 => SD_TXD_P_OUT,
+ hdoutn_ch0 => SD_TXD_N_OUT,
+-- rxiclk_ch0 => clk_200_i, -- no more RX-fifo
+ txiclk_ch0 => clk_200_i,
+ rx_full_clk_ch0 => clk_rx_full,
+ rx_half_clk_ch0 => clk_rx_half,
+ tx_full_clk_ch0 => clk_tx_full,
+ tx_half_clk_ch0 => clk_tx_half,
+ fpga_rxrefclk_ch0 => clk_200_internal,
+ txdata_ch0 => tx_data,
+ tx_k_ch0 => tx_k,
+ tx_force_disp_ch0 => '0',
+ tx_disp_sel_ch0 => '0',
+ rxdata_ch0 => rx_data,
+ rx_k_ch0 => rx_k,
+ rx_disp_err_ch0 => open,
+ rx_cv_err_ch0 => rx_error,
+ rx_serdes_rst_ch0_c => rx_serdes_rst,
+ sb_felb_ch0_c => '0',
+ sb_felb_rst_ch0_c => '0',
+ tx_pcs_rst_ch0_c => tx_pcs_rst,
+ tx_pwrup_ch0_c => '1',
+ rx_pcs_rst_ch0_c => rx_pcs_rst,
+ rx_pwrup_ch0_c => '1',
+ rx_los_low_ch0_s => rx_los_low,
+ lsm_status_ch0_s => lsm_status,
+ rx_cdr_lol_ch0_s => rx_cdr_lol,
+ tx_div2_mode_ch0_c => '0',
+ rx_div2_mode_ch0_c => '0',
SCI_WRDATA => sci_data_in_i,
SCI_RDDATA => sci_data_out_i,
SCI_ADDR => sci_addr_i(5 downto 0),
SCI_SEL_QUAD => sci_qd_i,
- SCI_SEL_CH3 => sci_ch_i(0),
+ SCI_SEL_ch0 => sci_ch_i(0),
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
tx_allow_q <= tx_allow when rising_edge(SYSCLK);
-PROC_START_TIMER : process(clk_200_i)\r
-begin\r
+PROC_START_TIMER : process(clk_200_i)
+begin
if rising_edge(clk_200_i) then
- if got_link_ready_i = '1' then\r
+ if got_link_ready_i = '1' then
watchdog_timer <= (others => '0');
if start_timer(start_timer'left) = '0' then
start_timer <= start_timer + 1;
end if;
else
- start_timer <= (others => '0');\r
- if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then\r
- watchdog_trigger <= '1';\r
+ start_timer <= (others => '0');
+ if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then
+ watchdog_trigger <= '1';
else
- watchdog_trigger <= '0';\r
+ watchdog_trigger <= '0';
end if;
- if watchdog_trigger = '0' then\r
- watchdog_timer <= watchdog_timer + 1;\r
- else \r
+ if watchdog_trigger = '0' then
+ watchdog_timer <= watchdog_timer + 1;
+ else
watchdog_timer <= (others => '0');
- end if;\r
- end if;\r
+ end if;
+ end if;
end if;
end process;
STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
STAT_OP(14) <= '0';
STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset
-STAT_OP(12) <= '0';
-STAT_OP(11) <= '0';
+STAT_OP(12) <= tx_pll_lol; --'0';
+STAT_OP(11) <= rx_cdr_lol; --'0';
STAT_OP(10) <= rx_allow;
STAT_OP(9) <= tx_allow;
--STAT_OP(8 downto 4) <= (others => '0');
STAT_OP(5) <= request_retr_i;
STAT_OP(4) <= start_retr_i;
STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-end med_ecp3_sfp_sync_up_arch;
-
+end med_ecp3_sfp_sync_up_arch;
\ No newline at end of file
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 02 20 15:49:26.247" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 07 16:16:02.152" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 02 20 15:47:38.000"/>
- <File name="serdes_sync_downstream.pp" type="pp" modified="2014 02 20 15:47:38.000"/>
- <File name="serdes_sync_downstream.sym" type="sym" modified="2014 02 20 15:47:38.000"/>
- <File name="serdes_sync_downstream.tft" type="tft" modified="2014 02 20 15:47:38.000"/>
- <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 02 20 15:47:38.000"/>
- <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 02 20 15:47:38.000"/>
+ <File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 04 07 16:16:00.000"/>
+ <File name="serdes_sync_downstream.pp" type="pp" modified="2014 04 07 16:16:00.000"/>
+ <File name="serdes_sync_downstream.sym" type="sym" modified="2014 04 07 16:16:00.000"/>
+ <File name="serdes_sync_downstream.tft" type="tft" modified="2014 04 07 16:16:00.000"/>
+ <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 04 07 16:16:00.000"/>
+ <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 04 07 16:16:00.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=02/20/2014
-Time=15:47:38
+Date=04/07/2014
+Time=16:16:00
[Parameters]
Verilog=0
_tx_data_width2=8
_tx_data_width3=8
_tx_fifo0=DISABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
+_tx_fifo1=DISABLED
+_tx_fifo2=DISABLED
+_tx_fifo3=DISABLED
_tx_ficlk_rate0=200
_tx_ficlk_rate1=200
_tx_ficlk_rate2=200
_tx_ficlk_rate3=200
_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=INTERNAL
+_pll_rxsrc3=INTERNAL
Multiplier0=
Multiplier1=
Multiplier2=
_rx_data_width2=8
_rx_data_width3=8
_rx_fifo0=DISABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
+_rx_fifo1=DISABLED
+_rx_fifo2=DISABLED
+_rx_fifo3=DISABLED
_rx_ficlk_rate0=200
_rx_ficlk_rate1=250.0
_rx_ficlk_rate2=250.0
_rterm_rx2=50
_rterm_rx3=50
_rx_dcc0=DC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=AC
+_rx_dcc1=DC
+_rx_dcc2=DC
+_rx_dcc3=DC
_los_threshold_mode0=LOS_E
_los_threshold_mode1=LOS_E
_los_threshold_mode2=LOS_E
DEVICE_NAME "LFE3-150EA"
CH0_PROTOCOL "G8B10B"
-CH1_PROTOCOL "G8B10B"
-CH2_PROTOCOL "G8B10B"
-CH3_PROTOCOL "G8B10B"
CH0_MODE "RXTX"
-CH1_MODE "RXTX"
-CH2_MODE "RXTX"
-CH3_MODE "RXTX"
+CH1_MODE "DISABLED"
+CH2_MODE "DISABLED"
+CH3_MODE "DISABLED"
CH0_CDR_SRC "REFCLK_CORE"
-CH1_CDR_SRC "REFCLK_CORE"
-CH2_CDR_SRC "REFCLK_CORE"
-CH3_CDR_SRC "REFCLK_CORE"
PLL_SRC "REFCLK_CORE"
TX_DATARATE_RANGE "MEDHIGH"
CH0_RX_DATARATE_RANGE "MEDHIGH"
-CH1_RX_DATARATE_RANGE "MEDHIGH"
-CH2_RX_DATARATE_RANGE "MEDHIGH"
-CH3_RX_DATARATE_RANGE "MEDHIGH"
REFCK_MULT "10X"
#REFCLK_RATE 200
CH0_RX_DATA_RATE "FULL"
-CH1_RX_DATA_RATE "FULL"
-CH2_RX_DATA_RATE "FULL"
-CH3_RX_DATA_RATE "FULL"
CH0_TX_DATA_RATE "FULL"
-CH1_TX_DATA_RATE "FULL"
-CH2_TX_DATA_RATE "FULL"
-CH3_TX_DATA_RATE "FULL"
CH0_TX_DATA_WIDTH "8"
-CH1_TX_DATA_WIDTH "8"
-CH2_TX_DATA_WIDTH "8"
-CH3_TX_DATA_WIDTH "8"
CH0_RX_DATA_WIDTH "8"
-CH1_RX_DATA_WIDTH "8"
-CH2_RX_DATA_WIDTH "8"
-CH3_RX_DATA_WIDTH "8"
CH0_TX_FIFO "DISABLED"
-CH1_TX_FIFO "ENABLED"
-CH2_TX_FIFO "ENABLED"
-CH3_TX_FIFO "ENABLED"
CH0_RX_FIFO "DISABLED"
-CH1_RX_FIFO "DISABLED"
-CH2_RX_FIFO "DISABLED"
-CH3_RX_FIFO "DISABLED"
CH0_TDRV "0"
-CH1_TDRV "0"
-CH2_TDRV "0"
-CH3_TDRV "0"
#CH0_TX_FICLK_RATE 200
-#CH1_TX_FICLK_RATE 200
-#CH2_TX_FICLK_RATE 200
-#CH3_TX_FICLK_RATE 200
#CH0_RXREFCLK_RATE "200"
-#CH1_RXREFCLK_RATE "200"
-#CH2_RXREFCLK_RATE "200"
-#CH3_RXREFCLK_RATE "200"
#CH0_RX_FICLK_RATE 200
-#CH1_RX_FICLK_RATE 200
-#CH2_RX_FICLK_RATE 200
-#CH3_RX_FICLK_RATE 200
CH0_TX_PRE "DISABLED"
-CH1_TX_PRE "DISABLED"
-CH2_TX_PRE "DISABLED"
-CH3_TX_PRE "DISABLED"
CH0_RTERM_TX "50"
-CH1_RTERM_TX "50"
-CH2_RTERM_TX "50"
-CH3_RTERM_TX "50"
CH0_RX_EQ "DISABLED"
-CH1_RX_EQ "DISABLED"
-CH2_RX_EQ "DISABLED"
-CH3_RX_EQ "DISABLED"
CH0_RTERM_RX "50"
-CH1_RTERM_RX "50"
-CH2_RTERM_RX "50"
-CH3_RTERM_RX "50"
CH0_RX_DCC "DC"
-CH1_RX_DCC "DC"
-CH2_RX_DCC "DC"
-CH3_RX_DCC "DC"
CH0_LOS_THRESHOLD_LO "2"
-CH1_LOS_THRESHOLD_LO "2"
-CH2_LOS_THRESHOLD_LO "2"
-CH3_LOS_THRESHOLD_LO "2"
PLL_TERM "50"
PLL_DCC "AC"
PLL_LOL_SET "0"
CH0_TX_SB "DISABLED"
-CH1_TX_SB "DISABLED"
-CH2_TX_SB "DISABLED"
-CH3_TX_SB "DISABLED"
CH0_RX_SB "DISABLED"
-CH1_RX_SB "DISABLED"
-CH2_RX_SB "DISABLED"
-CH3_RX_SB "DISABLED"
CH0_TX_8B10B "ENABLED"
-CH1_TX_8B10B "ENABLED"
-CH2_TX_8B10B "ENABLED"
-CH3_TX_8B10B "ENABLED"
CH0_RX_8B10B "ENABLED"
-CH1_RX_8B10B "ENABLED"
-CH2_RX_8B10B "ENABLED"
-CH3_RX_8B10B "ENABLED"
CH0_COMMA_A "1100000101"
-CH1_COMMA_A "1100000101"
-CH2_COMMA_A "1100000101"
-CH3_COMMA_A "1100000101"
CH0_COMMA_B "0011111010"
-CH1_COMMA_B "0011111010"
-CH2_COMMA_B "0011111010"
-CH3_COMMA_B "0011111010"
CH0_COMMA_M "1111111100"
-CH1_COMMA_M "1111111100"
-CH2_COMMA_M "1111111100"
-CH3_COMMA_M "1111111100"
CH0_RXWA "ENABLED"
-CH1_RXWA "ENABLED"
-CH2_RXWA "ENABLED"
-CH3_RXWA "ENABLED"
CH0_ILSM "ENABLED"
-CH1_ILSM "ENABLED"
-CH2_ILSM "ENABLED"
-CH3_ILSM "ENABLED"
CH0_CTC "DISABLED"
-CH1_CTC "DISABLED"
-CH2_CTC "DISABLED"
-CH3_CTC "DISABLED"
CH0_CC_MATCH4 "0100011100"
-CH1_CC_MATCH4 "0100011100"
-CH2_CC_MATCH4 "0100011100"
-CH3_CC_MATCH4 "0100011100"
CH0_CC_MATCH_MODE "1"
-CH1_CC_MATCH_MODE "1"
-CH2_CC_MATCH_MODE "1"
-CH3_CC_MATCH_MODE "1"
CH0_CC_MIN_IPG "3"
-CH1_CC_MIN_IPG "3"
-CH2_CC_MIN_IPG "3"
-CH3_CC_MIN_IPG "3"
CCHMARK "9"
CCLMARK "7"
CH0_SSLB "DISABLED"
-CH1_SSLB "DISABLED"
-CH2_SSLB "DISABLED"
-CH3_SSLB "DISABLED"
CH0_SPLBPORTS "DISABLED"
-CH1_SPLBPORTS "DISABLED"
-CH2_SPLBPORTS "DISABLED"
-CH3_SPLBPORTS "DISABLED"
CH0_PCSLBPORTS "DISABLED"
-CH1_PCSLBPORTS "DISABLED"
-CH2_PCSLBPORTS "DISABLED"
-CH3_PCSLBPORTS "DISABLED"
INT_ALL "DISABLED"
QD_REFCK2CORE "ENABLED"
-- CONFIG_FILE : String := "serdes_sync_downstream.txt";
-- QUAD_MODE : String := "SINGLE";
-- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
+-- CH1_CDR_SRC : String := "REFCLK_CORE";
+-- CH2_CDR_SRC : String := "REFCLK_CORE";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
-- PLL_SRC : String := "REFCLK_CORE"
);
port (
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 02 05 09:13:24.083" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 03 20 10:34:14.620" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 02 05 09:13:21.000"/>
- <File name="serdes_sync_upstream.pp" type="pp" modified="2014 02 05 09:13:21.000"/>
- <File name="serdes_sync_upstream.sym" type="sym" modified="2014 02 05 09:13:21.000"/>
- <File name="serdes_sync_upstream.tft" type="tft" modified="2014 02 05 09:13:21.000"/>
- <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 02 05 09:13:21.000"/>
- <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 02 05 09:13:21.000"/>
+ <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 02 25 13:39:52.000"/>
+ <File name="serdes_sync_upstream.pp" type="pp" modified="2014 02 25 13:39:52.000"/>
+ <File name="serdes_sync_upstream.sym" type="sym" modified="2014 02 25 13:39:53.000"/>
+ <File name="serdes_sync_upstream.tft" type="tft" modified="2014 02 25 13:39:52.000"/>
+ <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 02 25 13:39:52.000"/>
+ <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 02 25 13:39:52.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_upstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=02/05/2014
-Time=09:13:21
+Date=02/25/2014
+Time=13:39:52
[Parameters]
Verilog=0
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; \r
+use work.trb_net16_hub_func.all;
use work.soda_components.all;
entity soda_start_of_burst_faker is
constant c_PHASE_L : std_logic := '0'; -- byt2word allignment of soda
constant c_PHASE_H : std_logic := '1'; -- byt2word allignment of soda
- constant c_HUB_CHILDREN : natural range 1 to 4 := 2; -- number of children per soda-hub
+ constant c_HUB_CHILDREN : natural range 1 to 4 := 4; -- number of children per soda-hub
constant cSODA_CLOCK_PERIOD : natural range 1 to 20 := 5; -- soda clock-period in ns
+ constant cSYS_CLOCK_PERIOD : natural range 1 to 20 := 10; -- soda clock-period in ns
constant cBURST_PERIOD : natural := 2400; -- particle-beam burst-period in ns
constant cSODA_COMMAND_WINDOS_SIZE : natural range 1 to 65535 := 5000; -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns
constant cWINDOW_delay : std_logic_vector(7 downto 0) := conv_std_logic_vector(28, 8); -- in clock-cycles
constant cCLOCKS_PER_WINDOW : std_logic_vector(15 downto 0) := conv_std_logic_vector((cSODA_COMMAND_WINDOS_SIZE / cSODA_CLOCK_PERIOD) - 1, 16); -- in clock-cycles
+ constant c_QUAD_DATA_WIDTH : integer := 4*c_DATA_WIDTH;
+ constant c_QUAD_NUM_WIDTH : integer := 4*c_NUM_WIDTH;
+ constant c_QUAD_MUX_WIDTH : integer := 3; --!!!
+
+ subtype t_HUB_BIT is std_logic_vector(c_HUB_CHILDREN-1 downto 0);
+ type t_HUB_NUM is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ type t_HUB_NIBL is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(3 downto 0);
+ type t_HUB_BYTE is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0);
+ type t_HUB_WORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0);
+ type t_HUB_LWORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0);
+
+ type t_HUB_TIMER13 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(12 downto 0);
+ type t_HUB_TIMER19 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(18 downto 0);
+ type t_HUB_TIMER21 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(20 downto 0);
- type t_HUB_DLM is array(c_HUB_CHILDREN-1 downto 0) of std_logic;
- type t_HUB_DLM_BYTE is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0);
- type t_HUB_DLM_WORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0);
- type t_HUB_DLM_LWORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0);
type t_PACKET_TYPE_SENT is (c_NO_PACKET, c_CMD_PACKET, c_BST_PACKET);
type t_PACKET_TYPE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of t_PACKET_TYPE_SENT;
- type t_HUB_BIT_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic;
+
+ subtype t_HUB_BIT_ARRAY is std_logic_vector(c_HUB_CHILDREN-1 downto 0);
type t_HUB_BYTE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0);
type t_HUB_WORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0);
type t_HUB_LWORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0);
- type t_QUAD_BIT is array(3 downto 0) of std_logic;
+ subtype t_QUAD_BIT is std_logic_vector(3 downto 0);
type t_QUAD_NIBL is array(3 downto 0) of std_logic_vector(3 downto 0);
type t_QUAD_BYTE is array(3 downto 0) of std_logic_vector(7 downto 0);
type t_QUAD_9WORD is array(3 downto 0) of std_logic_vector(8 downto 0);
SODA_READ_IN : in std_logic := '0';
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
- LEDS_OUT : out std_logic_vector(3 downto 0)
+ LEDS_OUT : out std_logic_vector(3 downto 0)
);
end component;
UPLINK_PHASE_IN : in std_logic := '0'; --PL!
-- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
- RXDN_DLM_IN : in t_HUB_DLM;
- RXDN_DLM_WORD_IN : in t_HUB_DLM_BYTE;
- TXDN_DLM_OUT : out t_HUB_DLM;
- TXDN_DLM_WORD_OUT : out t_HUB_DLM_BYTE;
- TXDN_DLM_PREVIEW_OUT : out t_HUB_DLM; --PL!
- DNLINK_PHASE_IN : in t_HUB_DLM; --PL!
+ RXDN_DLM_IN : in t_HUB_BIT;
+ RXDN_DLM_WORD_IN : in t_HUB_BYTE;
+ TXDN_DLM_OUT : out t_HUB_BIT;
+ TXDN_DLM_WORD_OUT : out t_HUB_BYTE;
+ TXDN_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL!
+ DNLINK_PHASE_IN : in t_HUB_BIT; --PL!
SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
PULSE_OUT : out std_logic
);
end component;
-
+
component med_ecp3_sfp_sync_down is
generic(
SERDES_NUM : integer range 0 to 3 := 0;
LINK_PHASE_OUT : out std_logic := '0'; --PL!
--SFP Connection
- SD_RXD_P_IN : in t_QUAD_BIT;
- SD_RXD_N_IN : in t_QUAD_BIT;
- SD_TXD_P_OUT : out t_QUAD_BIT;
- SD_TXD_N_OUT : out t_QUAD_BIT;
- SD_REFCLK_P_IN : in t_QUAD_BIT; --not used
- SD_REFCLK_N_IN : in t_QUAD_BIT; --not used
- SD_PRSNT_N_IN : in t_QUAD_BIT; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in t_QUAD_BIT; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out t_QUAD_BIT := (others => '0'); -- SFP disable
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
--Control Interface
SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
);
end component;
+
+component med_ecp3_sfp_4_sync_down is
+ generic( SERDES_NUM : integer range 0 to 3 := 0;
+ IS_SYNC_SLAVE : integer := c_NO); --select slave mode
+ port(
+ CLK : in std_logic; -- _internal_ 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ --Internal Connection TX
+ MED_DATA_IN : in t_HUB_WORD; --std_logic_vector(c_QUAD_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in t_HUB_NUM; --std_logic_vector(c_QUAD_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
+ MED_READ_OUT : out std_logic_vector(3 downto 0) := (others => '0');
+ --Internal Connection RX
+ MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0');
+ MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0');
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0');
+ MED_READ_IN : in std_logic_vector(3 downto 0);
+
+ CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+
+ --Sync operation
+ RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
+ RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
+ TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
+ TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
+ TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
+ LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN : in t_HUB_BIT; --std_logic;
+ SD_RXD_N_IN : in t_HUB_BIT; --std_logic;
+ SD_TXD_P_OUT : out t_HUB_BIT; --std_logic;
+ SD_TXD_N_OUT : out t_HUB_BIT; --std_logic;
+ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
+ CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
+end component;
+
+
component med_ecp3_sfp_sync_up is
generic(
SERDES_NUM : integer range 0 to 3 := 0;
SODA_CMD_WINDOW_OUT : out std_logic := '0'
);
end component;
+\r
+component soda_clockscaler is
+ port(
+ CLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLOCK_ENABLE_OUT : out std_logic := '0';\r
+ CLOCK_OUT : out std_logic
+ );
+end component;\r
end package;
\ No newline at end of file
entity soda_hub is
port(
- SYSCLK : in std_logic; -- fabric clock
- SODACLK : in std_logic; -- recovered clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
+ SYSCLK : in std_logic; -- fabric clock
+ SODACLK : in std_logic; -- recovered clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
-- SINGLE DUBPLEX UP-LINK TO THE TOP
RXUP_DLM_IN : in std_logic;
RXUP_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
- TXUP_DLM_OUT : out std_logic;
+ TXUP_DLM_OUT : out std_logic;
TXUP_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
TXUP_DLM_PREVIEW_OUT : out std_logic := '0'; --PL!
- UPLINK_PHASE_IN : in std_logic := '0'; --PL!
+ UPLINK_PHASE_IN : in std_logic := '0'; --PL!
\r
-- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
- RXDN_DLM_IN : in t_HUB_DLM;
- RXDN_DLM_WORD_IN : in t_HUB_DLM_BYTE;
- TXDN_DLM_OUT : out t_HUB_DLM;
- TXDN_DLM_WORD_OUT : out t_HUB_DLM_BYTE;
- TXDN_DLM_PREVIEW_OUT : out t_HUB_DLM; --PL!
- DNLINK_PHASE_IN : in t_HUB_DLM; --PL!
+ RXDN_DLM_IN : in t_HUB_BIT;
+ RXDN_DLM_WORD_IN : in t_HUB_BYTE;
+ TXDN_DLM_OUT : out t_HUB_BIT;
+ TXDN_DLM_WORD_OUT : out t_HUB_BYTE;
+ TXDN_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL!
+ DNLINK_PHASE_IN : in t_HUB_BIT; --PL!
- SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
- SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
- SODA_READ_IN : in std_logic := '0';
+ SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
+ SODA_READ_IN : in std_logic := '0';
SODA_WRITE_IN : in std_logic := '0';
- SODA_ACK_OUT : out std_logic := '0';
- LEDS_OUT : out std_logic_vector(3 downto 0);\r
+ SODA_ACK_OUT : out std_logic := '0';
+ LEDS_OUT : out std_logic_vector(3 downto 0);\r
LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
);
end soda_hub;
\r
hub_reply_packet_builder : soda_reply_pkt_builder \r
port map(
- SODACLK => SODACLK,
- RESET => RESET,
- CLEAR => '0',
- CLK_EN => CLK_EN,
+ SODACLK => SODACLK,
+ RESET => RESET,
+ CLEAR => '0',
+ CLK_EN => CLK_EN,
--Internal Connection
LINK_PHASE_IN => UPLINK_PHASE_IN,\r
START_OF_SUPERBURST => start_of_superburst_S,
SUPER_BURST_NR_IN => super_burst_nr_S,
- SODA_CMD_STROBE_IN => soda_cmd_valid_S,
+ SODA_CMD_STROBE_IN => soda_cmd_valid_S,
SODA_CMD_WORD_IN => soda_cmd_word_S,
- TX_DLM_PREVIEW_OUT => TXUP_DLM_PREVIEW_OUT,
- TX_DLM_OUT => txup_dlm_out_S, --TX_DLM_OUT,
- TX_DLM_WORD_OUT => TXUP_DLM_WORD_OUT
+ TX_DLM_PREVIEW_OUT => TXUP_DLM_PREVIEW_OUT,
+ TX_DLM_OUT => txup_dlm_out_S, --TX_DLM_OUT,
+ TX_DLM_WORD_OUT => TXUP_DLM_WORD_OUT
);
\r
channel :for i in c_HUB_CHILDREN-1 downto 0 generate
\r
packet_builder : soda_packet_builder
port map(
- SODACLK => SODACLK,
- RESET => RESET,
+ SODACLK => SODACLK,
+ RESET => RESET,
--Internal Connection
SODA_CMD_STROBE_IN => soda_cmd_valid_S,
START_OF_SUPERBURST => start_of_superburst_S,
SUPER_BURST_NR_IN => super_burst_nr_S,
SODA_CMD_WORD_IN => soda_cmd_word_S,
- EXPECTED_REPLY_OUT => open,
- TIME_CAL_OUT => open, --start_calibration_S(i),
- TX_DLM_OUT => TXDN_DLM_OUT(i),
- TX_DLM_WORD_OUT => TXDN_DLM_WORD_OUT(i)
+ EXPECTED_REPLY_OUT => open,
+ TIME_CAL_OUT => open, --start_calibration_S(i),
+ TX_DLM_PREVIEW_OUT => TXDN_DLM_PREVIEW_OUT(i),
+ TX_DLM_OUT => TXDN_DLM_OUT(i),
+ TX_DLM_WORD_OUT => TXDN_DLM_WORD_OUT(i)
);
hub_reply_handler : soda_reply_handler
SODA_DATA_OUT <= buf_bus_data_out;
SODA_ACK_OUT <= bus_ack;
-end architecture;
\ No newline at end of file
+end architecture;
----------------\r
--- TOP LEVEL --\r
---------------
-\r
+-- TOP LEVEL --
+---------------
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
signal sci1_data_out : std_logic_vector(7 downto 0);
signal sci1_addr : std_logic_vector(8 downto 0);
signal sci1_nack : std_logic;
+ signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
+
--SODA
signal soda_rx_clock_half : std_logic;
signal general_reset_i : std_logic := '1';
signal soda_counter_i : unsigned(3 downto 0);
- attribute syn_keep of soda_counter_i : signal is true;\r
+ attribute syn_keep of soda_counter_i : signal is true;
-- fix signal names for constraining
attribute syn_preserve of soda_rx_clock_full : signal is true;
attribute syn_keep of soda_rx_clock_full : signal is true;
---------------------------------------------------------------------------
-- Reset Generation
---------------------------------------------------------------------------
-\r
-\r
- TEST_LINE <= (others => '0'); -- otherwise it is floating\r
+
+
+ TEST_LINE <= (others => '0'); -- otherwise it is floating
LED_RX <= (others => '0'); -- otherwise it is floating
LED_TX <= (others => '0'); -- otherwise it is floating
LED_LINKOK <= (others => '0'); -- otherwise it is floating
- \r
+
GSR_N <= pll_lock;
THE_RESET_HANDLER : trb_net_reset_handler
SD_REFCLK_N_IN => '0',
SD_PRSNT_N_IN => SFP_MOD0(1),
SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => SFP_TXDIS(1),
+ SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),
SCI_DATA_IN => sci1_data_in,
SCI_DATA_OUT => sci1_data_out,
);
+-- SFP_TXDIS(1) <= sfp_txdis_S(1);
+ SFP_TXDIS <= sfp_txdis_S;
+
---------------------------------------------------------------------------
-- The Soda Central
---------------------------------------------------------------------------
-\r
+
A_SODA_CLIENT : soda_client
port map(
- SYSCLK => clk_sys_internal, --clk_sys_i,\r
+ SYSCLK => clk_sys_internal, --clk_sys_i,
SODACLK => clk_soda_i,
RESET => reset_i,
CLEAR => clear_i,
SODA_READ_IN => soda_read,
SODA_WRITE_IN => soda_write,
SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds,\r
+ LEDS_OUT => soda_leds,
LINK_DEBUG_IN => link_debug_in_S
);
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
- LED_ORANGE <= med_stat_op(8);
- LED_YELLOW <= med_stat_op(10);
- LED_GREEN <= med_stat_op(9);
- LED_RED <= med_stat_op(6);
+ LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);
+ LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);
+ LED_GREEN <= med_stat_op(12); --tx_pll_lol
+ LED_RED <= med_stat_op(11); --rx_cdr_lol
-- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
-- LED_YELLOW <= soda_leds(0); --'1';
-- LED_GREEN <= not med_stat_op(9);
-- LED_RED <= soda_leds(3);
---------------------------------------------------------------------------
--- DEBUG\r
+-- DEBUG
---------------------------------------------------------------------------
link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0);
link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0');
-- Test Circuits
---------------------------------------------------------------------------
clock_counter_proc : process(clk_sys_internal)
- begin\r
+ begin
if rising_edge(clk_sys_internal) then
- time_counter <= time_counter + 1;\r
+ time_counter <= time_counter + 1;
end if;
end process;
end process;
-end trb3_periph_sodaclient_arch;
+end trb3_periph_sodaclient_arch;
\ No newline at end of file
);
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of LED_LINKOK : signal is false;
- attribute syn_useioff of LED_TX : signal is false;
- attribute syn_useioff of LED_RX : signal is false;
- attribute syn_useioff of SFP_MOD0 : signal is false;
- attribute syn_useioff of SFP_TXDIS : signal is false;
- attribute syn_useioff of SFP_LOS : signal is false;
- attribute syn_useioff of TEST_LINE : signal is false;
-
- --important signals _with_ IO-FF
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of LED_LINKOK : signal is false;
+ attribute syn_useioff of LED_TX : signal is false;
+ attribute syn_useioff of LED_RX : signal is false;
+ attribute syn_useioff of SFP_MOD0 : signal is false;
+ attribute syn_useioff of SFP_TXDIS : signal is false;
+ attribute syn_useioff of SFP_LOS : signal is false;
+ attribute syn_useioff of TEST_LINE : signal is false;
+
+ --important signals _with_ IO-FF
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
end entity;
architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-
- --Clock / Reset
--- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
--- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- signal clk_sys_internal : std_logic;
- signal clk_raw_internal : std_logic;
- signal rx_clock_half : std_logic;
- signal rx_clock_full : std_logic;
- signal clk_tdc : std_logic;
- signal time_counter, time_counter2 : unsigned(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sci2_ack : std_logic;
- signal sci2_nack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 0;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
+
+ --Clock / Reset
+ -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ signal clk_sys_internal : std_logic;
+ signal clk_raw_internal : std_logic;
+ signal rx_clock_half : std_logic;
+ signal rx_clock_full : std_logic;
+ signal clk_tdc : std_logic;
+ signal time_counter, time_counter2 : unsigned(31 downto 0);
+ --Media Interface
+ signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(8 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_dataready_out : std_logic;
+ signal spimem_no_more_data_out : std_logic;
+ signal spimem_unknown_addr_out : std_logic;
+ signal spimem_write_ack_out : std_logic;
+
+ signal sci1_ack : std_logic;
+ signal sci1_write : std_logic;
+ signal sci1_read : std_logic;
+ signal sci1_data_in : std_logic_vector(7 downto 0);
+ signal sci1_data_out : std_logic_vector(7 downto 0);
+ signal sci1_addr : std_logic_vector(8 downto 0);
+ signal sci2_ack : std_logic;
+ signal sci2_nack : std_logic;
+ signal sci2_write : std_logic;
+ signal sci2_read : std_logic;
+ signal sci2_data_in : std_logic_vector(7 downto 0);
+ signal sci2_data_out : std_logic_vector(7 downto 0);
+ signal sci2_addr : std_logic_vector(8 downto 0);
+ signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
--SODA
signal soda_ack : std_logic;
signal soda_data_out : std_logic_vector(31 downto 0);
signal soda_addr : std_logic_vector(3 downto 0);
signal soda_leds : std_logic_vector(3 downto 0);
-\r
+
--TDC
- signal hit_in_i : std_logic_vector(63 downto 0);
-
- signal soda_rx_clock_half : std_logic;
- signal soda_rx_clock_full : std_logic;
- signal soda_tx_clock_half : std_logic;
- signal soda_tx_clock_full : std_logic;
- signal tx_dlm_i : std_logic;
- signal rx_dlm_i : std_logic;
- signal tx_dlm_word : std_logic_vector(7 downto 0);
- signal rx_dlm_word : std_logic_vector(7 downto 0);
+ signal hit_in_i : std_logic_vector(63 downto 0);
+
+ signal soda_rx_clock_half : std_logic;
+ signal soda_rx_clock_full : std_logic;
+ signal soda_tx_clock_half : std_logic;
+ signal soda_tx_clock_full : std_logic;
+ signal tx_dlm_i : std_logic;
+ signal rx_dlm_i : std_logic;
+ signal tx_dlm_word : std_logic_vector(7 downto 0);
+ signal rx_dlm_word : std_logic_vector(7 downto 0);
signal tx_dlm_preview_S : std_logic; --PL!
signal link_phase_S : std_logic; --PL!
attribute syn_preserve of CLK_PCLK_RIGHT : signal is true;
attribute syn_keep of CLK_PCLK_RIGHT : signal is true;
-- attribute syn_noprune of CLK_PCLK_RIGHT : signal is true;
-\r
+
attribute syn_preserve of soda_rx_clock_full : signal is true;
attribute syn_keep of soda_rx_clock_full : signal is true;
attribute syn_preserve of soda_rx_clock_half : signal is true;
MED_DATAREADY_OUT => med_dataready_in(0),
MED_READ_IN => med_read_out(0),
REFCLK2CORE_OUT => open,
- CLK_RX_HALF_OUT => rx_clock_half,
- CLK_RX_FULL_OUT => rx_clock_full,
+ CLK_RX_HALF_OUT => open, --rx_clock_half,
+ CLK_RX_FULL_OUT => open, --rx_clock_full,
--SFP Connection
SD_RXD_P_IN => SERDES_ADDON_RX(2),
CLK => clk_raw_internal, --clk_200_i,
SYSCLK => clk_sys_internal, --clk_sys_i,
RESET => reset_i,
- CLEAR => clear_i,\r
--- PCSA_REFCLKP => PCSA_REFCLKP, -- external refclock straight into serdes PL!\r
+ CLEAR => clear_i,
+-- PCSA_REFCLKP => PCSA_REFCLKP, -- external refclock straight into serdes PL!
-- PCSA_REFCLKN => PCSA_REFCLKN, -- external refclock straight into serdes PL!
--Internal Connection for TrbNet data -> not used a.t.m.
MED_DATA_IN => med_data_out(31 downto 16),
RX_DLM => rx_dlm_i,
RX_DLM_WORD => rx_dlm_word,
TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,\r
- TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!\r
- LINK_PHASE_OUT => link_phase_S, --PL!
+ TX_DLM_WORD => tx_dlm_word,
+ TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
+ LINK_PHASE_OUT => link_phase_S, --PL!
--SFP Connection
SD_RXD_P_IN => SERDES_ADDON_RX(0),
SD_RXD_N_IN => SERDES_ADDON_RX(1),
SD_REFCLK_N_IN => '0',
SD_PRSNT_N_IN => SFP_MOD0(1),
SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => SFP_TXDIS(1),
+ SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),
SCI_DATA_IN => sci2_data_in,
SCI_DATA_OUT => sci2_data_out,
CTRL_DEBUG => (others => '0')
);
-
+ SFP_TXDIS(1) <= sfp_txdis_S(1);
+
---------------------------------------------------------------------------
-- The Soda Central
---------------------------------------------------------------------------
-THE_SOB_SOURCE : soda_start_of_burst_faker
+THE_SOB_SOURCE : soda_start_of_burst_faker\r
+ generic map(\r
+ CLOCK_PERIOD => cSYS_CLOCK_PERIOD, -- clock-period in ns
+ BURST_PERIOD => cBURST_PERIOD -- burst-period in ns
+ )
port map(
- SYSCLK => clk_raw_internal, --soda_rx_clock_half, --
+ SYSCLK => clk_sys_internal, --soda_rx_clock_half, --
RESET => reset_i,
SODA_BURST_PULSE_OUT => SOB_S
);
SODA_ACK_OUT => soda_ack,
LEDS_OUT => soda_leds
);
-
+\r
+\r
+--alive : soda_clockscaler
+-- port map(
+-- CLK => clk_raw_internal,
+-- RESET => reset_i,
+-- CLOCK_ENABLE_OUT => open,
+-- CLOCK_OUT => LED_GREEN
+-- );
+\r
+--rx_alive : soda_clockscaler
+-- port map(
+-- CLK => soda_rx_clock_full,
+-- RESET => reset_i,
+-- CLOCK_ENABLE_OUT => open,
+-- CLOCK_OUT => LED_RED
+-- );
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
- LED_ORANGE <= med_stat_op(16+8);
- LED_YELLOW <= med_stat_op(16+10);
- LED_GREEN <= med_stat_op(16+9);
- LED_RED <= med_stat_op(16+6);
+ LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);
+ LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);
+ LED_GREEN <= med_stat_op(12); --tx_pll_lol
+ LED_RED <= med_stat_op(11); --rx_cdr_lol
-- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
-- LED_YELLOW <= soda_leds(0); --'1';
-- LED_GREEN <= not med_stat_op(9);
-end trb3_periph_sodasource_arch;
+end trb3_periph_sodasource_arch;
\ No newline at end of file
--- /dev/null
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--- /dev/null
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+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>6</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>ispCLOCK</Family>
+ <Name>ispPAC-CLK5410D</Name>
+ <IDCode>0x00190043</IDCode>
+ <Package>64-pin QFNS</Package>
+ <PON>ispPAC-CLK5410D-XXSN64C</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/trb3/base/clockmanager/CM1.jed</File>
+ <FileTime>04/10/13 09:35:41</FileTime>
+ <JedecChecksum>0x1C8C</JedecChecksum>
+ <Operation>Erase,Program,Verify</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>32</PreloadLength>
+ <IOVectorData>0x00000000</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0xFFFFFFFF</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>7</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>ispCLOCK</Family>
+ <Name>ispPAC-CLK5410D</Name>
+ <IDCode>0x00190043</IDCode>
+ <Package>64-pin QFNS</Package>
+ <PON>ispPAC-CLK5410D-XXSN64C</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>32</PreloadLength>
+ <IOVectorData>0x00000000</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <VerifyUsercode value="FALSE"/>
+ </ProjectOptions>
+ <CableOptions>
+ <CableName>USB</CableName>
+ <PortAdd>EzUSB-0</PortAdd>
+ <JTAGPinSetting>
+ TRST HIGH;
+ ISPEN HIGH;
+ </JTAGPinSetting>
+ <TRSTConnect value="TRUE"/>
+ <ISPENConnect value="TRUE"/>
+ </CableOptions>
+</ispXCF>
--- /dev/null
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="2.1.0">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>1</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit</File>
+ <FileTime>09/24/13 10:52:51</FileTime>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>2</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140320.bit</File>
+ <FileTime>03/20/14 12:21:09</FileTime>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>3</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit</File>
+ <FileTime>09/03/13 16:32:30</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>4</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/gsi/bitfiles/trb3_periph_sodasource_20130408.bit</File>
+ <FileTime>04/10/13 14:12:21</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>5</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140320.bit</File>
+ <FileTime>03/18/14 15:42:08</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>6</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>ispCLOCK</Family>
+ <Name>ispPAC-CLK5410D</Name>
+ <IDCode>0x00190043</IDCode>
+ <Package>64-pin QFNS</Package>
+ <PON>ispPAC-CLK5410D-XXSN64C</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed</File>
+ <FileTime>04/10/13 09:35:41</FileTime>
+ <JedecChecksum>0x1C57</JedecChecksum>
+ <Operation>Erase,Program,Verify</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>32</PreloadLength>
+ <IOVectorData>0x00000000</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0xFFFFFFFF</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>7</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>ispCLOCK</Family>
+ <Name>ispPAC-CLK5410D</Name>
+ <IDCode>0x00190043</IDCode>
+ <Package>64-pin QFNS</Package>
+ <PON>ispPAC-CLK5410D-XXSN64C</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>32</PreloadLength>
+ <IOVectorData>0x00000000</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <VerifyUsercode value="FALSE"/>
+ </ProjectOptions>
+ <CableOptions>
+ <CableName>USB</CableName>
+ <PortAdd>EzUSB-0</PortAdd>
+ </CableOptions>
+</ispXCF>
--- /dev/null
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="2.1.0">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>1</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit</File>
+ <FileTime>09/24/13 10:52:51</FileTime>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>2</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140414.bit</File>
+ <FileTime>04/14/14 11:17:17</FileTime>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>3</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit</File>
+ <FileTime>09/03/13 16:32:30</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>4</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/gsi/bitfiles/trb3_periph_sodasource_20130408.bit</File>
+ <FileTime>04/10/13 14:12:21</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>5</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140414.bit</File>
+ <FileTime>04/14/14 11:19:05</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>6</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>ispCLOCK</Family>
+ <Name>ispPAC-CLK5410D</Name>
+ <IDCode>0x00190043</IDCode>
+ <Package>64-pin QFNS</Package>
+ <PON>ispPAC-CLK5410D-XXSN64C</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed</File>
+ <FileTime>04/10/13 09:35:41</FileTime>
+ <JedecChecksum>0x1C57</JedecChecksum>
+ <Operation>Erase,Program,Verify</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>32</PreloadLength>
+ <IOVectorData>0x00000000</IOVectorData>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <Usercode>0xFFFFFFFF</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>7</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>ispCLOCK</Family>
+ <Name>ispPAC-CLK5410D</Name>
+ <IDCode>0x00190043</IDCode>
+ <Package>64-pin QFNS</Package>
+ <PON>ispPAC-CLK5410D-XXSN64C</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>32</PreloadLength>
+ <IOVectorData>0x00000000</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <VerifyUsercode value="FALSE"/>
+ </ProjectOptions>
+ <CableOptions>
+ <CableName>USB</CableName>
+ <PortAdd>EzUSB-0</PortAdd>
+ </CableOptions>
+</ispXCF>
jspc29 / soda.git / commitdiff