generic flash ctrl, IF

diff --git a/default/logicbox.prj b/default/logicbox.prj
index 23ee67243d50444477ef667ead290988b9ddf03f..2b1374f1cb146956479900a5787b7e306a842e46 100644 (file)
--- a/default/logicbox.prj
+++ b/default/logicbox.prj
@@ -8,16 +8,19 @@ add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesi
 
 #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../code/uart_sctrl.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/uart_sctrl.vhd"
 add_file -vhdl -lib work "../code/sedcheck.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 
-add_file -vhdl -lib work "../cores/flashram.vhd"
-add_file -vhdl -lib work "../cores/efb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v"
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
+
 add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd"
-add_file -verilog -lib work "../cores/efb_define_def.v"
-add_file -verilog -lib work "../cores/UFM_WB.v"
+
 
 add_file -vhdl -lib work "logicbox.vhd"
 

diff --git a/default/logicbox.vhd b/default/logicbox.vhd
index 1229532543e32993731e41c8ace4f5a5fc972ad1..6e34b76227fe50a6df3062e9ae538f43c42f724c 100644 (file)
--- a/default/logicbox.vhd
+++ b/default/logicbox.vhd
@@ -290,27 +290,13 @@ THE_UART : entity work.uart_sctrl
     DEBUG     => open\r
     );\r
 \r
----------------------------------------------------------------------------\r
--- UFM (FLASH) CONTROLLER\r
----------------------------------------------------------------------------      \r
---THE_UFM : entity UFM_control\r
---  generic map(\r
---    NO_DATAPAGES => 1,\r
---    UFM_STARTPAGE => "00"&x"00"\r
---    )\r
---  port map(\r
---    CLK => clk_33,\r
---    CMD => ufm_cmd, --CMD=0 => Read; CMD=1 => Write\r
---    GO => ufm_go,\r
---    BUSY => ufm_busy,\r
---    RESET => '0',  \r
---    DATA_IN => ufm_data_in, \r
---    DATA_OUT => ufm_data_out,\r
---    DATABYTE_COUNTER => ufm_databyte_counter,\r
---    BUS_READY_IN => ufm_bus_ready_in,\r
---    BUS_READY_OUT  => ufm_bus_ready_out,\r
---    FLASH_ERROR => open--ufmflasherror\r
---    );\r
+--uart_rx_data <= uart_data_out;\r
+--uart_data_in <= uart_tx_data;\r
+--uart_addr    <= uart_addr_out;\r
+--bus_write    <= uart_write_out;\r
+--bus_read     <= uart_read_out;\r
+--uart_ready_in <= bus_ready;\r
+--bus_busy     <= uart_busy_out;\r
 \r
 THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
   generic map(\r
@@ -318,7 +304,8 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
     )\r
   port map(\r
 \r
-    CLK => clk_33,\r
+    CLK_l => clk_33,\r
+    CLK_f => clk_33,\r
     RESET => '0',\r
 \r
     SPI_DATA_IN   => uart_data_out,\r
@@ -337,7 +324,7 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
     LOC_READY_IN  => bus_ready,\r
     LOC_BUSY_OUT  => bus_busy\r
 \r
-  );\r
+ );\r
 \r
 \r
 ---------------------------------------------------------------------------\r
@@ -365,7 +352,7 @@ PROC_REGS : process begin
       when x"ff" => uart_tx_data <= testreg1;              \r
       when x"fe" => uart_tx_data <= testreg2;                    \r
                     \r
-      when others =>null;\r
+      when others => uart_tx_data <= x"00000000";\r
     end case;\r
     \r
   elsif bus_write = '1' then\r
@@ -452,14 +439,14 @@ PROC_REGS : process begin
 end process;\r
 \r
 \r
--- THE_SED : entity work.sedcheck\r
---   port map(\r
---     CLK        => clk_i,\r
---     ERROR_OUT  => sed_error,\r
---     \r
---     CONTROL_IN => controlsed_i,\r
---     DEBUG      => sed_debug\r
---     );\r
+ THE_SED : entity work.sedcheck\r
+   port map(\r
+     CLK        => clk_i,\r
+     ERROR_OUT  => sed_error,\r
+     \r
+     CONTROL_IN => controlsed_i,\r
+     DEBUG      => sed_debug\r
+     );\r
 \r
 --   process begin\r
 --     wait until rising_edge(clk_i);\r