add bus master input to accel hub

diff --git a/trb_net16_hub_streaming_port_sctrl_accel.vhd b/trb_net16_hub_streaming_port_sctrl_accel.vhd
index b93a2cd0573790a79205ca3baaff8408adef0f53..9f525ebb8ed66377bcfb1886ed8c86d627ca87e2 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl_accel.vhd
+++ b/trb_net16_hub_streaming_port_sctrl_accel.vhd
@@ -95,7 +95,10 @@ entity trb_net16_hub_streaming_port_sctrl_record is
     BUS_RX                       : out CTRLBUS_RX;
     BUS_TX                       : in  CTRLBUS_TX;
     TIMER                        : out TIMERS;
-
+    --Data port - external master (e.g. Flash or Debug)
+    BUS_MASTER_IN                : out CTRLBUS_TX;
+    BUS_MASTER_OUT               : in  CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0');
+    BUS_MASTER_ACTIVE            : in  std_logic := '0';
     --Gbe Sctrl Input
     GSC_INIT_DATAREADY_IN        : in  std_logic;
     GSC_INIT_DATA_IN             : in  std_logic_vector(15 downto 0);
@@ -176,7 +179,7 @@ signal HUB_MED_CTRL_OP   : std_logic_vector(mii*16-1 downto 0);
 signal reset_i_mux_io    : std_logic;
 
 signal hub_make_network_reset : std_logic := '0';
-signal hub_got_network_reset  : std_logic;\r
+signal hub_got_network_reset  : std_logic;
 signal timer_i                : TIMERS;
 signal timer_ticks            : std_logic_vector(1 downto 0);
 signal hub_ctrl_debug         : std_logic_vector(31 downto 0);
@@ -334,7 +337,9 @@ end generate;
       REGIO_WRITE_ACK_IN        => wrack,
       REGIO_UNKNOWN_ADDR_IN     => hubbus_tx.unknown,
       REGIO_TIMEOUT_OUT         => hubbus_rx.timeout,
-
+      BUS_MASTER_IN             => BUS_MASTER_IN,
+      BUS_MASTER_OUT            => BUS_MASTER_OUT,
+      BUS_MASTER_ACTIVE         => BUS_MASTER_ACTIVE,
       TIMER_TICKS_OUT(0)        => timer_i.tick_us,
       TIMER_TICKS_OUT(1)        => timer_i.tick_ms,
       ONEWIRE            => ONEWIRE,
@@ -356,7 +361,7 @@ end generate;
   hub_ctrl_debug(2 downto 0) <= not io_error_in;
   hub_ctrl_debug(31 downto 3) <= (others => '0');
   HUB_STAT_GEN <= buf_HUB_STAT_GEN;
-  timer_ticks <= timer_i.tick_ms & timer_i.tick_us;\r
+  timer_ticks <= timer_i.tick_ms & timer_i.tick_us;
   TIMER <= timer_i;
   
 ---------------------------------------------------------------------

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 113169a5b93aa8652795b04cadf045912a69fe26..ccd835e5735499c58f21c6b3f05262a16178ed0a 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -3672,4 +3672,44 @@ end component;
     );\r
 end component trb_net_xdna;\r
 \r
+component i2c_slim2 is\r
+port(\r
+  CLOCK           : in  std_logic;\r
+  RESET           : in  std_logic;\r
+  -- I2C command / setup\r
+  I2C_GO_IN       : in  std_logic; -- startbit to trigger I2C actions\r
+  ACTION_IN       : in  std_logic; -- '0' -> write, '1' -> read\r
+  WORD_IN         : in  std_logic; -- '0' -> byte, '1' -> word\r
+  DIRECT_IN       : in  std_logic; -- '0' -> normal access, '1' -> direct read\r
+  I2C_SPEED_IN    : in  std_logic_vector(5 downto 0); -- speed adjustment (to be defined)\r
+  I2C_ADDR_IN     : in  std_logic_vector(7 downto 0); -- I2C address byte (R/W bit is ignored)\r
+  I2C_CMD_IN      : in  std_logic_vector(7 downto 0); -- I2C command byte (sent after address byte)\r
+  I2C_DW_IN       : in  std_logic_vector(15 downto 0); -- data word for write command\r
+  I2C_DR_OUT      : out std_logic_vector(15 downto 0); -- data word from read command\r
+  STATUS_OUT      : out std_logic_vector(7 downto 0); -- status and error bits\r
+  VALID_OUT       : out std_logic;\r
+  I2C_BUSY_OUT    : out std_logic;\r
+  I2C_DONE_OUT    : out std_logic;\r
+  -- I2C connections\r
+  SDA_IN          : in  std_logic; \r
+  SDA_OUT         : out std_logic;\r
+  SCL_IN          : in  std_logic;\r
+  SCL_OUT         : out std_logic;\r
+  -- Debug\r
+  BSM_OUT         : out std_logic_vector(3 downto 0)\r
+);\r
+end component;\r
+\r
+component common_i2c is\r
+  port(\r
+    CLOCK      : in    std_logic;\r
+    RESET      : in    std_logic;\r
+    SDA        : inout std_logic;\r
+    SCL        : inout std_logic;\r
+    BUS_RX     : in    CTRLBUS_RX;\r
+    BUS_TX     : out   CTRLBUS_TX\r
+    );\r
+end component;\r
+\r
+\r
 end package;\r