final cosmetics, EU removed

diff --git a/GSI_2015_MP_CBMNet/trb3_cbmnet.pdf b/GSI_2015_MP_CBMNet/trb3_cbmnet.pdf
index 2b40f97e63cdc51024bb8fa503500782afbea687..245c8314a8a0446929ed4c93189e76aa6333c191 100644 (file)
Binary files a/GSI_2015_MP_CBMNet/trb3_cbmnet.pdf and b/GSI_2015_MP_CBMNet/trb3_cbmnet.pdf differ

diff --git a/GSI_2015_MP_CBMNet/trb3_cbmnet.tex b/GSI_2015_MP_CBMNet/trb3_cbmnet.tex
index 4ca09f6eb1466cb26d1143bfbdd08ae85c6269f7..cd139cc8957eb1aec2062632ff5a5531a60b76df 100644 (file)
--- a/GSI_2015_MP_CBMNet/trb3_cbmnet.tex
+++ b/GSI_2015_MP_CBMNet/trb3_cbmnet.tex
@@ -4,13 +4,13 @@
 \usepackage[utf8]{inputenc}
 \usepackage{amsmath}
 \usepackage{amssymb}
-%% GSI Scientific Report 2013 
+%% GSI Scientific Report 2013
 %% \setlength{\titleblockheight}{27mm} KG
 \setlength{\titleblockheight}{35mm}
 
 \begin{document}
 \title{A CBMNet Bridge for the TRB3
-\thanks{This work has been supported by BMBF (05P12RFFC7), EU-FP7 HadronPhysics3, HGS-HIRe, GSI and HIC for FAIR.}
+\thanks{This work has been supported by BMBF (05P12RFFC7), HGS-HIRe, GSI and HIC for FAIR.}
 }
 
 \author[1]{M. Penschuck}
@@ -26,9 +26,9 @@ The TRB3 is a flexible and modular FPGA-based data acquisition platform originat
 Unifying all base-functionality on a universal main board, connectivity to the experimental setup is established using up to five application-specific add-on boards.
 The platform is used by a number of detectors, amongst them prototypes for CBM-MVD and CBM-RICH.
 
-The board features five inexpensive Lattice ECP3 FPGAs optimised for a high IO count rather than computational power, which is typically not required for early DAQ stages:
-one central chip primarily executes management- and network-related tasks while the remaining FPGAs together with their respective add-ons form four independent sub-systems.
-Applications include FPGA-based TDC- (up to 264 channels/board with a precision of 7.2~ps RMS [1]) and ADC-measurements as well as the read-out of high-speed digital signals, e.g. for the MAPS in case of CBM-MVD.
+The board features five inexpensive Lattice ECP3 FPGAs optimised for a high I/O count rather than computational power, which is typically not required for early DAQ stages:
+One central chip primarily executes management- and network-related tasks while the remaining FPGAs together with their respective add-ons form four independent sub-systems.
+Applications include FPGA-based TDC- (up to 264 channels/board with a precision of 7.2~ps RMS [1]) and ADC-measurements as well as the read-out of high-speed digital signals, e.g.~for the pixel sensors in case of CBM-MVD.
 The TRB3 can be operated in a stand-alone fashion only requiring an external power supply and a PC capable of Gigabit Ethernet (GbE);
 however, large systems are inherently supported by its internal network protocol, TrbNet, which was originally developed for HADES.
 
@@ -55,7 +55,7 @@ The network bridge was successfully used in conjunction with the current CBM-RIC
   \begin{center}
     \includegraphics[width=0.8\columnwidth]{topology.eps}
   \end{center}
-  
+
   \caption{
     A typical TRB3 set-up with CBMNet bridge.
     If multiple boards are used, they can share a common CBMNet link.
@@ -66,14 +66,14 @@ The network bridge was successfully used in conjunction with the current CBM-RIC
 
 
 
-\begin{thebibliography}{9} 
+\begin{thebibliography}{9}
   \bibitem{}
     C. Ugur and the TRB3 collaboration, ``264 Channel TDC Platform applying 65 channel high precision (7.2 psRMS) FPGA based TDCs'',
     IEEE NoMe TDC, October 2013
 
   \bibitem{}
     D. Hutter, ``CBM FLES Input Interface Developments'', CBM Progress Report 2014
-    
+
 \end{thebibliography}
 \end{document}