uploaded extre files

diff --git a/dirich/config.vhd b/dirich/config.vhd
index 222661e0aa0d8bc68c7b5c3e75aecb8d5067bf35..30cc46c4663dcfc9050f83bf901cceb0fa719111 100644 (file)
--- a/dirich/config.vhd
+++ b/dirich/config.vhd
@@ -10,20 +10,22 @@ package config is
 --Begin of design configuration
 ------------------------------------------------------------------------------
 --TDC settings
-  constant NUM_TDC_MODULES          : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS         : integer range 1 to 65 := 3;  -- number of tdc channels per module
-  constant NUM_TDC_CHANNELS_POWER2  : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
-  constant DOUBLE_EDGE_TYPE         : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
+  constant BOARD                   : string                := "dirich";  -- Options: dirich, trb3
+  constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 5;  -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
+  constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
   -- 1: same channel,
   -- 2: alternating channels,
   -- 3: same channel with stretcher
-  constant RING_BUFFER_SIZE         : integer range 0 to 7  := 7;  --ring buffer size
+  constant RING_BUFFER_SIZE        : integer range 0 to 7  := 0;  --ring buffer size
   -- mode:  0,  1,  2,   3,   7
   -- size: 32, 64, 96, 128, dyn
-  constant TDC_DATA_FORMAT          : integer range 0 to 3 := 15;  --type of data format for the TDC
+  constant TDC_DATA_FORMAT         : integer range 0 to 3  := 0;  --type of data format for the TDC
   --  0: Single fine time as the sum of the two transitions
   --  1: Double fine time, individual transitions
+  -- 13: Debug - fine time + (if 0x3ff full chain)
   -- 14: Debug - single fine time and the ROM addresses for the two transitions
   -- 15: Debug - complete carry chain dump
 

diff --git a/dirich/config_compile_gsi.pl b/dirich/config_compile_gsi.pl
index bbf389263ed717f697bca0e7c5aba41a6dccf9f3..2125f1e6ec712543bed1bf5b4ffe29ba5f8bd041 100644 (file)
--- a/dirich/config_compile_gsi.pl
+++ b/dirich/config_compile_gsi.pl
@@ -6,7 +6,7 @@ Speedgrade  => '8',
 TOPNAME                      => "dirich",
 lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/opt/lattice/diamond/3.6_x64',
+lattice_path                 => '/opt/lattice/diamond/3.8_x64',
 synplify_path                => '/opt/synplicity/K-2015.09',
 #synplify_command             => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
 synplify_command             => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",

diff --git a/dirich/dirich.prj b/dirich/dirich.prj
index c943f561c5f0c8700c04727c74039b8740ee5ba9..5035fd1a56f7eb32e747cf16c16859ea3e0be1d8 100644 (file)
--- a/dirich/dirich.prj
+++ b/dirich/dirich.prj
@@ -205,6 +205,8 @@ add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
 #add_file -vhdl -lib work "tdc_release/TDC.vhd"
 add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
 add_file -vhdl -lib work "tdc_release/up_counter.vhd"
+
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"

diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd
index 06fe157147e7a786afc9ba773a10a5bcb14b9ffc..d4ff9fb0b5048f6fcd06517411f99dcfc8ceda86 100644 (file)
--- a/dirich/dirich.vhd
+++ b/dirich/dirich.vhd
@@ -425,11 +425,9 @@ begin
       );
 
 -- For single edge measurements
-  --gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
-  --  hit_in_i <= INPUT;
-  --end generate;
-  hit_in_i(1) <= INPUT(31);
-  hit_in_i(2) <= INPUT(32);
+  gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+    hit_in_i <= INPUT;
+  end generate;
 
 -- For ToT Measurements
   gen_double : if DOUBLE_EDGE_TYPE = 2 generate