<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_3" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 05 26 18:57:42.046" version="8.1" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="serdes_sync_3" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 06 22 12:02:24.605" version="8.1" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="serdes_sync_3.lpc" type="lpc" modified="2015 05 26 18:57:40.000"/>
- <File name="serdes_sync_3.pp" type="pp" modified="2015 05 26 18:57:40.000"/>
- <File name="serdes_sync_3.sym" type="sym" modified="2015 05 26 18:57:40.000"/>
- <File name="serdes_sync_3.tft" type="tft" modified="2015 05 26 18:57:40.000"/>
- <File name="serdes_sync_3.txt" type="pcs_module" modified="2015 05 26 18:57:40.000"/>
- <File name="serdes_sync_3.vhd" type="top_level_vhdl" modified="2015 05 26 18:57:40.000"/>
+ <File name="serdes_sync_3.lpc" type="lpc" modified="2015 06 22 12:02:18.000"/>
+ <File name="serdes_sync_3.pp" type="pp" modified="2015 06 22 12:02:18.000"/>
+ <File name="serdes_sync_3.sym" type="sym" modified="2015 06 22 12:02:18.000"/>
+ <File name="serdes_sync_3.tft" type="tft" modified="2015 06 22 12:02:18.000"/>
+ <File name="serdes_sync_3.txt" type="pcs_module" modified="2015 06 22 12:02:18.000"/>
+ <File name="serdes_sync_3.vhd" type="top_level_vhdl" modified="2015 06 22 12:02:18.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_3
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=05/26/2015
-Time=18:57:40
+Date=06/22/2015
+Time=12:02:18
[Parameters]
Verilog=0
_tx_fifo0=DISABLED
_tx_fifo1=ENABLED
_tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
+_tx_fifo3=ENABLED
_tx_ficlk_rate0=200
_tx_ficlk_rate1=200
_tx_ficlk_rate2=200
CH3_TX_DATA_RATE "FULL"
CH3_TX_DATA_WIDTH "8"
CH3_RX_DATA_WIDTH "8"
-CH3_TX_FIFO "DISABLED"
+CH3_TX_FIFO "ENABLED"
CH3_RX_FIFO "ENABLED"
CH3_TDRV "0"
#CH3_TX_FICLK_RATE 200
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
--Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
- --Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
- CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
+ MEDIA_MED2INT : out MED2INT;
+ MEDIA_INT2MED : in INT2MED;
--Sync operation
RX_DLM : out std_logic := '0';
SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
--Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
-- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
STAT_DEBUG : out std_logic_vector (63 downto 0);
CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
signal clk_200_i : std_logic;
signal clk_200_internal : std_logic;
-signal clk_rx_full : std_logic;
-signal clk_rx_half : std_logic;
-signal clk_tx_full : std_logic;
-signal clk_tx_half : std_logic;
+signal clk_rx_full, clk_rx_half : std_logic;
+signal clk_tx_full, clk_tx_half : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_k : std_logic;
signal rx_error : std_logic;
signal rst_n : std_logic;
-signal rst : std_logic;
signal rx_serdes_rst : std_logic;
signal tx_serdes_rst : std_logic;
signal tx_pcs_rst : std_logic;
signal rx_pcs_rst : std_logic;
signal rst_qd : std_logic;
signal serdes_rst_qd : std_logic;
-signal sd_los_i : std_logic;
signal rx_los_low : std_logic;
signal lsm_status : std_logic;
signal rx_cdr_lol : std_logic;
signal tx_pll_lol : std_logic;
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
+signal sci_ch_i : std_logic_vector(4 downto 0);
+signal sci_addr_i : std_logic_vector(5 downto 0);
signal sci_data_in_i : std_logic_vector(7 downto 0);
signal sci_data_out_i : std_logic_vector(7 downto 0);
signal sci_read_i : std_logic;
signal sci_write_i : std_logic;
signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow : std_logic;
-signal rx_allow : std_logic;
-signal tx_allow_q : std_logic;
-signal rx_allow_q : std_logic;
-signal request_retr_i : std_logic;
-signal start_retr_i : std_logic;
-signal request_retr_position_i : std_logic_vector(7 downto 0);
-signal start_retr_position_i : std_logic_vector(7 downto 0);
-signal send_link_reset_i : std_logic;
-signal make_link_reset_i : std_logic;
-signal got_link_ready_i : std_logic;
-signal internal_make_link_reset_out : std_logic;
+signal wa_position_sel : std_logic_vector(3 downto 0);
signal stat_rx_control_i : std_logic_vector(31 downto 0);
signal stat_tx_control_i : std_logic_vector(31 downto 0);
signal debug_rx_control_i : std_logic_vector(31 downto 0);
signal debug_tx_control_i : std_logic_vector(31 downto 0);
-signal rx_fsm_state : std_logic_vector(3 downto 0);
-signal tx_fsm_state : std_logic_vector(3 downto 0);
-signal debug_reg : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state : sci_ctrl;
-signal sci_timer : unsigned(12 downto 0) := (others => '0');
-signal start_timer : unsigned(18 downto 0) := (others => '0');
+signal stat_fsm_reset_i : std_logic_vector(31 downto 0);
-signal rx_dlm_i : std_logic;
-signal led_dlm, last_led_dlm : std_logic;
-signal led_ok : std_logic;
-signal led_tx, last_led_tx : std_logic;
-signal led_rx, last_led_rx : std_logic;
-signal timer : unsigned(20 downto 0);
begin
clk_200_internal <= CLK;
-CLK_RX_HALF_OUT <= clk_rx_half;
-CLK_RX_FULL_OUT <= clk_rx_full;
-
-
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-
-rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
-rst <= (CLEAR or sd_los_i or internal_make_link_reset_out);
-
-
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
clk_200_i <= clk_rx_full;
end generate;
SCI_WRDATA => sci_data_in_i,
SCI_RDDATA => sci_data_out_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_SEL_QUAD => sci_qd_i,
+ SCI_ADDR => sci_addr_i,
+ SCI_SEL_QUAD => sci_ch_i(4),
SCI_SEL_CH0 => sci_ch_i(0),
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
fpga_txrefclk => clk_200_i,
- tx_serdes_rst_c => tx_serdes_rst,
+ tx_serdes_rst_c => '0',
tx_pll_lol_qd_s => tx_pll_lol,
rst_qd_c => rst_qd,
- serdes_rst_qd_c => serdes_rst_qd
+ serdes_rst_qd_c => '0'
);
end generate;
hdinn_ch3 => SD_RXD_N_IN,
hdoutp_ch3 => SD_TXD_P_OUT,
hdoutn_ch3 => SD_TXD_N_OUT,
- rxiclk_ch3 => clk_200_i,
- txiclk_ch3 => clk_200_i,
+ rxiclk_ch3 => clk_rx_full, --JM06
+ txiclk_ch3 => clk_tx_full, --JM06 clk_tx_fullclk_200_i,
rx_full_clk_ch3 => clk_rx_full,
rx_half_clk_ch3 => clk_rx_half,
tx_full_clk_ch3 => clk_tx_full,
SCI_WRDATA => sci_data_in_i,
SCI_RDDATA => sci_data_out_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_SEL_QUAD => sci_qd_i,
+ SCI_ADDR => sci_addr_i,
+ SCI_SEL_QUAD => sci_ch_i(4),
SCI_SEL_CH3 => sci_ch_i(0),
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
fpga_txrefclk => clk_200_i,
- tx_serdes_rst_c => tx_serdes_rst,
+ tx_serdes_rst_c => '0',
tx_pll_lol_qd_s => tx_pll_lol,
rst_qd_c => rst_qd,
- serdes_rst_qd_c => serdes_rst_qd
+ serdes_rst_qd_c => '0'
);
end generate;
tx_serdes_rst <= '0'; --no function
serdes_rst_qd <= '0'; --included in rst_qd
+ wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0
+ else wa_position(15 downto 12) when SERDES_NUM = 3;
--------------------------------------------------
--- Reset FSM & Link states
--------------------------------------------------
-THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n,
- RX_REFCLK => clk_200_i,
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RX_SERDES_RST_CH_C => rx_serdes_rst,
- RX_CDR_LOL_CH_S => rx_cdr_lol,
- RX_LOS_LOW_CH_S => rx_los_low,
- RX_PCS_RST_CH_C => rx_pcs_rst,
- WA_POSITION => wa_position_rx(3 downto 0),
- STATE_OUT => rx_fsm_state
- );
-
-THE_TX_FSM : tx_reset_fsm
+THE_MED_CONTROL : entity work.med_sync_control
+ generic map(
+ IS_SYNC_SLAVE => IS_SYNC_SLAVE,
+ IS_TX_RESET => 1
+ )
port map(
- RST_N => rst_n,
- TX_REFCLK => clk_200_internal,
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RST_QD_C => rst_qd,
- TX_PCS_RST_CH_C => tx_pcs_rst,
- STATE_OUT => tx_fsm_state
- );
-
+ CLK_SYS => SYSCLK,
+ CLK_RXI => clk_rx_full,
+ CLK_RXHALF => clk_rx_half,
+ CLK_TXI => clk_tx_full,
+ CLK_REF => clk_200_internal,
+ RESET => RESET,
+ CLEAR => CLEAR,
+ SFP_LOS => SD_LOS_IN,
+ TX_LOL => tx_pll_lol,
+ RX_CDR_LOL => rx_cdr_lol,
+ RX_LOS => rx_los_low,
+ WA_POSITION => wa_position_sel,
--- Master does not do bit-locking
-SYNC_WA_POSITION : process begin
- wait until rising_edge(clk_200_i);
- if IS_SYNC_SLAVE = 1 then
- wa_position_rx <= wa_position;
- else
- wa_position_rx <= x"0000";
- end if;
-end process;
-
-
---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
-PROC_ALLOW : process begin
- wait until rising_edge(clk_200_i);
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
- rx_allow <= '1';
- else
- rx_allow <= '0';
- end if;
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
- tx_allow <= '1';
- else
- tx_allow <= '0';
- end if;
-end process;
-
-rx_allow_q <= rx_allow when rising_edge(SYSCLK);
-tx_allow_q <= tx_allow when rising_edge(SYSCLK);
+ RX_SERDES_RST => rx_serdes_rst,
+ RX_PCS_RST => rx_pcs_rst,
+ QUAD_RST => rst_qd,
+ TX_PCS_RST => tx_pcs_rst,
-
-PROC_START_TIMER : process begin
- wait until rising_edge(clk_200_i);
- if got_link_ready_i = '1' then
- if start_timer(start_timer'left) = '0' then
- start_timer <= start_timer + 1;
- end if;
- else
- start_timer <= (others => '0');
- end if;
-end process;
+ MEDIA_MED2INT => MEDIA_MED2INT,
+ MEDIA_INT2MED => MEDIA_INT2MED,
+ TX_DATA => tx_data,
+ TX_K => tx_k,
+ RX_DATA => rx_data,
+ RX_K => rx_k,
--------------------------------------------------
--- TX Data
--------------------------------------------------
-THE_TX : tx_control
- port map(
- CLK_200 => clk_200_i,
- CLK_100 => SYSCLK,
- RESET_IN => rst,
-
- TX_DATA_IN => MED_DATA_IN,
- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,
- TX_WRITE_IN => MED_DATAREADY_IN,
- TX_READ_OUT => MED_READ_OUT,
-
- TX_DATA_OUT => tx_data,
- TX_K_OUT => tx_k,
-
- REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
- REQUEST_POSITION_IN => request_retr_position_i, --TODO
-
- START_RETRANSMIT_IN => start_retr_i, --TODO
- START_POSITION_IN => start_retr_position_i, --TODO
-
- SEND_DLM => TX_DLM,
- SEND_DLM_WORD => TX_DLM_WORD,
+ TX_DLM_WORD => TX_DLM_WORD,
+ TX_DLM => TX_DLM,
+ RX_DLM_WORD => RX_DLM_WORD,
+ RX_DLM => RX_DLM,
- SEND_LINK_RESET_IN => CTRL_OP(15),
- TX_ALLOW_IN => tx_allow,
- RX_ALLOW_IN => rx_allow,
-
- DEBUG_OUT => debug_tx_control_i,
- STAT_REG_OUT => stat_tx_control_i
- );
-
+ STAT_TX_CONTROL => stat_tx_control_i,
+ STAT_RX_CONTROL => stat_rx_control_i,
+ DEBUG_TX_CONTROL => debug_tx_control_i,
+ DEBUG_RX_CONTROL => debug_rx_control_i,
+ STAT_RESET => stat_fsm_reset_i
+ );
--------------------------------------------------
--- RX Data
--------------------------------------------------
-THE_RX_CONTROL : rx_control
+THE_SCI_READER : entity work.sci_reader
port map(
- CLK_200 => clk_200_i,
- CLK_100 => SYSCLK,
- RESET_IN => rst,
-
- RX_DATA_OUT => MED_DATA_OUT,
- RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,
- RX_WRITE_OUT => MED_DATAREADY_OUT,
- RX_READ_IN => MED_READ_IN,
-
- RX_DATA_IN => rx_data,
- RX_K_IN => rx_k,
-
- REQUEST_RETRANSMIT_OUT => request_retr_i,
- REQUEST_POSITION_OUT => request_retr_position_i,
-
- START_RETRANSMIT_OUT => start_retr_i,
- START_POSITION_OUT => start_retr_position_i,
-
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
- RX_DLM => rx_dlm_i,
- RX_DLM_WORD => RX_DLM_WORD,
+ CLK => SYSCLK,
+ RESET => RESET,
- SEND_LINK_RESET_OUT => send_link_reset_i,
- MAKE_RESET_OUT => make_link_reset_i,
- RX_ALLOW_IN => rx_allow,
- GOT_LINK_READY => got_link_ready_i,
-
- DEBUG_OUT => debug_rx_control_i,
- STAT_REG_OUT => stat_rx_control_i
- );
+ --SCI
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i,
+ SCI_SEL => sci_ch_i,
+ SCI_RD => sci_read_i,
+ SCI_WR => sci_write_i,
-RX_DLM <= rx_dlm_i;
+ WA_POS_OUT => wa_position,
--------------------------------------------------
--- SCI
--------------------------------------------------
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process
- variable cnt : integer range 0 to 4 := 0;
-begin
- wait until rising_edge(SYSCLK);
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer <= sci_timer + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- elsif sci_timer(sci_timer'left) = '1' then
- sci_timer <= (others => '0');
- sci_state <= GET_WA;
- end if;
- when SCTRL =>
- if sci_reg_i = '1' then
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
- when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
- when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
- when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
+ --Slowcontrol
+ BUS_RX => BUS_RX,
+ BUS_TX => BUS_TX,
- when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
- when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
- when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
- when GET_WA_FINISH =>
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
- end case;
-
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
- else
- SCI_NACK <= '0';
- end if;
-
-end process;
-
--------------------------------------------------
--- Generate LED signals
--------------------------------------------------
-led_ok <= rx_allow and tx_allow when rising_edge(SYSCLK);
-led_rx <= (MED_DATAREADY_OUT or led_rx) and not timer(20) when rising_edge(SYSCLK);
-led_tx <= (MED_DATAREADY_IN or led_tx or sd_los_i) and not timer(20) when rising_edge(SYSCLK);
-led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(SYSCLK);
-
-ROC_TIMER : process begin
- wait until rising_edge(SYSCLK);
- timer <= timer + 1 ;
- if timer(20) = '1' then
- timer <= (others => '0');
- last_led_rx <= led_rx ;
- last_led_tx <= led_tx;
- last_led_dlm <= led_dlm;
- end if;
-end process;
-
--------------------------------------------------
--- Debug Registers
--------------------------------------------------
-debug_reg(2 downto 0) <= rx_fsm_state(2 downto 0);
-debug_reg(3) <= rx_serdes_rst;
-debug_reg(4) <= CLEAR;
-debug_reg(5) <= tx_allow_q;
-debug_reg(6) <= rx_los_low;
-debug_reg(7) <= rx_cdr_lol;
-
-debug_reg(8) <= RESET;
-debug_reg(9) <= tx_pll_lol;
-debug_reg(10) <= rx_allow_q;
-debug_reg(11) <= CTRL_OP(15);
-debug_reg(12) <= make_link_reset_i;
-debug_reg(13) <= send_link_reset_i;
-debug_reg(14) <= sd_los_i;
-debug_reg(15) <= rx_pcs_rst;
--- debug_reg(31 downto 24) <= tx_data;
-
-debug_reg(16) <= '0';
-debug_reg(17) <= tx_allow;
-debug_reg(18) <= RESET;
-debug_reg(19) <= CLEAR;
-debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
-
-debug_reg(35 downto 32) <= wa_position(3 downto 0);
-debug_reg(36) <= debug_tx_control_i(6);
-debug_reg(39 downto 37) <= "000";
-debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
-
-
-STAT_DEBUG <= debug_reg;
-
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = 1 else '0';
-sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK);
+ MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i,
+ MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i,
+ MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i,
+ MEDIA_STATUS_REG_IN(127 downto 96) => (others => '0'),
+ DEBUG_OUT => open
+ );
-STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
-STAT_OP(14) <= '0' when rising_edge(SYSCLK); --sd_los_i
-STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset
-STAT_OP(12) <= led_dlm or last_led_dlm;
-STAT_OP(11) <= led_tx or last_led_tx;
-STAT_OP(10) <= led_rx or last_led_rx;
-STAT_OP(9) <= led_ok;
-STAT_OP(8 downto 4) <= (others => '0');
-STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
---STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else ("01" & tx_pll_lol & rx_cdr_lol);
+STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0);
+STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8);
+STAT_DEBUG(7) <= '0';
+STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0);
+
+
end architecture;
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+
+entity med_sync_control is
+ generic(
+ IS_SYNC_SLAVE : integer := 1;
+ IS_TX_RESET : integer := 1
+ );
+ port(
+ CLK_SYS : in std_logic;
+ CLK_RXI : in std_logic;
+ CLK_RXHALF : in std_logic;
+ CLK_TXI : in std_logic;
+ CLK_REF : in std_logic;
+ RESET : in std_logic;
+ CLEAR : in std_logic;
+
+ SFP_LOS : in std_logic;
+ TX_LOL : in std_logic;
+ RX_CDR_LOL : in std_logic;
+ RX_LOS : in std_logic;
+ WA_POSITION : in std_logic_vector(3 downto 0);
+
+ RX_SERDES_RST : out std_logic;
+ RX_PCS_RST : out std_logic;
+ QUAD_RST : out std_logic;
+ TX_PCS_RST : out std_logic;
+
+ MEDIA_MED2INT : out MED2INT;
+ MEDIA_INT2MED : in INT2MED;
+
+ TX_DATA : out std_logic_vector(7 downto 0);
+ TX_K : out std_logic;
+ RX_DATA : in std_logic_vector(7 downto 0);
+ RX_K : in std_logic;
+
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ TX_DLM : in std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ RX_DLM : out std_logic;
+
+ STAT_TX_CONTROL : out std_logic_vector(31 downto 0);
+ STAT_RX_CONTROL : out std_logic_vector(31 downto 0);
+ DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0);
+ DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0);
+ STAT_RESET : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+
+architecture med_sync_control_arch of med_sync_control is
+
+signal rx_fsm_state : std_logic_vector(3 downto 0);
+signal tx_fsm_state : std_logic_vector(3 downto 0);
+signal wa_position_rx : std_logic_vector(3 downto 0);
+signal start_timer : unsigned(17 downto 0) := (others => '0');
+
+signal request_retr_i : std_logic;
+signal start_retr_i : std_logic;
+signal request_retr_position_i : std_logic_vector(7 downto 0);
+signal start_retr_position_i : std_logic_vector(7 downto 0);
+signal rx_dlm_i : std_logic;
+
+signal led_ok : std_logic;
+signal led_dlm, last_led_dlm : std_logic;
+signal led_rx, last_led_rx : std_logic;
+signal led_tx, last_led_tx : std_logic;
+signal timer : unsigned(20 downto 0);
+signal sd_los_i : std_logic;
+
+signal rx_allow : std_logic;
+signal tx_allow : std_logic;
+signal got_link_ready_i : std_logic;
+signal make_link_reset_i : std_logic;
+signal send_link_reset_i : std_logic;
+signal make_link_reset_real_i : std_logic;
+
+signal reset_i, rst_n : std_logic;
+signal media_med2int_i : MED2INT;
+
+begin
+
+rst_n <= not (CLEAR or sd_los_i or make_link_reset_real_i);
+reset_i <= (CLEAR or sd_los_i or make_link_reset_real_i);
+
+
+media_med2int_i.clk_half <= CLK_RXHALF;
+media_med2int_i.clk_full <= CLK_RXI;
+
+-------------------------------------------------
+-- Reset FSM & Link states
+-------------------------------------------------
+THE_RX_FSM : rx_reset_fsm
+ port map(
+ RST_N => RST_N,
+ RX_REFCLK => CLK_REF,
+ TX_PLL_LOL_QD_S => TX_LOL,
+ RX_SERDES_RST_CH_C => RX_SERDES_RST,
+ RX_CDR_LOL_CH_S => RX_CDR_LOL,
+ RX_LOS_LOW_CH_S => RX_LOS,
+ RX_PCS_RST_CH_C => RX_PCS_RST,
+ WA_POSITION => wa_position_rx,
+ STATE_OUT => rx_fsm_state
+ );
+
+THE_TX_FSM : tx_reset_fsm
+ port map(
+ RST_N => RST_N,
+ TX_REFCLK => CLK_REF,
+ TX_PLL_LOL_QD_S => TX_LOL,
+ RST_QD_C => QUAD_RST,
+ TX_PCS_RST_CH_C => TX_PCS_RST,
+ STATE_OUT => tx_fsm_state
+ );
+
+
+SYNC_WA_POSITION : process begin
+ wait until rising_edge(CLK_REF);
+ if IS_SYNC_SLAVE = 1 then
+ wa_position_rx <= WA_POSITION;
+ else
+ wa_position_rx <= x"0";
+ end if;
+end process;
+
+-------------------------------------------------
+-- RX & TX allow
+-------------------------------------------------
+--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
+PROC_ALLOW : process begin
+ wait until rising_edge(CLK_SYS);
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
+ rx_allow <= '1';
+ else
+ rx_allow <= '0';
+ end if;
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
+ tx_allow <= '1';
+ else
+ tx_allow <= '0';
+ end if;
+end process;
+
+
+PROC_START_TIMER : process begin
+ wait until rising_edge(CLK_SYS);
+ if got_link_ready_i = '1' then
+ if start_timer(start_timer'left) = '0' then
+ start_timer <= start_timer + 1;
+ end if;
+ else
+ start_timer <= (others => '0');
+ end if;
+end process;
+
+-------------------------------------------------
+-- TX Data
+-------------------------------------------------
+THE_TX : tx_control
+ port map(
+ CLK_200 => CLK_TXI, --JM06 clk_200_i,
+ CLK_100 => CLK_SYS,
+ RESET_IN => reset_i,
+
+ TX_DATA_IN => MEDIA_INT2MED.data,
+ TX_PACKET_NUMBER_IN => MEDIA_INT2MED.packet_num,
+ TX_WRITE_IN => MEDIA_INT2MED.dataready,
+ TX_READ_OUT => media_med2int_i.tx_read,
+
+ TX_DATA_OUT => TX_DATA,
+ TX_K_OUT => TX_K,
+
+ REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
+ REQUEST_POSITION_IN => request_retr_position_i, --TODO
+
+ START_RETRANSMIT_IN => start_retr_i, --TODO
+ START_POSITION_IN => start_retr_position_i, --TODO
+
+ SEND_DLM => TX_DLM,
+ SEND_DLM_WORD => TX_DLM_WORD,
+
+ SEND_LINK_RESET_IN => MEDIA_INT2MED.ctrl_op(15),
+ TX_ALLOW_IN => tx_allow,
+ RX_ALLOW_IN => rx_allow,
+
+ DEBUG_OUT => DEBUG_TX_CONTROL,
+ STAT_REG_OUT => STAT_TX_CONTROL
+ );
+
+
+-------------------------------------------------
+-- RX Data
+-------------------------------------------------
+THE_RX_CONTROL : rx_control
+ port map(
+ CLK_200 => CLK_RXI, --JM06 clk_200_i,
+ CLK_100 => CLK_SYS,
+ RESET_IN => reset_i,
+
+ RX_DATA_OUT => media_med2int_i.data,
+ RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num,
+ RX_WRITE_OUT => media_med2int_i.dataready,
+-- RX_READ_IN => '1',
+
+ RX_DATA_IN => RX_DATA,
+ RX_K_IN => RX_K,
+
+ REQUEST_RETRANSMIT_OUT => request_retr_i,
+ REQUEST_POSITION_OUT => request_retr_position_i,
+
+ START_RETRANSMIT_OUT => start_retr_i,
+ START_POSITION_OUT => start_retr_position_i,
+
+ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
+ RX_DLM => rx_dlm_i,
+ RX_DLM_WORD => RX_DLM_WORD,
+
+ SEND_LINK_RESET_OUT => send_link_reset_i,
+ MAKE_RESET_OUT => make_link_reset_i,
+ RX_ALLOW_IN => rx_allow,
+ GOT_LINK_READY => got_link_ready_i,
+
+ DEBUG_OUT => DEBUG_RX_CONTROL,
+ STAT_REG_OUT => STAT_RX_CONTROL
+ );
+
+RX_DLM <= rx_dlm_i;
+MEDIA_MED2INT <= media_med2int_i;
+
+-------------------------------------------------
+-- Generate LED signals
+-------------------------------------------------
+led_ok <= rx_allow and tx_allow when rising_edge(CLK_SYS);
+led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS);
+led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_i) and not timer(20) when rising_edge(CLK_SYS);
+led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(CLK_SYS);
+
+ROC_TIMER : process begin
+ wait until rising_edge(CLK_SYS);
+ timer <= timer + 1 ;
+ if timer(20) = '1' then
+ timer <= (others => '0');
+ last_led_rx <= led_rx ;
+ last_led_tx <= led_tx;
+ last_led_dlm <= led_dlm;
+ end if;
+end process;
+
+-------------------------------------------------
+-- Status signals
+-------------------------------------------------
+
+STAT_RESET(3 downto 0) <= rx_fsm_state;
+STAT_RESET(7 downto 4) <= tx_fsm_state;
+STAT_RESET(8) <= tx_allow;
+STAT_RESET(9) <= rx_allow;
+STAT_RESET(31 downto 10) <= (others => '0');
+
+make_link_reset_real_i <= make_link_reset_i when IS_SYNC_SLAVE = 1 else '0';
+sd_los_i <= SFP_LOS when rising_edge(CLK_SYS);
+
+media_med2int_i.stat_op(15) <= send_link_reset_i when rising_edge(CLK_SYS);
+media_med2int_i.stat_op(14) <= '0';
+media_med2int_i.stat_op(13) <= make_link_reset_real_i when rising_edge(CLK_SYS); --make trbnet reset
+media_med2int_i.stat_op(12) <= led_dlm or last_led_dlm;
+media_med2int_i.stat_op(11) <= led_tx or last_led_tx;
+media_med2int_i.stat_op(10) <= led_rx or last_led_rx;
+media_med2int_i.stat_op(9) <= led_ok;
+media_med2int_i.stat_op(8 downto 4) <= (others => '0');
+media_med2int_i.stat_op(3 downto 0) <= x"0" when rx_allow = '1' and tx_allow = '1' else x"7";
+
+end architecture;
\ No newline at end of file
RX_DATA_OUT : out std_logic_vector(15 downto 0);
RX_PACKET_NUMBER_OUT : out std_logic_vector(2 downto 0);
RX_WRITE_OUT : out std_logic;
- RX_READ_IN : in std_logic;
RX_DATA_IN : in std_logic_vector( 7 downto 0);
RX_K_IN : in std_logic;
SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
--Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
-- Status and control port
STAT_OP : out std_logic_vector (15 downto 0);
CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
RX_DATA_OUT : out std_logic_vector(15 downto 0);
RX_PACKET_NUMBER_OUT : out std_logic_vector(2 downto 0);
RX_WRITE_OUT : out std_logic;
- RX_READ_IN : in std_logic;
+-- RX_READ_IN : in std_logic;
RX_DATA_IN : in std_logic_vector( 7 downto 0);
RX_K_IN : in std_logic;
type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, MAKE_RESET, START_RETR);
signal rx_state : rx_state_t;
signal rx_state_bits : std_logic_vector(3 downto 0);
-signal rx_packet_num : std_logic_vector(2 downto 0) := "100";
+signal rx_packet_num : std_logic_vector(2 downto 0);
signal buf_rx_write_out : std_logic := '0';
signal rx_data : std_logic_vector(17 downto 0);
next_sop <= '0';
rx_data(15 downto 8)<= reg_rx_data_in;
rx_data(16) <= next_sop;
+ rx_data(17) <= '0';
ct_fifo_write <= '1';
rx_state <= FIRST;
else
STAT_REG_OUT(7) <= ct_fifo_write;
STAT_REG_OUT(15 downto 8) <= reg_rx_data_in(7 downto 0);
STAT_REG_OUT(16) <= rx_data(16);
+STAT_REG_OUT(17) <= '0';
STAT_REG_OUT(31 downto 18) <= (others => '0');
end process;
-process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, timer1, rx_lol_los_int, timer2)
+process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, timer1, rx_lol_los_int, timer2, wa_position, rx_lol_los_del)
begin
-- reset_timer1 <= '0';
reset_timer2 <= '0';
use work.trb3_components.all;
use work.config.all;
-entity trb3sc_tools is
+entity sci_reader is
port(
CLK : in std_logic;
begin
-gen_output : for i in 0 to 3 generate
- -- Master does not do bit-locking
- SYNC_WA_POSITION : process begin
- wait until rising_edge(CLK);
- if IS_SYNC_SLAVE(i) = 1 then
- WA_POS_OUT(i*4+3 downto i*4) <= wa_position(i*4+3 downto i*4);
- else
- WA_POS_OUT(i*4+3 downto i*4) <= x"0000";
- end if;
- end process;
-end generate;
+-- gen_output : for i in 0 to 3 generate
+-- -- Master does not do bit-locking
+-- SYNC_WA_POSITION : process begin
+-- wait until rising_edge(CLK);
+-- if IS_SYNC_SLAVE(i) = 1 then
+-- WA_POS_OUT(i*4+3 downto i*4) <= wa_position(i*4+3 downto i*4);
+-- else
+-- WA_POS_OUT(i*4+3 downto i*4) <= x"0000";
+-- end if;
+-- end process;
+-- end generate;
+WA_POS_OUT <= wa_position;
-------------------------------------------------
-- SCI
-------------------------------------------------
--gives access to serdes config port from slow control and reads word alignment every ~ 40 us
+ BUS_TX.unknown <= '0';
+ BUS_TX.rack <= '0';
+ BUS_TX.wack <= '0';
+
PROC_SCI_CTRL: process
variable cnt : integer range 0 to 4 := 0;
begin
wait until rising_edge(CLK);
BUS_TX.ack <= '0';
BUS_TX.nack <= '0';
-
case sci_state is
when IDLE =>
SCI_SEL <= (others => '0');
sci_state <= IDLE;
else
sci_state <= GET_WA_WAIT;
- SCI_ADDR <= '0' & x"22";
- SCI_SEL <= x"0";
+ SCI_ADDR <= "100010";--'0' & x"22";
+ SCI_SEL <= (others => '0');
SCI_SEL(cnt) <= '1';
SCI_RD <= '1';
end if;
----------------------------------------------------------------------
- THE_RAM_WR_PROC : process(CLK_200, RESET_IN)
+ THE_RAM_WR_PROC : process(CLK_200)
begin
- if RESET_IN = '1' then
- ram_write <= '0';
- elsif rising_edge(CLK_200) then
+-- if RESET_IN = '1' then
+-- ram_write <= '0';
+-- els
+ if rising_edge(CLK_200) then
ram_write <= last_ct_fifo_read and not last_ct_fifo_empty;
end if;
end process;
end process;
--RAM read pointer
- THE_READ_CNT : process(CLK_200, RESET_IN)
+ THE_READ_CNT : process(CLK_200)
begin
- if RESET_IN = '1' then
- ram_read_addr <= (others => '0');
- elsif rising_edge(CLK_200) then
+-- if RESET_IN = '1' then
+-- ram_read_addr <= (others => '0');
+-- els
+ if rising_edge(CLK_200) then
if tx_allow_qtx = '0' then
ram_read_addr <= (others => '0');
elsif load_read_pointer_i = '1' then
end process;
--RAM write pointer
- THE_WRITE_CNT : process(CLK_200, RESET_IN)
+ THE_WRITE_CNT : process(CLK_200)
begin
- if RESET_IN = '1' then
- ram_write_addr <= (others => '0');
- elsif rising_edge(CLK_200) then
+-- if RESET_IN = '1' then
+-- ram_write_addr <= (others => '0');
+-- els
+ if rising_edge(CLK_200) then
if tx_allow_qtx = '0' then
ram_write_addr <= (others => '0');
elsif ram_write = '1' then
--RAM fill level counter
- THE_FILL_CNT : process(CLK_200, RESET_IN)
+ THE_FILL_CNT : process(CLK_200)
begin
- if RESET_IN = '1' then
- ram_fill_level <= (others => '0');
- elsif rising_edge(CLK_200) then
+-- if RESET_IN = '1' then
+-- ram_fill_level <= (others => '0');
+-- els
+ if rising_edge(CLK_200) then
if tx_allow_qtx = '0' then
ram_fill_level <= (others => '0');
else
DEBUG_OUT(4) <= ram_empty;
DEBUG_OUT(5) <= ram_afull;
DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200);
- DEBUG_OUT(31 downto 7) <= (others => '0');
+ DEBUG_OUT(15 downto 7) <= (others => '0');
+ DEBUG_OUT(23 downto 16) <= tx_data_200(7 downto 0);
+ DEBUG_OUT(31 downto 24) <= ram_dout(7 downto 0);
process(CLK_100)
begin
CLK_EN : in std_logic := '1';
-- Media direction port
- MED_DATAREADY_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
-
+ MEDIA_MED2INT : in MED2INT;
+ MEDIA_INT2MED : out INT2MED;
+
--Timing trigger in
TRG_TIMING_TRG_RECEIVED_IN : in std_logic;
ONEWIRE_INOUT : inout std_logic; --temperature sensor
--Config endpoint id, if not statically assigned
REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');
-
- --Timing registers
- TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds
- TIME_LOCAL_OUT : out std_logic_vector ( 7 downto 0); --local time running with chip frequency
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger
- TIME_TICKS_OUT : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick
+ TIMERS_OUT : out TIMERS;
--Debugging & Status information
STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
ADDRESS_MASK => ADDRESS_MASK,
BROADCAST_BITMASK => BROADCAST_BITMASK,
BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
- REGIO_NUM_STAT_REGS => 0,
- REGIO_NUM_CTRL_REGS => 0,
+ REGIO_NUM_STAT_REGS => 1,
+ REGIO_NUM_CTRL_REGS => 1,
REGIO_INIT_CTRL_REGS => (others => '0'),
REGIO_INIT_ADDRESS => INIT_ADDRESS,
REGIO_INIT_BOARD_INFO => HARDWARE_INFO,
RESET => RESET,
CLK_EN => CLK_EN,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
- MED_STAT_OP_IN => MED_STAT_OP_IN,
- MED_CTRL_OP_OUT => MED_CTRL_OP_OUT,
+ MED_DATAREADY_OUT => MEDIA_INT2MED.dataready,
+ MED_DATA_OUT => MEDIA_INT2MED.data,
+ MED_PACKET_NUM_OUT => MEDIA_INT2MED.packet_num,
+ MED_READ_IN => MEDIA_MED2INT.tx_read,
+ MED_DATAREADY_IN => MEDIA_MED2INT.dataready,
+ MED_DATA_IN => MEDIA_MED2INT.data,
+ MED_PACKET_NUM_IN => MEDIA_MED2INT.packet_num,
+ MED_READ_OUT => open,
+ MED_STAT_OP_IN => MEDIA_MED2INT.stat_op,
+ MED_CTRL_OP_OUT => MEDIA_INT2MED.ctrl_op,
-- LVL1 trigger APL
TRG_TIMING_TRG_RECEIVED_IN => TRG_TIMING_TRG_RECEIVED_IN,
DEBUG_LVL1_HANDLER_OUT => DEBUG_LVL1_HANDLER_OUT
);
+TIMERS_OUT.microsecond <= time_global_i;
+TIMERS_OUT.clock <= time_local_i;
+TIMERS_OUT.last_trigger <= time_since_last_trg_i;
+TIMERS_OUT.tick_ms <= time_ticks_i(1);
+TIMERS_OUT.tick_us <= time_ticks_i(0);
+
---------------------------------------------------------------------------
-- RegIO Bus Handler
---------------------------------------------------------------------------
-- stat_reg_i <= REGIO_STAT_REG_IN;
- TIME_GLOBAL_OUT <= time_global_i;
- TIME_LOCAL_OUT <= time_local_i;
- TIME_SINCE_LAST_TRG_OUT <= time_since_last_trg_i;
- TIME_TICKS_OUT <= time_ticks_i;
process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,clk)
begin
data_finished : std_logic;
end record;
+
+ type TIMERS is record
+ microsecond : std_logic_vector (31 downto 0); --global time, microseconds
+ clock : std_logic_vector ( 7 downto 0); --local time running with chip frequency
+ last_trigger : std_logic_vector (31 downto 0); --local time, resetted with each trigger
+ tick_ms : std_logic;
+ tick_us : std_logic;
+ end record;
+ type MED2INT is record
+ data : std_logic_vector(15 downto 0);
+ packet_num: std_logic_vector(2 downto 0);
+ dataready : std_logic;
+ tx_read : std_logic;
+ stat_op : std_logic_vector(15 downto 0);
+ clk_half : std_logic;
+ clk_full : std_logic;
+ end record;
+
+ type INT2MED is record
+ data : std_logic_vector(15 downto 0);
+ packet_num: std_logic_vector(2 downto 0);
+ dataready : std_logic;
+ ctrl_op : std_logic_vector(15 downto 0);
+ end record;
+
type std_logic_vector_array_36 is array (integer range <>) of std_logic_vector(35 downto 0);
type std_logic_vector_array_32 is array (integer range <>) of std_logic_vector(31 downto 0);
type ctrlbus_tx_array_t is array (integer range <>) of CTRLBUS_TX;
type ctrlbus_rx_array_t is array (integer range <>) of CTRLBUS_RX;
type readout_tx_array_t is array (integer range <>) of READOUT_TX;
-
+ type med2int_array_t is array (integer range <>) of MED2INT;
+ type int2med_array_t is array (integer range <>) of INT2MED;
+
--function declarations
function and_all (arg : std_logic_vector)
return std_logic;
jspc29 / trbnet.git / commitdiff