--- /dev/null
+// --------------------------------------------------------------------
+// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// --------------------------------------------------------------------
+// Copyright (c) 2001 - 2012 by Lattice Semiconductor Corporation
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code for use
+// in synthesis for any Lattice programmable logic product. Other
+// use of this code, including the selling or duplication of any
+// portion is strictly prohibited.
+//
+// Disclaimer:
+//
+// This verilog source code is intended as a design reference
+// which illustrates how these types of functions can be implemented.
+// It is the user's responsibility to verify their design for
+// consistency and functionality through the use of formal
+// verification methods. Lattice Semiconductor provides no warranty
+// regarding the use or functionality of this code.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-268-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
+//
+// --------------------------------------------------------------------
+// Code Revision History :
+// --------------------------------------------------------------------
+// Ver: | Author |Mod. Date |Changes Made:
+// V1.0 | Vijay |3/09/12 |Initial ver
+// V1.1 | SHossner|6/08/12 |Added READ_DELAY parameter
+//
+// --------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+`include "efb_define_def.v"
+
+module UFM_WB(
+ input clk_i
+ , input rst_n
+ , input[2:0] cmd
+ , input[10:0] ufm_page
+ , input GO
+ , output reg BUSY
+ , output reg ERR
+
+ /***************** DPRAM port B signals *************/
+ , output reg mem_clk
+ , output reg mem_we
+ , output reg mem_ce
+ , output reg[3:0] mem_addr
+ , output reg[7:0] mem_wr_data
+ , input [7:0] mem_rd_data
+
+);
+
+//*****************
+// For clk_i speeds less than 16.6MHz, set READ_DELAY to zero for fastest UFM read operation
+// For clk_i speeds greater than 16.6MHz, set READ_DELAY as follows:
+// Calculate minimum READ_DELAY as follows:
+// READ_DELAY(min) = 240/PERIOD - 4
+// Where PERIOD = clk_i period in ns
+// Example, for clk_i = 45MHz, PERIOD = 22.22ns and READ_DELAY = 7 (6.8 rounded up)
+//
+// Or choose from the following table:
+// READ_DELAY | Max Clk_i
+// ------------+-------------
+// 0 | 16.6 Mhz
+// 2 | 25.0 Mhz
+// 4 | 33.3 Mhz
+// 8 | 50.0 Mhz
+// 12 | 66.6 Mhz
+// 14 | 75.0 Mhz
+
+parameter READ_DELAY = 4;
+//*****************
+
+wire ufm_enable_cmd;
+wire ufm_read_cmd;
+wire ufm_write_cmd;
+wire ufm_erase_cmd;
+wire ufm_disable_cmd;
+reg ufm_enabled;
+reg n_ufm_enabled;
+wire ufm_repeated_read;
+wire ufm_repeated_write;
+
+reg [7:0] wb_dat_i ;
+reg wb_stb_i ;
+wire wb_cyc_i = wb_stb_i ;
+reg [7:0] wb_adr_i ;
+reg wb_we_i ;
+wire [7:0] wb_dat_o ;
+wire wb_ack_o ;
+
+reg [7:0] n_wb_dat_i ;
+reg n_wb_stb_i ;
+reg [7:0] n_wb_adr_i ;
+reg n_wb_we_i ;
+reg n_busy;
+reg n_error;
+reg [7:0] c_state ,n_state;
+reg efb_flag,n_efb_flag;
+reg[7:0] sm_wr_data;
+reg[3:0] sm_addr;
+reg sm_ce;
+reg sm_we;
+reg[4:0] count;
+reg sm_addr_MSB;
+reg[7:0] sm_rd_data;
+
+
+reg[7:0] n_data_frm_ufm;
+reg[3:0] n_addr_ufm;
+reg n_clk_en_ufm;
+reg n_wr_en_ufm;
+reg[4:0] n_count;
+reg n_ufm_addr_MSB;
+
+flash inst1 ( .wb_clk_i(clk_i ), // EFB with UFM enabled
+ .wb_rst_i(!rst_n ),
+ .wb_cyc_i(wb_cyc_i ),
+ .wb_stb_i(wb_stb_i ),
+ .wb_we_i(wb_we_i ),
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i ),
+ .wb_dat_o(wb_dat_o ),
+ .wb_ack_o(wb_ack_o ),
+ .wbc_ufm_irq( )
+ );
+
+// flashram inst2 ( .DataInA(sm_wr_data ), // True dual port RAM. Port A controlled by internal SM and port B controlled by user.
+// .DataInB(mem_wr_data ),
+// .AddressA({sm_addr_MSB,sm_addr} ),
+// .AddressB({!sm_addr_MSB,mem_addr} ),
+// .ClockA(clk_i ),
+// .ClockB(mem_clk ),
+// .ClockEnA(sm_ce ),
+// .ClockEnB(mem_ce ),
+// .WrA(sm_we ),
+// .WrB(mem_we ),
+// .ResetA(!rst_n ),
+// .ResetB(!rst_n ),
+// .QA(sm_rd_data ),
+// .QB(mem_rd_data ));
+
+
+always @ (*)
+ begin
+ sm_rd_data <= mem_rd_data;
+ mem_we <= sm_we;
+ mem_clk <= clk_i;
+ mem_addr <= sm_addr;
+ mem_wr_data <= sm_wr_data;
+ end
+
+ assign ufm_enable_cmd = (cmd == 3'b100) ? 1'b1 : 1'b0 ;
+ assign ufm_read_cmd = ((cmd == 3'b000) || (cmd == 3'b001)) ? 1'b1 : 1'b0 ;
+ assign ufm_write_cmd = ((cmd == 3'b010) || (cmd == 3'b011)) ? 1'b1 : 1'b0 ;
+ assign ufm_erase_cmd = (cmd == 3'b111) ? 1'b1 : 1'b0 ;
+ assign ufm_disable_cmd = (cmd == 3'b101) ? 1'b1 : 1'b0 ;
+ assign ufm_repeated_read = (cmd == 3'b001) ? 1'b1 : 1'b0 ;
+ assign ufm_repeated_write = (cmd == 3'b011) ? 1'b1 : 1'b0 ;
+
+
+
+always @ (posedge clk_i or negedge rst_n) // generate clk enable and write enable signals for port A of the DPRAM
+ begin
+ if(!rst_n)
+ begin
+ sm_ce <= 1'b0;
+ sm_we <= 1'b0;
+ end
+ else if (((c_state == `state58) && (n_state == `state59)) || ((c_state == `state51)))
+ begin
+ sm_ce <= 1'b0;
+ sm_we <= 1'b0;
+ end
+ else if ((n_state == `state58) || ((c_state == `state50) && (n_state == `state51)))
+ begin
+ sm_ce <= 1'b1;
+ if (ufm_read_cmd)
+ sm_we <= 1'b1;
+ else
+ sm_we <= 1'b0;
+ end
+ else
+ begin
+ sm_ce <= 1'b0;
+ sm_we <= 1'b0;
+ end
+ end
+
+
+always @ (posedge clk_i or negedge rst_n)
+ begin
+ if(!rst_n)
+ begin
+ wb_dat_i <= 8'h00;
+ wb_stb_i <= 1'b0 ;
+ wb_adr_i <= 8'h00;
+ wb_we_i <= 1'b0;
+ end
+ else
+ begin
+ wb_dat_i <= n_wb_dat_i;
+ wb_stb_i <= #0.1 n_wb_stb_i;
+ wb_adr_i <= n_wb_adr_i;
+ wb_we_i <= n_wb_we_i ;
+
+ end
+ end
+
+ always @ (posedge clk_i or negedge rst_n)
+ begin
+ if(!rst_n) begin
+ c_state <= 10'h000;
+ BUSY <= 1'b1;
+ efb_flag <= 1'b0 ;
+ ERR <= 1'b0;
+ ufm_enabled <= 1'b0;
+ sm_wr_data <= 8'h00;
+ sm_addr <= 4'b0000;
+ count <= 4'hF;
+ sm_addr_MSB <= 1'b0;
+ end
+ else begin
+ c_state <= n_state ;
+ BUSY <= n_busy;
+ efb_flag <= n_efb_flag;
+ ERR <= n_error;
+ ufm_enabled <= n_ufm_enabled;
+ sm_wr_data <= n_data_frm_ufm;
+ sm_addr <= n_addr_ufm;
+ count <= n_count;
+ sm_addr_MSB <= n_ufm_addr_MSB;
+ end
+ end
+
+
+
+ always @ (*)
+ begin
+ n_state = c_state;
+ n_efb_flag = 1'b0 ;
+ n_busy = BUSY;
+ n_error = ERR;
+ n_ufm_enabled = ufm_enabled;
+ n_data_frm_ufm = sm_wr_data;
+ n_addr_ufm = sm_addr;
+ n_clk_en_ufm = sm_ce;
+ n_wr_en_ufm = sm_we;
+ n_count = count;
+ n_ufm_addr_MSB = sm_addr_MSB;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = 1'b0 ;
+ n_wb_adr_i = 8'h00;
+ n_wb_we_i = 1'b0;
+ n_efb_flag = 1'b0 ;
+ case (c_state)
+
+ `state0 : begin
+ n_wb_dat_i = 8'h00;
+ n_wb_adr_i = 8'h00;
+ n_efb_flag = 1'b0 ;
+ n_wb_we_i = 1'b0;
+ n_wb_stb_i = 1'b0 ;
+ n_busy = 1'b1;
+ n_error = 1'b0;
+ n_ufm_enabled = 1'b0;
+ n_state = `state1; // (state1 - state8)--check if UFM is busy and deassert BUSY flag if free.
+ end
+
+ `state1: begin // enable WB-UFM interface
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state2;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state2: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state3;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'hF0;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state3: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state4;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state4: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state5;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state5: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state6;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_efb_flag = 1'b1 ;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state6: begin // Return Back to State 2
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ if(wb_dat_o & (8'h80) )
+ n_state = `state7;
+ else
+ n_state = `state8;
+ end
+ else begin
+ n_wb_we_i = `READ_STATUS;
+ n_wb_adr_i = `CFGRXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ n_state = c_state;
+ end
+ end
+
+ `state7: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state1;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_busy = 1'b1;
+ n_state = c_state;
+ end
+ end
+
+ `state8: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_busy = 1'b0;
+ n_state = `state9;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_busy = 1'b1;
+ n_state = c_state;
+ end
+ end
+
+ `state9: begin
+ if (GO)
+ begin
+ n_busy = 1'b1;
+ n_error = 1'b0;
+ if (ufm_enabled && ufm_write_cmd)
+ n_ufm_addr_MSB = !sm_addr_MSB;
+ n_state = `state10;
+ end
+ else
+ begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_busy = 1'b0;
+ n_error = ERR;
+ n_state = c_state;
+ end
+ end
+
+
+ `state10: begin
+ if(ufm_enable_cmd) // enable UFM
+ n_state = `state11;
+ else if (ufm_enabled)begin // decode command only if UFM is already enabled
+ if (ufm_read_cmd)
+ n_state = `state35;
+ else if (ufm_write_cmd)
+ n_state = `state35;
+ else if (ufm_erase_cmd)
+ n_state = `state17;
+ else if (ufm_disable_cmd)
+ n_state = `state23;
+ end
+ else begin // set ERR if a command is sent when UFM is disabled and go to previous state and wait for GO
+ n_busy = 1'b0;
+ n_error = 1'b1;
+ n_state = `state9;
+ end
+ end
+
+ `state11: begin // (state11 - state16) enable UFM
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state12;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_efb_flag = 1'b1 ;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state12: begin // enable configuration
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state13;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h74;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state13: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state14;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h08;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state14: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state15;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_efb_flag = 1'b1 ;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state15: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state16;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state16: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_ufm_enabled = 1'b1;
+ n_state = `state1; // check for busy flag after enabling UFM
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_ufm_enabled = 1'b0;
+ n_state = c_state;
+ end
+ end
+
+
+ `state17: begin // (state17- state22) erase UFM
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state18;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_efb_flag = 1'b1 ;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state18: begin
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state19;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'hCB;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state19: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state20;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state20: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state21;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_efb_flag = 1'b1 ;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state21: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state22;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+ `state22: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state1; // check for busy flag after erasing UFM
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state23: begin // open frame // (state23 - state 32) disable UFM
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state24;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_efb_flag = 1'b1 ;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state24: begin // disable configuration
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state25;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h26;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state25: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state26;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state26: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state27;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_efb_flag = 1'b1 ;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state27: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state28;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+ `state28: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state29;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+ `state29: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state30;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h80;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+ `state30: begin // bypass command
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state31;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'hFF;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state31: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state32;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'hFF;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state32: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state33;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'hFF;
+ n_efb_flag = 1'b1 ;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state33: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_state = `state34;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'hFF;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state34: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_busy = 1'b0;
+ n_ufm_enabled = 1'b0;
+ n_state = `state9;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state35: begin // (state35 - state60 ) UFM read/write operations
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ if (ufm_repeated_read)
+ n_state = `state46;
+ else if (ufm_repeated_write)
+ n_state = `state54;
+ else
+ n_state = `state36;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state36: begin // Set UFM Page Address
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state37;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'hB4;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state37: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state38;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state38: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state39;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state39: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state40;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state40: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state41;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h40;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state41: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state42;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state42: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state43;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = {5'b00000,ufm_page[10:8]};
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state43: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state44;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = ufm_page[7:0];
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+ `state44: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ if (ufm_write_cmd)
+ n_state = `state53;
+ else
+ n_state = `state45;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+ `state45: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state46;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h80;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+ `state46: begin // Read Operation
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_count = READ_DELAY;
+ n_state = `stateRD_delay;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'hCA;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+ `stateRD_delay: begin
+ if (count == 0)
+ n_state = `state47;
+ else begin
+ n_count = count - 1;
+ n_state = `stateRD_delay;
+ end
+ end
+
+ `state47: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state48;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h10;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state48: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state49;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state49: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_count = 5'b10000;
+ n_addr_ufm = 4'h0;
+ n_clk_en_ufm = 1'b1;
+ n_state = `state50;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h01;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state51: begin //
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_addr_ufm = sm_addr + 1;
+ if (count == 0)
+ n_state = `state52;
+ else begin
+ n_state = `state50;
+ end
+ end
+
+ `state50: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_count = count - 1;
+ n_data_frm_ufm = wb_dat_o;
+ n_state = `state51;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `READ_DATA;
+ n_wb_adr_i = `CFGRXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+ `state52: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_ufm_addr_MSB = !sm_addr_MSB;
+ n_busy = 1'b0;
+ n_state = `state9;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_busy = 1'b1;
+ n_state = c_state;
+ end
+ end
+
+ `state53: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state54;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h80;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+ `state54: begin // Write Operation
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state55;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'hC9;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state55: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state56;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state56: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_state = `state57;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state57: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_count = 5'b10000;
+ n_addr_ufm = 4'h0;
+ n_clk_en_ufm = 1'b1;
+ n_wr_en_ufm = 1'b0;
+ n_state = `state58;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h01;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+
+ `state58: begin //
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_count = count - 1;
+ n_state = `state59;
+ end
+
+ `state59: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ n_addr_ufm = sm_addr + 1;
+ if (count == 0)
+ n_state = `state60;
+ else begin
+ n_state = `state58;
+ end
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = sm_rd_data;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+
+ `state60: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_efb_flag = 1'b0 ;
+ n_wb_stb_i = `LOW ;
+ n_state = `state1;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_state = c_state;
+ end
+ end
+ endcase
+ end
+
+
+
+endmodule
+
+
+
\ No newline at end of file
--- /dev/null
+/****************************************************************************\r
+**\r
+** Description:\r
+** `define Define for PULI Utility\r
+**\r
+** Disclaimer:\r
+** This source code is intended as a design reference which\r
+** illustrates how these types of functions can be implemented. It\r
+** is the user's responsibility to verify their design for\r
+** consistency and functionality through the use of formal\r
+** verification methods. Lattice Semiconductor provides no warranty\r
+** regarding the use or functionality of this code.\r
+**\r
+*****************************************************************************\r
+**\r
+** Lattice Semiconductor Corporation\r
+** 5555 NE Moore Court\r
+** Hillsboro, OR 97214\r
+** U.S.A\r
+**\r
+** TEL: 1-800-Lattice (USA and Canada )\r
+** (503 268-8001 (other locations )\r
+**\r
+** web: http://www.latticesemi.com\r
+** email: techsupport@latticesemi.com\r
+**\r
+*****************************************************************************\r
+** Change History (Latest changes on top )\r
+**\r
+** Ver Date Person\r
+** --------------------------------------------------------------------------\r
+** 3.0 13/9/2011 Akhilesh LBN\r
+**\r
+*****************************************************************************/\r
+\r
+\r
+/***********************************************************************\r
+ * *\r
+ * EFB REGISTER SET *\r
+ * *\r
+ ***********************************************************************/\r
+\r
+ \r
+`define MICO_EFB_I2C_CR 8'h40 //4a\r
+`define MICO_EFB_I2C_CMDR 8'h41 //4b\r
+`define MICO_EFB_I2C_BLOR 8'h42 //4c\r
+`define MICO_EFB_I2C_BHIR 8'h43 //4d\r
+`define MICO_EFB_I2C_TXDR 8'h44 //4e\r
+`define MICO_EFB_I2C_SR 8'h45 //4f\r
+`define MICO_EFB_I2C_GCDR 8'h46 //50\r
+`define MICO_EFB_I2C_RXDR 8'h47 //51\r
+`define MICO_EFB_I2C_IRQSR 8'h48 //52\r
+`define MICO_EFB_I2C_IRQENR 8'h49 //53\r
+\r
+`define MICO_EFB_SPI_CR0 8'h54 \r
+`define MICO_EFB_SPI_CR1 8'h55 \r
+`define MICO_EFB_SPI_CR2 8'h56 \r
+`define MICO_EFB_SPI_BR 8'h57 \r
+`define MICO_EFB_SPI_CSR 8'h58 \r
+`define MICO_EFB_SPI_TXDR 8'h59 \r
+`define MICO_EFB_SPI_SR 8'h5a \r
+`define MICO_EFB_SPI_RXDR 8'h5b \r
+`define MICO_EFB_SPI_IRQSR 8'h5c \r
+`define MICO_EFB_SPI_IRQENR 8'h5d \r
+\r
+\r
+`define MICO_EFB_TIMER_CR0 8'h5E \r
+`define MICO_EFB_TIMER_CR1 8'h5F \r
+`define MICO_EFB_TIMER_TOP_SET_LO 8'h60 \r
+`define MICO_EFB_TIMER_TOP_SET_HI 8'h61 \r
+`define MICO_EFB_TIMER_OCR_SET_LO 8'h62 \r
+`define MICO_EFB_TIMER_OCR_SET_HI 8'h63 \r
+`define MICO_EFB_TIMER_CR2 8'h64 \r
+`define MICO_EFB_TIMER_CNT_SR_LO 8'h65 \r
+`define MICO_EFB_TIMER_CNT_SR_HI 8'h66 \r
+`define MICO_EFB_TIMER_TOP_SR_LO 8'h67 \r
+`define MICO_EFB_TIMER_TOP_SR_HI 8'h68 \r
+`define MICO_EFB_TIMER_OCR_SR_LO 8'h69 \r
+`define MICO_EFB_TIMER_OCR_SR_HI 8'h6A \r
+`define MICO_EFB_TIMER_ICR_SR_LO 8'h6B \r
+`define MICO_EFB_TIMER_ICR_SR_HI 8'h6C \r
+`define MICO_EFB_TIMER_SR 8'h6D \r
+`define MICO_EFB_TIMER_IRQSR 8'h6E \r
+`define MICO_EFB_TIMER_IRQENR 8'h6F \r
+\r
+ \r
+/***********************************************************************\r
+ * *\r
+ * EFB SPI CONTROLLER PHYSICAL DEVICE SPECIFIC INFORMATION *\r
+ * *\r
+ ***********************************************************************/\r
+\r
+\r
+\r
+\r
+// Control Register 1 Bit Masks\r
+`define MICO_EFB_SPI_CR1_SPE 8'h80 \r
+`define MICO_EFB_SPI_CR1_WKUPEN 8'h40 \r
+// Control Register 2 Bit Masks\r
+`define MICO_EFB_SPI_CR2_LSBF 8'h01 \r
+`define MICO_EFB_SPI_CR2_CPHA 8'h02 \r
+`define MICO_EFB_SPI_CR2_CPOL 8'h04 \r
+`define MICO_EFB_SPI_CR2_SFSEL_NORMAL 8'h00 \r
+`define MICO_EFB_SPI_CR2_SFSEL_LATTICE 8'h08 \r
+`define MICO_EFB_SPI_CR2_SRME 8'h20 \r
+`define MICO_EFB_SPI_CR2_MCSH 8'h40 \r
+`define MICO_EFB_SPI_CR2_MSTR 8'h80 \r
+// Status Register Bit Masks\r
+`define MICO_EFB_SPI_SR_TIP 8'h80 \r
+`define MICO_EFB_SPI_SR_TRDY 8'h10 \r
+`define MICO_EFB_SPI_SR_RRDY 8'h08 \r
+`define MICO_EFB_SPI_SR_TOE 8'h04 \r
+`define MICO_EFB_SPI_SR_ROE 8'h02 \r
+`define MICO_EFB_SPI_SR_MDF 8'h01 \r
+\r
+/***********************************************************************\r
+ * *\r
+ * EFB I2C CONTROLLER PHYSICAL DEVICE SPECIFIC INFORMATION *\r
+ * *\r
+ ***********************************************************************/\r
+\r
+\r
+\r
+// Control Register Bit Masks\r
+`define MICO_EFB_I2C_CR_I2CEN 8'h80 \r
+`define MICO_EFB_I2C_CR_GCEN 8'h40 \r
+`define MICO_EFB_I2C_CR_WKUPEN 8'h20 \r
+// Status Register Bit Masks\r
+`define MICO_EFB_I2C_SR_TIP 8'h80 \r
+`define MICO_EFB_I2C_SR_BUSY 8'h40 \r
+`define MICO_EFB_I2C_SR_RARC 8'h20 \r
+`define MICO_EFB_I2C_SR_SRW 8'h10 \r
+`define MICO_EFB_I2C_SR_ARBL 8'h08 \r
+`define MICO_EFB_I2C_SR_TRRDY 8'h04 \r
+`define MICO_EFB_I2C_SR_TROE 8'h02 \r
+`define MICO_EFB_I2C_SR_HGC 8'h01 \r
+// Command Register Bit Masks \r
+`define MICO_EFB_I2C_CMDR_STA 8'h80 \r
+`define MICO_EFB_I2C_CMDR_STO 8'h40 \r
+`define MICO_EFB_I2C_CMDR_RD 8'h20 \r
+`define MICO_EFB_I2C_CMDR_WR 8'h10 \r
+`define MICO_EFB_I2C_CMDR_NACK 8'h08 \r
+`define MICO_EFB_I2C_CMDR_CKSDIS 8'h04 \r
+\r
+/***********************************************************************\r
+ * *\r
+ * EFB I2C USER DEFINE *\r
+ * *\r
+ ***********************************************************************/\r
+`define MICO_EFB_I2C_TRANSMISSION_DONE 8'h00 \r
+`define MICO_EFB_I2C_TRANSMISSION_ONGOING 8'h80 \r
+`define MICO_EFB_I2C_FREE 8'h00 \r
+`define MICO_EFB_I2C_BUSY 8'h40 \r
+`define MICO_EFB_I2C_ACK_NOT_RCVD 8'h20 \r
+`define MICO_EFB_I2C_ACK_RCVD 8'h00 \r
+`define MICO_EFB_I2C_ARB_LOST 8'h08 \r
+`define MICO_EFB_I2C_ARB_NOT_LOST 8'h00 \r
+`define MICO_EFB_I2C_DATA_READY 8'h04 \r
+\r
+/***********************************************************************\r
+ * *\r
+ * EFB TIMER PHYSICAL DEVICE SPECIFIC INFORMATION *\r
+ * *\r
+ ***********************************************************************/\r
+\r
+\r
+\r
+// Control Register 0\r
+`define MICO_EFB_TIMER_RSTN_MASK 8'h80 \r
+`define MICO_EFB_TIMER_GSRN_MASK 8'h40 \r
+`define MICO_EFB_TIMER_GSRN_ENABLE 8'h40 \r
+`define MICO_EFB_TIMER_GSRN_DISABLE 8'h00 \r
+`define MICO_EFB_TIMER_CCLK_MASK 8'h38 \r
+`define MICO_EFB_TIMER_CCLK_DIV_0 8'h00 \r
+`define MICO_EFB_TIMER_CCLK_DIV_1 8'h08 \r
+`define MICO_EFB_TIMER_CCLK_DIV_8 8'h10 \r
+`define MICO_EFB_TIMER_CCLK_DIV_64 8'h18 \r
+`define MICO_EFB_TIMER_CCLK_DIV_256 8'h20 \r
+`define MICO_EFB_TIMER_CCLK_DIV_1024 8'h28 \r
+`define MICO_EFB_TIMER_SCLK_MASK 8'h07 \r
+`define MICO_EFB_TIMER_SCLK_CIB_RE 8'h00 \r
+`define MICO_EFB_TIMER_SCLK_OSC_RE 8'h02 \r
+`define MICO_EFB_TIMER_SCLK_CIB_FE 8'h04 \r
+`define MICO_EFB_TIMER_SCLK_OSC_FE 8'h06 \r
+// Control Register 1\r
+`define MICO_EFB_TIMER_TOP_SEL_MASK 8'h80 \r
+`define MICO_EFB_TIMER_TOP_MAX 8'h00 \r
+`define MICO_EFB_TIMER_TOP_USER_SELECT 8'h10 \r
+`define MICO_EFB_TIMER_OC_MODE_MASK 8'h0C \r
+`define MICO_EFB_TIMER_OC_MODE_STATIC_ZERO 8'h00 \r
+`define MICO_EFB_TIMER_OC_MODE_TOGGLE 8'h04 \r
+`define MICO_EFB_TIMER_OC_MODE_CLEAR 8'h08 \r
+`define MICO_EFB_TIMER_OC_MODE_SET 8'h0C \r
+`define MICO_EFB_TIMER_MODE_MASK 8'h03 \r
+`define MICO_EFB_TIMER_MODE_WATCHDOG 8'h00 \r
+`define MICO_EFB_TIMER_MODE_CTC 8'h01 \r
+`define MICO_EFB_TIMER_MODE_FAST_PWM 8'h02 \r
+`define MICO_EFB_TIMER_MODE_TRUE_PWM 8'h03 \r
+// Control Register 2\r
+`define MICO_EFB_TIMER_OC_FORCE 8'h04 \r
+`define MICO_EFB_TIMER_CNT_RESET 8'h02 \r
+`define MICO_EFB_TIMER_CNT_PAUSE 8'h01 \r
+// Status Register\r
+`define MICO_EFB_TIMER_SR_OVERFLOW 8'h01 \r
+`define MICO_EFB_TIMER_SR_COMPARE_MATCH 8'h02 \r
+`define MICO_EFB_TIMER_SR_CAPTURE 8'h04 \r
+\r
+\r
+\r
+`define CFGCR 8'h70 \r
+`define CFGTXDR 8'h71 \r
+`define CFGSR 8'h72 \r
+`define CFGRXDR 8'h73 \r
+`define CFGIRQ 8'h74 \r
+`define CFGIRQEN 8'h75 \r
+\r
+/***********************************************************************\r
+ * *\r
+ * PULI SPECIFIC *\r
+ * *\r
+ ***********************************************************************/\r
+ \r
+ `define ALL_ZERO 8'h00 \r
+ `define READ 1'b0 \r
+ `define READ 1'b0 \r
+ `define HIGH 1'b1 \r
+ `define WRITE 1'b1 \r
+ `define LOW 1'b0 \r
+ `define READ_STATUS 1'b0 \r
+ `define READ_DATA 1'b0 \r
+ \r
+/***********************************************************************\r
+ * *\r
+ * State Machine Variables *\r
+ * *\r
+ ***********************************************************************/ \r
+ \r
+\r
+`define state0 7'd00 \r
+`define state1 7'd01 \r
+`define state2 7'd02 \r
+`define state3 7'd03 \r
+`define state4 7'd04 \r
+`define state5 7'd05 \r
+`define state6 7'd06 \r
+`define state7 7'd07 \r
+`define state8 7'd08 \r
+`define state9 7'd09 \r
+`define state10 7'd10 \r
+`define state11 7'd11 \r
+`define state12 7'd12 \r
+`define state13 7'd13 \r
+`define state14 7'd14 \r
+`define state15 7'd15 \r
+`define state16 7'd16 \r
+`define state17 7'd17 \r
+`define state18 7'd18 \r
+`define state19 7'd19 \r
+`define state20 7'd20 \r
+`define state21 7'd21 \r
+`define state22 7'd22 \r
+`define state23 7'd23 \r
+`define state24 7'd24 \r
+`define state25 7'd25 \r
+`define state26 7'd26 \r
+`define state27 7'd27 \r
+`define state28 7'd28 \r
+`define state29 7'd29 \r
+`define state30 7'd30 \r
+`define state31 7'd31 \r
+`define state32 7'd32 \r
+`define state33 7'd33 \r
+`define state34 7'd34 \r
+`define state35 7'd35 \r
+`define state36 7'd36 \r
+`define state37 7'd37 \r
+`define state38 7'd38 \r
+`define state39 7'd39 \r
+`define state40 7'd40 \r
+`define state41 7'd41 \r
+`define state42 7'd42 \r
+`define state43 7'd43 \r
+`define state44 7'd44 \r
+`define state45 7'd45 \r
+`define state46 7'd46 \r
+`define state47 7'd47 \r
+`define state48 7'd48 \r
+`define state49 7'd49 \r
+`define state50 7'd50 \r
+`define state51 7'd51 \r
+`define state52 7'd52 \r
+`define state53 7'd53 \r
+`define state54 7'd54 \r
+`define state55 7'd55 \r
+`define state56 7'd56 \r
+`define state57 7'd57 \r
+`define state58 7'd58 \r
+`define state59 7'd59 \r
+`define state60 7'd60 \r
+`define stateRD_delay 7'd61 \r
+`define state62 7'd62 \r
+`define state63 7'd63 \r
+`define state64 7'd64 \r
+`define state65 7'd65 \r
+`define state66 7'd66 \r
+`define state67 7'd67 \r
+`define state68 7'd68 \r
+`define state69 7'd69 \r
+`define state70 7'd70 \r
+`define state71 7'd71 \r
+`define state72 7'd72 \r
+`define state73 7'd73 \r
+`define state74 7'd74 \r
+`define state75 7'd75 \r
+`define state76 7'd76 \r
+`define state77 7'd77 \r
+`define state78 7'd78 \r
+`define state79 7'd79 \r
+`define state80 7'd80 \r
+`define state81 7'd81 \r
+`define state82 7'd82 \r
+`define state83 7'd83 \r
+`define state84 7'd84 \r
+`define state85 7'd85 \r
+`define state86 7'd86 \r
+`define state87 7'd87 \r
+`define state88 7'd88 \r
+`define state89 7'd89 \r
+`define state90 7'd90 \r
+`define state91 7'd91 \r
+`define state92 7'd92 \r
+`define state93 7'd93 \r
+`define state94 7'd94 \r
+`define state95 7'd95 \r
+`define state96 7'd96 \r
+`define state97 7'd97 \r
+`define state98 7'd98 \r
+`define state99 7'd99 \r
+`define state100 7'd100 \r
+`define state101 7'd101 \r
+`define state102 7'd102 \r
+`define state103 7'd103 \r
+`define state104 7'd104 \r
+`define state105 7'd105 \r
+`define state106 7'd106 \r
+`define state107 7'd107 \r
+`define state108 7'd108 \r
+`define state109 7'd109 \r
+`define state110 7'd110 \r
+`define state111 7'd111 \r
+`define state112 7'd112 \r
+`define state113 7'd113 \r
+`define state114 7'd114 \r
+`define state115 7'd115 \r
+`define state116 7'd116 \r
+`define state117 7'd117 \r
+`define state118 7'd118 \r
+`define state119 7'd119 \r
+`define state120 7'd120 \r
+`define state121 7'd121 \r
+`define state122 7'd122 \r
+`define state123 7'd123 \r
+`define state124 7'd124 \r
+`define state125 7'd125 \r
+`define state126 7'd126 \r
+`define state127 7'd127 \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+
\ No newline at end of file
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 08 03 15:06:03.281" version="1.0" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 08 09 14:22:13.751" version="1.0" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="flash.lpc" type="lpc" modified="2012 08 03 15:05:55.000"/>
- <File name="flash.vhd" type="top_level_vhdl" modified="2012 08 03 15:05:55.000"/>
- <File name="flash_tmpl.vhd" type="template_vhdl" modified="2012 08 03 15:05:55.000"/>
+ <File name="flash.lpc" type="lpc" modified="2012 08 09 14:22:11.000"/>
+ <File name="flash.vhd" type="top_level_vhdl" modified="2012 08 09 14:22:11.000"/>
+ <File name="flash_tmpl.vhd" type="template_vhdl" modified="2012 08 09 14:22:11.000"/>
</Package>
</DiamondModule>
ModuleName=flash
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=08/03/2012
-Time=15:05:55
+Date=08/09/2012
+Time=14:22:11
[Parameters]
Verilog=0
tc_sa_oflow=0
tc_top=65535
ufm=1
-wb_clk_freq=133
+wb_clk_freq=33.33
ufm_usage=SHARED_EBR_TAG
-ufm_ebr=751
+ufm_ebr=0
ufm_remain=
-mem_size=16
+mem_size=767
ufm_start=
ufm_init=0
memfile=
-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87)
-- Module Version: 1.0
---/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 133 -ufm -ufm_ebr 751 -mem_size 16 -ufm_0 -wb -dev 4000 -e
+--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 33.33 -ufm -ufm_ebr 0 -mem_size 767 -ufm_0 -wb -dev 4000 -e
--- Fri Aug 3 15:05:55 2012
+-- Thu Aug 9 14:22:11 2012
library IEEE;
use IEEE.std_logic_1164.all;
--- synopsys translate_off
+-- -- synopsys translate_off
library MACHXO2;
use MACHXO2.components.all;
--- synopsys translate_on
+-- -- synopsys translate_on
entity flash is
port (
EFBInst_0: EFB
generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE",
- UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 751,
- UFM_INIT_PAGES=> 16, DEV_DENSITY=> "4000L", EFB_UFM=> "ENABLED",
+ UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 0,
+ UFM_INIT_PAGES=> 767, DEV_DENSITY=> "4000L", EFB_UFM=> "ENABLED",
TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF",
TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF",
TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767,
I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED",
I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz",
I2C1_SLAVE_ADDR=> "0b0011001", I2C1_ADDRESSING=> "7BIT",
- EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "133.0")
+ EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.3")
port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i,
WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7),
WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5),
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="flashram" module="RAM_DP_TRUE" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 08 09 14:41:35.856" version="7.1" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="" type="mem" modified="2012 08 09 14:41:35.000"/>
+ <File name="flashram.lpc" type="lpc" modified="2012 08 09 14:41:31.000"/>
+ <File name="flashram.vhd" type="top_level_vhdl" modified="2012 08 09 14:41:31.000"/>
+ <File name="flashram_tmpl.vhd" type="template_vhdl" modified="2012 08 09 14:41:31.000"/>
+ <File name="tb_flashram_tmpl.vhd" type="testbench_vhdl" modified="2012 08 09 14:41:32.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=machxo2
+PartType=LCMXO2-4000HC
+PartName=LCMXO2-4000HC-6FTG256C
+SpeedGrade=6
+Package=FTBGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP_TRUE
+CoreRevision=7.1
+ModuleName=flashram
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/09/2012
+Time=14:41:31
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=16
+RData=8
+WAddress=16
+WData=8
+ROutputEn=0
+RClockEn=0
+WOutputEn=0
+WClockEn=0
+enByte=0
+ByteSize=9
+Optimization=Area
+Reset=Sync
+Reset1=Sync
+Init=0
+MemFile=
+MemFormat=bin
+EnECC=0
+Pipeline=0
+WriteA=Normal
+WriteB=Normal
+init_data=0
+
+[FilesGenerated]
+=mem
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87)
+-- Module Version: 7.1
+--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 11 -rp 1010 -data_width 8 -rdata_width 8 -num_rows 16 -cascade 11 -mem_init0 -writemodeA NORMAL -writemodeB NORMAL -e
+
+-- Thu Aug 9 14:41:31 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO2;
+use MACHXO2.components.all;
+-- synopsys translate_on
+
+entity flashram is
+ port (
+ DataInA: in std_logic_vector(7 downto 0);
+ DataInB: in std_logic_vector(7 downto 0);
+ AddressA: in std_logic_vector(3 downto 0);
+ AddressB: in std_logic_vector(3 downto 0);
+ ClockA: in std_logic;
+ ClockB: in std_logic;
+ ClockEnA: in std_logic;
+ ClockEnB: in std_logic;
+ WrA: in std_logic;
+ WrB: in std_logic;
+ ResetA: in std_logic;
+ ResetB: in std_logic;
+ QA: out std_logic_vector(7 downto 0);
+ QB: out std_logic_vector(7 downto 0));
+end flashram;
+
+architecture Structure of flashram is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP8KC
+ generic (INIT_DATA : in String; INITVAL_1F : in String;
+ INITVAL_1E : in String; INITVAL_1D : in String;
+ INITVAL_1C : in String; INITVAL_1B : in String;
+ INITVAL_1A : in String; INITVAL_19 : in String;
+ INITVAL_18 : in String; INITVAL_17 : in String;
+ INITVAL_16 : in String; INITVAL_15 : in String;
+ INITVAL_14 : in String; INITVAL_13 : in String;
+ INITVAL_12 : in String; INITVAL_11 : in String;
+ INITVAL_10 : in String; INITVAL_0F : in String;
+ INITVAL_0E : in String; INITVAL_0D : in String;
+ INITVAL_0C : in String; INITVAL_0B : in String;
+ INITVAL_0A : in String; INITVAL_09 : in String;
+ INITVAL_08 : in String; INITVAL_07 : in String;
+ INITVAL_06 : in String; INITVAL_05 : in String;
+ INITVAL_04 : in String; INITVAL_03 : in String;
+ INITVAL_02 : in String; INITVAL_01 : in String;
+ INITVAL_00 : in String; ASYNC_RESET_RELEASE : in String;
+ RESETMODE : in String; GSR : in String;
+ WRITEMODE_B : in String; WRITEMODE_A : in String;
+ CSDECODE_B : in String; CSDECODE_A : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ port (DIA8: in std_logic; DIA7: in std_logic;
+ DIA6: in std_logic; DIA5: in std_logic;
+ DIA4: in std_logic; DIA3: in std_logic;
+ DIA2: in std_logic; DIA1: in std_logic;
+ DIA0: in std_logic; ADA12: in std_logic;
+ ADA11: in std_logic; ADA10: in std_logic;
+ ADA9: in std_logic; ADA8: in std_logic;
+ ADA7: in std_logic; ADA6: in std_logic;
+ ADA5: in std_logic; ADA4: in std_logic;
+ ADA3: in std_logic; ADA2: in std_logic;
+ ADA1: in std_logic; ADA0: in std_logic; CEA: in std_logic;
+ OCEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA2: in std_logic; CSA1: in std_logic;
+ CSA0: in std_logic; RSTA: in std_logic;
+ DIB8: in std_logic; DIB7: in std_logic;
+ DIB6: in std_logic; DIB5: in std_logic;
+ DIB4: in std_logic; DIB3: in std_logic;
+ DIB2: in std_logic; DIB1: in std_logic;
+ DIB0: in std_logic; ADB12: in std_logic;
+ ADB11: in std_logic; ADB10: in std_logic;
+ ADB9: in std_logic; ADB8: in std_logic;
+ ADB7: in std_logic; ADB6: in std_logic;
+ ADB5: in std_logic; ADB4: in std_logic;
+ ADB3: in std_logic; ADB2: in std_logic;
+ ADB1: in std_logic; ADB0: in std_logic; CEB: in std_logic;
+ OCEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB2: in std_logic; CSB1: in std_logic;
+ CSB0: in std_logic; RSTB: in std_logic;
+ DOA8: out std_logic; DOA7: out std_logic;
+ DOA6: out std_logic; DOA5: out std_logic;
+ DOA4: out std_logic; DOA3: out std_logic;
+ DOA2: out std_logic; DOA1: out std_logic;
+ DOA0: out std_logic; DOB8: out std_logic;
+ DOB7: out std_logic; DOB6: out std_logic;
+ DOB5: out std_logic; DOB4: out std_logic;
+ DOB3: out std_logic; DOB2: out std_logic;
+ DOB1: out std_logic; DOB0: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute MEM_LPC_FILE of flashram_0_0_0_0 : label is "flashram.lpc";
+ attribute MEM_INIT_FILE of flashram_0_0_0_0 : label is "INIT_ALL_0s";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ flashram_0_0_0_0: DP8KC
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA8=>scuba_vlo, DIA7=>DataInA(7), DIA6=>DataInA(6),
+ DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3),
+ DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0),
+ ADA12=>scuba_vlo, ADA11=>scuba_vlo, ADA10=>scuba_vlo,
+ ADA9=>scuba_vlo, ADA8=>scuba_vlo, ADA7=>scuba_vlo,
+ ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1),
+ ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo,
+ ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA,
+ WEA=>WrA, CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo,
+ RSTA=>ResetA, DIB8=>scuba_vlo, DIB7=>DataInB(7),
+ DIB6=>DataInB(6), DIB5=>DataInB(5), DIB4=>DataInB(4),
+ DIB3=>DataInB(3), DIB2=>DataInB(2), DIB1=>DataInB(1),
+ DIB0=>DataInB(0), ADB12=>scuba_vlo, ADB11=>scuba_vlo,
+ ADB10=>scuba_vlo, ADB9=>scuba_vlo, ADB8=>scuba_vlo,
+ ADB7=>scuba_vlo, ADB6=>AddressB(3), ADB5=>AddressB(2),
+ ADB4=>AddressB(1), ADB3=>AddressB(0), ADB2=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB0=>scuba_vhi, CEB=>ClockEnB,
+ OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB2=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB0=>scuba_vlo, RSTB=>ResetB, DOA8=>open,
+ DOA7=>QA(7), DOA6=>QA(6), DOA5=>QA(5), DOA4=>QA(4),
+ DOA3=>QA(3), DOA2=>QA(2), DOA1=>QA(1), DOA0=>QA(0),
+ DOB8=>open, DOB7=>QB(7), DOB6=>QB(6), DOB5=>QB(5),
+ DOB4=>QB(4), DOB3=>QB(3), DOB2=>QB(2), DOB1=>QB(1),
+ DOB0=>QB(0));
+
+end Structure;
+
+-- synopsys translate_off
+library MACHXO2;
+configuration Structure_CON of flashram is
+ for Structure
+ for all:VHI use entity MACHXO2.VHI(V); end for;
+ for all:VLO use entity MACHXO2.VLO(V); end for;
+ for all:DP8KC use entity MACHXO2.DP8KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 08 09 14:45:06.293" version="5.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll.lpc" type="lpc" modified="2012 08 09 14:45:01.000"/>
+ <File name="pll.vhd" type="top_level_vhdl" modified="2012 08 09 14:45:01.000"/>
+ <File name="pll_tmpl.vhd" type="template_vhdl" modified="2012 08 09 14:45:01.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=machxo2
+PartType=LCMXO2-4000HC
+PartName=LCMXO2-4000HC-6FTG256C
+SpeedGrade=6
+Package=FTBGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.2
+ModuleName=pll
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/09/2012
+Time=14:45:01
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+mode=Frequency
+CLKI=133
+CLKI_DIV=1
+fb_mode=INT_OP
+CLKFB_DIV=1
+FRACN_ENABLE=0
+FRACN_DIV=0
+DynamicPhase=STATIC
+ClkEnable=0
+Standby=0
+PLLRst=0
+PLLMRst=0
+ClkOS2Rst=0
+ClkOS3Rst=0
+LockSig=1
+LockStk=0
+WBProt=0
+OPBypass=1
+OPUseDiv=1
+CLKOP_DIV=4
+FREQ_PIN_CLKOP=33.33
+OP_Tol=5.0
+CLKOP_AFREQ=33.250000
+CLKOP_PHASEADJ=0
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+EnCLKOS=1
+OSBypass=1
+OSUseDiv=0
+CLKOS_DIV=1
+FREQ_PIN_CLKOS=100
+OS_Tol=0.0
+CLKOS_AFREQ=133.000000
+CLKOS_PHASEADJ=0
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+EnCLKOS2=0
+OS2Bypass=0
+OS2UseDiv=0
+CLKOS2_DIV=1
+FREQ_PIN_CLKOS2=100
+OS2_Tol=0.0
+CLKOS2_AFREQ=
+CLKOS2_PHASEADJ=0
+EnCLKOS3=0
+OS3Bypass=0
+OS3UseDiv=0
+CLKOS3_DIV=1
+FREQ_PIN_CLKOS3=100
+OS3_Tol=0.0
+CLKOS3_AFREQ=
+CLKOS3_PHASEADJ=0
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87)
+-- Module Version: 5.2
+--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n pll -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 133 -bypassp -bypass_divp -fclkop 33.25 -bypasss -phase_cntl STATIC -fb_mode 5 -lock -e
+
+-- Thu Aug 9 14:45:01 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO2;
+use MACHXO2.components.all;
+-- synopsys translate_on
+
+entity pll is
+ port (
+ CLKI: in std_logic;
+ CLKOP: out std_logic;
+ CLKOS: out std_logic;
+ LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll : entity is true;
+end pll;
+
+architecture Structure of pll is
+
+ -- internal signal declarations
+ signal CLKOS_t: std_logic;
+ signal CLKOP_t: std_logic;
+ signal CLKFB_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EHXPLLJ
+ generic (INTFB_WAKE : in String; DDRST_ENA : in String;
+ DCRST_ENA : in String; MRST_ENA : in String;
+ PLLRST_ENA : in String; DPHASE_SOURCE : in String;
+ OUTDIVIDER_MUXD2 : in String;
+ OUTDIVIDER_MUXC2 : in String;
+ OUTDIVIDER_MUXB2 : in String;
+ OUTDIVIDER_MUXA2 : in String;
+ PREDIVIDER_MUXD1 : in Integer;
+ PREDIVIDER_MUXC1 : in Integer;
+ PREDIVIDER_MUXB1 : in Integer;
+ PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
+ PLL_LOCK_MODE : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
+ FRACN_ENABLE : in String; FEEDBK_PATH : in String;
+ CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
+ CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
+ CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
+ CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
+ VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
+ VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
+ CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
+ CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
+ CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
+ CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
+ CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ PHASESEL1: in std_logic; PHASESEL0: in std_logic;
+ PHASEDIR: in std_logic; PHASESTEP: in std_logic;
+ LOADREG: in std_logic; STDBY: in std_logic;
+ PLLWAKESYNC: in std_logic; RST: in std_logic;
+ RESETM: in std_logic; RESETC: in std_logic;
+ RESETD: in std_logic; ENCLKOP: in std_logic;
+ ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
+ ENCLKOS3: in std_logic; PLLCLK: in std_logic;
+ PLLRST: in std_logic; PLLSTB: in std_logic;
+ PLLWE: in std_logic; PLLADDR4: in std_logic;
+ PLLADDR3: in std_logic; PLLADDR2: in std_logic;
+ PLLADDR1: in std_logic; PLLADDR0: in std_logic;
+ PLLDATI7: in std_logic; PLLDATI6: in std_logic;
+ PLLDATI5: in std_logic; PLLDATI4: in std_logic;
+ PLLDATI3: in std_logic; PLLDATI2: in std_logic;
+ PLLDATI1: in std_logic; PLLDATI0: in std_logic;
+ CLKOP: out std_logic; CLKOS: out std_logic;
+ CLKOS2: out std_logic; CLKOS3: out std_logic;
+ LOCK: out std_logic; INTLOCK: out std_logic;
+ REFCLK: out std_logic; CLKINTFB: out std_logic;
+ DPHSRC: out std_logic; PLLACK: out std_logic;
+ PLLDATO7: out std_logic; PLLDATO6: out std_logic;
+ PLLDATO5: out std_logic; PLLDATO4: out std_logic;
+ PLLDATO3: out std_logic; PLLDATO2: out std_logic;
+ PLLDATO1: out std_logic; PLLDATO0: out std_logic);
+ end component;
+ attribute STDBY_ENABLE : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute ICP_CURRENT : string;
+ attribute LPF_RESISTOR : string;
+ attribute STDBY_ENABLE of PLLInst_0 : label is "DISABLED";
+ attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "133.000000";
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "33.250000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "133.000000";
+ attribute ICP_CURRENT of PLLInst_0 : label is "0";
+ attribute LPF_RESISTOR of PLLInst_0 : label is "0";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLJ
+ generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
+ MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
+ DPHASE_SOURCE=> "DISABLED", PLL_USE_WB=> "DISABLED",
+ CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0,
+ CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0,
+ CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", FRACN_DIV=> 0,
+ FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
+ PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
+ OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
+ CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "REFCLK",
+ PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "ENABLED",
+ OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "ENABLED",
+ CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 1,
+ CLKOS_DIV=> 1, CLKOP_DIV=> 4, CLKFB_DIV=> 1, CLKI_DIV=> 1,
+ FEEDBK_PATH=> "INT_DIVA")
+ port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo,
+ PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
+ PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
+ PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo,
+ RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
+ ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
+ PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
+ PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
+ PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
+ PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
+ PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
+ PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
+ PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
+ PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
+ CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
+ REFCLK=>open, CLKINTFB=>CLKFB_t, DPHSRC=>open, PLLACK=>open,
+ PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
+ PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
+ PLLDATO1=>open, PLLDATO0=>open);
+
+ CLKOS <= CLKOS_t;
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library MACHXO2;
+configuration Structure_CON of pll is
+ for Structure
+ for all:VLO use entity MACHXO2.VLO(V); end for;
+ for all:EHXPLLJ use entity MACHXO2.EHXPLLJ(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
#-- Synopsys, Inc.
#-- Version F-2012.03-SP1
-#-- Project file /local/trb/cvs/trb3/wasa/panda_dirc_wasa/panda_dirc_wasa_syn.prj
+#-- Project file /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa/panda_dirc_wasa_syn.prj
#-- Written on Mon Aug 6 18:53:10 2012
#project files
add_file -vhdl -lib work "/d/jspc29/lattice/diamond/1.4.2.105/cae_library/synthesis/vhdl/machxo2.vhd"
-add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd"
-add_file -vhdl -lib work "/local/trb/cvs/trb3/base/trb3_components.vhd"
-add_file -vhdl -lib work "/local/trb/cvs/trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "/local/trb/cvs/trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/source/spi_slave.vhd"
-add_file -vhdl -lib work "/local/trb/cvs/trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/version.vhd"
-add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/cores/oddr16.vhd"
-add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/source/pwm.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/version.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/source/pwm.vhd"
+
+
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/flashram.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/pll.vhd"
+add_file -verilog -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/UFM_WB.v"
+add_file -verilog -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/efb_define_def.v"
+
+
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd"
#implementation: "panda_dirc_wasa"
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
-
+set_option -top_module "panda_dirc_wasa"
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
);\r
end component;\r
\r
+component flashram\r
+ port (\r
+ DataInA: in std_logic_vector(7 downto 0); \r
+ DataInB: in std_logic_vector(7 downto 0); \r
+ AddressA: in std_logic_vector(3 downto 0); \r
+ AddressB: in std_logic_vector(3 downto 0); \r
+ ClockA: in std_logic; \r
+ ClockB: in std_logic; \r
+ ClockEnA: in std_logic; \r
+ ClockEnB: in std_logic; \r
+ WrA: in std_logic; \r
+ WrB: in std_logic; \r
+ ResetA: in std_logic; \r
+ ResetB: in std_logic; \r
+ QA: out std_logic_vector(7 downto 0); \r
+ QB: out std_logic_vector(7 downto 0)\r
+ );\r
+end component;\r
+\r
+component pll\r
+ port (\r
+ CLKI: in std_logic; \r
+ CLKOP: out std_logic; \r
+ CLKOS: out std_logic; \r
+ LOCK: out std_logic);\r
+end component;\r
+\r
+\r
+component UFM_WB\r
+ port(\r
+ clk_i : in std_logic;\r
+ rst_n : in std_logic;\r
+ cmd : in std_logic_vector(2 downto 0);\r
+ ufm_page : in std_logic_vector(10 downto 0);\r
+ GO : in std_logic;\r
+ BUSY : out std_logic;\r
+ ERR : out std_logic;\r
+ mem_clk : out std_logic;\r
+ mem_we : out std_logic;\r
+ mem_ce : out std_logic;\r
+ mem_addr : out std_logic_vector(3 downto 0);\r
+ mem_wr_data : out std_logic_vector(7 downto 0);\r
+ mem_rd_data : in std_logic_vector(7 downto 0)\r
+ );\r
+end component;\r
+\r
+\r
attribute NOM_FREQ : string;\r
attribute NOM_FREQ of clk_source : label is "133.00";\r
signal clk_i : std_logic;\r
signal id_addr_i : std_logic_vector(2 downto 0);\r
signal id_write_i: std_logic;\r
signal ram_write_i : std_logic;\r
-signal ram_data_i: std_logic_vector(15 downto 0);\r
-signal ram_data_o: std_logic_vector(15 downto 0);\r
-signal ram_addr_i: integer range 0 to 15;\r
+signal ram_data_i: std_logic_vector(7 downto 0);\r
+signal ram_data_o: std_logic_vector(7 downto 0);\r
+signal ram_addr_i: std_logic_vector(3 downto 0);\r
signal temperature_i : std_logic_vector(11 downto 0);\r
\r
type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);\r
signal spi_channel_i : std_logic_vector(7 downto 0);\r
signal spi_write_i : std_logic_vector(15 downto 0);\r
\r
+signal pll_lock : std_logic;\r
+signal clk_33 : std_logic;\r
+signal clk_osc : std_logic;\r
+\r
+signal flashram_addr_i : std_logic_vector(3 downto 0);\r
+signal flashram_cen_i : std_logic;\r
+signal flashram_reset : std_logic;\r
+signal flashram_write_i: std_logic;\r
+signal flashram_data_i : std_logic_vector(7 downto 0);\r
+signal flashram_data_o : std_logic_vector(7 downto 0);\r
+\r
+signal flash_command : std_logic_vector(2 downto 0);\r
+signal flash_page : std_logic_vector(10 downto 0);\r
+signal flash_go : std_logic;\r
+signal flash_busy : std_logic;\r
+signal flash_err : std_logic;\r
+\r
begin\r
\r
PROC_RESET : process begin\r
wait until rising_edge(clk_i);\r
- reset_i <= '0';\r
+ reset_i <= not pll_lock;\r
if reset_cnt /= x"F" then\r
reset_cnt <= reset_cnt + 1;\r
reset_i <= '1';\r
end if;\r
end process;\r
\r
+\r
+\r
+THE_PLL : pll\r
+ port map(\r
+ CLKI => clk_osc,\r
+ CLKOP => clk_33, --33\r
+ CLKOS => clk_i, --133\r
+ LOCK => pll_lock\r
+ );\r
+\r
---------------------------------------------------------------------------\r
-- Clock\r
---------------------------------------------------------------------------\r
-- synthesis translate_on\r
port map (\r
STDBY => '0',\r
- OSC => clk_i,\r
+ OSC => clk_osc,\r
SEDSTDBY => open\r
);\r
\r
DEBUG_OUT => open\r
);\r
\r
+ \r
+---------------------------------------------------------------------------\r
+-- RAM Interface\r
+--------------------------------------------------------------------------- \r
+\r
ram_write_i <= spi_write_i(4); --or signal from Flash entity\r
-ram_data_i <= spi_data_i; --or signal from Flash entity\r
-ram_addr_i <= to_integer(unsigned(spi_channel_i(3 downto 0))); --or signal from Flash entity\r
+ram_data_i <= spi_data_i(7 downto 0); --or signal from Flash entity\r
+ram_addr_i <= spi_channel_i(3 downto 0); --or signal from Flash entity\r
+\r
+spi_reg40_i <= x"00" & ram_data_o;\r
+\r
+\r
+THE_FLASH_RAM : flashram\r
+ port map(\r
+ DataInA => ram_data_i,\r
+ DataInB => flashram_data_i,\r
+ AddressA => ram_addr_i,\r
+ AddressB => flashram_addr_i,\r
+ ClockA => clk_i, \r
+ ClockB => clk_33,\r
+ ClockEnA => '1',\r
+ ClockEnB => flashram_cen_i,\r
+ WrA => ram_write_i, \r
+ WrB => flashram_write_i, \r
+ ResetA => '0',\r
+ ResetB => flashram_reset,\r
+ QA => ram_data_o,\r
+ QB => flashram_data_o\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Flash Controller\r
+--------------------------------------------------------------------------- \r
+\r
+THE_FLASH : UFM_WB\r
+ port map(\r
+ clk_i => clk_33,\r
+ rst_n => '1',\r
+ cmd => flash_command,\r
+ ufm_page => flash_page,\r
+ GO => flash_go,\r
+ BUSY => flash_busy,\r
+ ERR => flash_err,\r
+ mem_clk => open,\r
+ mem_we => flashram_write_i,\r
+ mem_ce => flashram_cen_i,\r
+ mem_addr => flashram_addr_i,\r
+ mem_wr_data => flashram_data_i,\r
+ mem_rd_data => flashram_data_o\r
+ );\r
\r
-PROC_RAM : process begin\r
- wait until rising_edge(clk_i);\r
- if ram_write_i = '1' then\r
- ram(ram_addr_i) <= ram_data_i;\r
- end if;\r
- ram_data_o <= ram(ram_addr_i);\r
- spi_reg40_i <= ram(to_integer(unsigned(spi_channel_i(3 downto 0))));\r
-end process;\r
\r
---------------------------------------------------------------------------\r
-- PWM\r
--------------------------------------------------------------------------- \r
\r
THE_ONEWIRE : trb_net_onewire\r
+ generic map(\r
+ CLK_PERIOD => 30\r
+ )\r
port map(\r
- CLK => clk_i,\r
+ CLK => clk_33,\r
RESET => reset_i,\r
READOUT_ENABLE_IN => '1',\r
ONEWIRE => TEMP_LINE,\r
\r
SPARE_LINE <= (others => '0');\r
\r
-TEST_LINE(0) <= clk_i;\r
+TEST_LINE(0) <= '0';\r
TEST_LINE(15 downto 1) <= (others => '0');\r
\r
LED_GREEN <= '0';\r
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
;mvc_lib = $MODEL_TECH/../mvc_lib
-work = work
machxo2 = /d/jspc29/lattice/diamond/1.4.2.105/ispfpga/vhdl/data/machxo2/mti/machxo2
+work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
UserTimeUnit = default
; Default run length
-RunLength = 30 us
+RunLength = 10 us
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 13
-Project_File_0 = /d/jspc22/trb/cvs/trbnet/trb_net_components.vhd
-Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1343057812 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_1 = /d/jspc22/trb/cvs/trb3/wasa/source/pwm.vhd
-Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344343677 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_2 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/full_tb.vhd
-Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350435 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_3 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd
-Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350118 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd
-Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1342609010 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_5 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd
-Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344271888 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_6 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd
-Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344343599 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_7 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd
-Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1308757058 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_8 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd
-Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344272681 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_9 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd
-Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_10 = /d/jspc22/trb/cvs/trbnet/special/spi_ltc2600.vhd
-Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1339672931 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_11 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd
-Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1343999155 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_12 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd
-Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_Files_Count = 17
+Project_File_0 = /d/jspc22/trb/cvs/trb3/wasa/cores/efb_define_def.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1344528395 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = /d/jspc22/trb/cvs/trbnet/trb_net_components.vhd
+Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1343057812 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_2 = /d/jspc22/trb/cvs/trb3/wasa/source/pwm.vhd
+Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344352102 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_3 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/full_tb.vhd
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350435 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd
+Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350118 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_5 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344531529 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_6 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd
+Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344271888 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_7 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344852112 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_8 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1308757058 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_9 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344272681 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_10 = /d/jspc22/trb/cvs/trb3/wasa/cores/UFM_WB.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1344852401 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+/d/jspc22/trb/cvs/trb3/wasa/cores\7f compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_11 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd
+Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_12 = /d/jspc22/trb/cvs/trbnet/special/spi_ltc2600.vhd
+Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344353596 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_13 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd
+Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344852431 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_14 = /d/jspc22/trb/cvs/trb3/wasa/cores/flashram.vhd
+Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344516091 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_15 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd
+Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_16 = /d/jspc22/trb/cvs/trb3/wasa/cores/pll.vhd
+Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344516301 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
PROC_MEM : process begin
wait until rising_edge(CLK);
if WRITE_IN = '1' then
- set(to_integer(unsigned(ADDR_IN)))(16) <= '0';
+-- set(to_integer(unsigned(ADDR_IN)))(16) <= '0';
set(to_integer(unsigned(ADDR_IN)))(15 downto 0) <= unsigned(DATA_IN);
end if;
DATA_OUT <= std_logic_vector(set(to_integer(unsigned(ADDR_IN)))(15 downto 0));
jspc29 / trb3.git / commitdiff