--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity handler_data is
+ generic(
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8
+ );
+ port(
+ CLOCK : in std_logic;
+ RESET : in std_logic;
+
+ --From LVL1 Handler
+ LVL1_TRG_RECEIVED_OUT : in std_logic; --TRG Info valid & FEE busy
+ LVL1_TRG_TYPE_OUT : in std_logic_vector(3 downto 0); --trigger type
+ LVL1_TRG_INFO_OUT : in std_logic_vector(23 downto 0); --further trigger details
+ LVL1_TRG_NUMBER_OUT : in std_logic_vector(15 downto 0); --trigger number
+ LVL1_BUFFER_WARN_OUT : out std_logic; --some fifos might be full soon
+ LVL1_BUFFER_FULL_OUT : out std_logic; --some fifos are full
+ LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
+
+ --From FEE
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ FEE_DATA_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+
+ --To IPU Handler
+ IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+ IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0);
+ IPU_HDR_DATA_READ_IN : in std_logic;
+ IPU_HDR_DATA_EMPTY_OUT : out std_logic;
+
+ --Debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0);
+
+end entity;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity handler_ipu is
+ generic(
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1
+ );
+ port(
+ CLOCK : in std_logic;
+ RESET : in std_logic;
+
+ --From Data Handler
+ DAT_DATA : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+ DAT_DATA_READ : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ DAT_DATA_EMPTY : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ DAT_HDR_DATA : in std_logic_vector(31 downto 0);
+ DAT_HDR_DATA_READ : out std_logic;
+ DAT_HDR_DATA_EMPTY : in std_logic;
+
+
+ --To IPU Channel
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);
+ IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
+ IPU_START_READOUT_IN : in std_logic;
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);
+ IPU_DATAREADY_OUT : out std_logic;
+ IPU_READOUT_FINISHED_OUT : out std_logic;
+ IPU_READ_IN : in std_logic;
+ IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
+
+
+ --Debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0);
+
+end entity;
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+
+entity lvl1_handler is
+ port (
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ --Timing Trigger
+ LVL1_TIMING_TRG_IN : in std_logic;
+ --LVL1_handler connection
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_IN : in std_logic;
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ LVL1_TRG_RELEASE_OUT : out std_logic := '0';
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+
+ --FEE logic / Data Handler
+ FEE_TIMING_TRIGGER_OUT : out std_logic; --timing trigger (registered)
+ FEE_TRG_RECEIVED_OUT : out std_logic; --TRG Info valid & FEE busy
+ FEE_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); --trigger type
+ FEE_TRG_INFO_OUT : out std_logic_vector(23 downto 0); --further trigger details
+ FEE_TRG_CODE_OUT : out std_logic_vector(7 downto 0); --further trigger details
+ FEE_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --trigger number
+ FEE_BUSY_IN : in std_logic; --FEE busy
+ FEE_BUFFER_WARN_IN : in std_logic; --some fifos (if any) might be full soon
+ FEE_TRG_STATUSBITS_IN : in std_logic_vector(31 downto 0);
+
+ DAT_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ DAT_DATA_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+
+ --Debug
+ DEBUG_OUT : out std_logic_vector (15 downto 0)
+ );
+end entity;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity handler_trigger_and_data is
+ generic(
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8
+
+ );
+ port(
+ CLOCK : in std_logic;
+ RESET : in std_logic;
+
+ --To Endpoint
+ --Timing Trigger (registered)
+ LVL1_TIMING_TRG_IN : in std_logic;
+ --LVL1_handler connection
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_IN : in std_logic;
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ LVL1_TRG_RELEASE_OUT : out std_logic;
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+
+ --IPU channel
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0);
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
+ IPU_START_READOUT_IN : in std_logic;
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0);
+ IPU_DATAREADY_OUT : out std_logic;
+ IPU_READOUT_FINISHED_OUT : out std_logic;
+ IPU_READ_IN : in std_logic;
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0);
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+
+ --To FEE
+ --Trigger to FEE
+ FEE_TIMING_TRIGGER_OUT : out std_logic; --timing trigger (registered)
+ FEE_TRG_RECEIVED_OUT : out std_logic; --TRG Info valid & FEE busy
+ FEE_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); --trigger type
+ FEE_TRG_INFO_OUT : out std_logic_vector(23 downto 0); --further trigger details
+ FEE_TRG_CODE_OUT : out std_logic_vector(7 downto 0); --further trigger details
+ FEE_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --trigger number
+ FEE_BUSY_IN : in std_logic; --FEE busy
+ FEE_BUFFER_WARN_IN : in std_logic; --some fifos (if any) might be full soon
+ FEE_TRG_STATUSBITS_IN : in std_logic_vector(31 downto 0);
+
+ --Data Input from FEE
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ FEE_DATA_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+
+ --Debug
+ DEBUG_LVL1_HANDLER_OUT : out std_logic_vector(31 downto 0);
+ DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0);
+ DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0)
+
+ );
+end entity;
+
+--Data inputs are read from 0 to MAX - 0 will always come first, MAX is always last.
+--To add debug information in front or behind the data, simply configure one more data port than needed for data
+
+
+architecture handler_trigger_and_data_arch of handler_trigger_and_data is
+
+begin
+
+
+
+
+end architecture;
\ No newline at end of file