END testbench;\r
\r
ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT trb_net16_gbe_buf\r
- GENERIC( DO_SIMULATION : integer range 0 to 1 := 1 );\r
- PORT(\r
- CLK : IN std_logic;\r
- TEST_CLK : IN std_logic;\r
+ component buf_tester is --trb_net16_gbe_buf is\r
+ generic( \r
+ DO_SIMULATION : integer range 0 to 1 := 1;\r
+ USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ TEST_CLK : in std_logic; -- only for simulation!\r
+ CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
+ CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
RESET : IN std_logic;\r
GSR_N : IN std_logic;\r
STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0);\r
SLV_ACK_OUT : out std_logic;\r
SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- gk 26.04.10\r
+ -- registers setup interface\r
+ BUS_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10\r
+ BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10\r
+ BUS_READ_EN_IN : in std_logic; -- gk 26.04.10\r
+ BUS_ACK_OUT : out std_logic; -- gk 26.04.10\r
+ -- gk 23.04.10\r
+ LED_PACKET_SENT_OUT : out std_logic;\r
+ LED_AN_DONE_N_OUT : out std_logic;\r
------------------------\r
CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
CTS_CODE_IN : IN std_logic_vector(7 downto 0);\r
BEGIN\r
\r
-- Please check and add your generic clause manually\r
- uut: trb_net16_gbe_buf \r
- GENERIC MAP( DO_SIMULATION => 1 )\r
+ uut: buf_tester --trb_net16_gbe_buf \r
+ GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 )\r
PORT MAP(\r
CLK => CLK,\r
+ CLK_125_TX_IN => '0',\r
+ CLK_125_RX_IN => '0',\r
TEST_CLK => TEST_CLK,\r
RESET => RESET,\r
GSR_N => GSR_N,\r
SLV_ACK_OUT => SLV_ACK_OUT,\r
SLV_DATA_IN => SLV_DATA_IN,\r
SLV_DATA_OUT => SLV_DATA_OUT,\r
+ -- gk 22.04.10\r
+ -- registers setup interface\r
+ BUS_ADDR_IN => x"00",\r
+ BUS_DATA_IN => x"0000_0000",\r
+ BUS_DATA_OUT => open,\r
+ BUS_WRITE_EN_IN => '0',\r
+ BUS_READ_EN_IN => '0',\r
+ BUS_ACK_OUT => open,\r
+ -- gk 23.04.10\r
+ LED_PACKET_SENT_OUT => open,\r
+ LED_AN_DONE_N_OUT => open,\r
+ --------------------------\r
CTS_NUMBER_IN => CTS_NUMBER_IN,\r
CTS_CODE_IN => CTS_CODE_IN,\r
CTS_INFORMATION_IN => CTS_INFORMATION_IN,\r
\r
variable stim : std_logic_vector(15 downto 0);\r
\r
+\r
-- RND test\r
--UNIFORM(seed1, seed2, rand);\r
--int_rand := INTEGER(TRUNC(rand*65536.0));\r
\r
wait for 500 ns;\r
\r
+\r
-------------------------------------------------------------------------------\r
-- Loop the transmissions\r
-------------------------------------------------------------------------------\r
UNIFORM(seed1, seed2, rand);\r
test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;\r
\r
- --test_data_len := 9685;\r
- test_data_len := 200;\r
+ test_data_len := 9685;\r
+ --test_data_len := 400;\r
\r
-- calculate the needed variables\r
test_loop_len := 2*(test_data_len - 1) + 1;\r
else\r
fee_dataready_in <= '1';\r
end if;\r
+ --fee_dataready_in <= '1';\r
end loop MY_DATA_LOOP;\r
-- there must be padding words to get multiple of four LWs\r
\r
DBG_SF_AEMPTY_OUT : out std_logic;
DBG_SF_FULL_OUT : out std_logic;
DBG_SF_AFULL_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(31 downto 0)
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
);
end component;
PROTOCOL_IN : in std_logic_vector(7 downto 0);
-- ports for packetTransmitter
RD_CLK : in std_logic;
- FT_DATA_OUT : out std_logic_vector(8 downto 0);
+ FT_DATA_OUT : out std_logic_vector(8 downto 0);-- gk 04.05.10
+ --FT_EOD_OUT : out std_logic;-- gk 04.05.10
FT_TX_EMPTY_OUT : out std_logic;
FT_TX_RD_EN_IN : in std_logic;
FT_START_OF_PACKET_OUT : out std_logic;
GBE_USE_MULTIEVENTS_OUT : out std_logic;
GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10
GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10
- GBE_DELAY_OUT : out std_logic_vector(31 downto 0) -- gk 28.04.10
+ GBE_DELAY_OUT : out std_logic_vector(31 downto 0)
);
end component;
signal fc_bsm_constr : std_logic_vector(7 downto 0);
signal fc_bsm_trans : std_logic_vector(3 downto 0);
-signal ft_data : std_logic_vector(8 downto 0);
+signal ft_data : std_logic_vector(8 downto 0);-- gk 04.05.10
signal ft_tx_empty : std_logic;
signal ft_start_of_packet : std_logic;
signal ft_bsm_init : std_logic_vector(3 downto 0);
signal gbe_trig_nr : std_logic_vector(31 downto 0);
-- gk 28.04.10
signal pc_delay : std_logic_vector(31 downto 0);
+-- gk 04.05.10
+signal ft_eod : std_logic;
begin
--pc_decoding <= x"00020001"; -- !!!! swap it!!!! -- gk 22.04.10
--pc_event_id <= x"000000ca"; -- !!!! swap it!!!! -- gk 22.04.10
--pc_queue_dec <= x"00030062"; -- !!!! swap it!!!! -- gk 22.04.10
+
-- FrameConstructor fixed magic values
fc_type <= x"0008";
fc_ihl_version <= x"45";
GBE_USE_MULTIEVENTS_OUT => use_multievents,
GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10
GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10
- GBE_DELAY_OUT => pc_delay -- gk 28.04.10
+ GBE_DELAY_OUT => pc_delay
);
-- IP configurator: allows IP config to change for each event builder
-- ports for packetTransmitter
RD_CLK => serdes_clk_125,
FT_DATA_OUT => ft_data,
+ --FT_EOD_OUT => ft_eod, -- gk 04.05.10
FT_TX_EMPTY_OUT => ft_tx_empty,
FT_TX_RD_EN_IN => mac_tx_read,
FT_START_OF_PACKET_OUT => ft_start_of_packet,
TX_MAC_CLK => serdes_clk_125,
TX_EMPTY_IN => ft_tx_empty,
START_OF_PACKET_IN => ft_start_of_packet,
- DATA_ENDFLAG_IN => ft_data(8),
+ DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10
-- MAC interface
HADDR_OUT => mac_haddr,
HDATA_OUT => mac_hdataout,
);
end generate serdes_extclk_gen;
- stage_stat_regs(31 downto 28) <= x"d";
+ stage_stat_regs(31 downto 28) <= x"e";
stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link status
stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm
stage_stat_regs(19 downto 18) <= (others => '0');
FC_BSM_TRANS_TST <= fc_bsm_trans;
-- FrameTransmitter signals
FT_TX_EMPTY_TST <= ft_tx_empty;
-FT_DATA_TST <= ft_data;
+FT_DATA_TST <= ft_data; -- gk 04.05.10
FT_START_OF_PACKET_TST <= ft_start_of_packet;
FT_BSM_INIT_TST <= ft_bsm_init;
FT_BSM_MAC_TST <= ft_bsm_mac;
use work.trb_net_components.all;\r
\r
entity trb_net16_med_ecp_sfp_gbe_8b is\r
+-- gk 28.04.10\r
+generic (\r
+ USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
+);\r
port(\r
RESET : in std_logic;\r
GSR_N : in std_logic;\r
CLK_125_OUT : out std_logic;\r
CLK_RX_OUT : out std_logic;\r
CLK_TX_OUT : out std_logic;\r
+ CLK_125_TX_IN : in std_logic; -- gk 28.04.10 used when intclk\r
+ CLK_125_RX_IN : in std_logic; -- gk 28.04.10 used when intclk\r
--SGMII connection to frame transmitter (tsmac)\r
FT_TX_CLK_EN_OUT : out std_logic;\r
FT_RX_CLK_EN_OUT : out std_logic;\r
);\r
end component;\r
\r
+component serdes_gbe_0_intclock_8b is\r
+ GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt");\r
+ port (\r
+ core_txrefclk : in std_logic;\r
+ core_rxrefclk : in std_logic;\r
+ hdinp0, hdinn0 : in std_logic;\r
+ hdoutp0, hdoutn0 : out std_logic;\r
+ ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;\r
+ ff_txdata_ch0 : in std_logic_vector (7 downto 0);\r
+ ff_rxdata_ch0 : out std_logic_vector (7 downto 0);\r
+ ff_tx_k_cntrl_ch0 : in std_logic;\r
+ ff_rx_k_cntrl_ch0 : out std_logic;\r
+ ff_rxfullclk_ch0 : out std_logic;\r
+ ff_xmit_ch0 : in std_logic;\r
+ ff_correct_disp_ch0 : in std_logic;\r
+ ff_disp_err_ch0, ff_cv_ch0 : out std_logic;\r
+ ff_rx_even_ch0 : out std_logic;\r
+ ffc_rrst_ch0 : in std_logic;\r
+ ffc_lane_tx_rst_ch0 : in std_logic;\r
+ ffc_lane_rx_rst_ch0 : in std_logic;\r
+ ffc_txpwdnb_ch0 : in std_logic;\r
+ ffc_rxpwdnb_ch0 : in std_logic;\r
+ ffs_rlos_lo_ch0 : out std_logic;\r
+ ffs_ls_sync_status_ch0 : out std_logic;\r
+ ffs_rlol_ch0 : out std_logic;\r
+ oob_out_ch0 : out std_logic;\r
+ ffc_macro_rst : in std_logic;\r
+ ffc_quad_rst : in std_logic;\r
+ ffc_trst : in std_logic;\r
+ ff_txfullclk : out std_logic;\r
+ ff_txhalfclk : out std_logic;\r
+ refck2core : out std_logic;\r
+ ffs_plol : out std_logic);\r
+\r
+end component;\r
+\r
component sgmii_gbe_pcs32\r
port( rst_n : in std_logic;\r
signal_detect : in std_logic;\r
DEBUG_OUT => reset_debug\r
);\r
\r
+-- gk 28.04.10\r
-- SerDes for GbE\r
-SERDES_GBE : serdes_gbe_0_extclock_8b \r
-port map( -- SerDes connection to outside world\r
- refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input\r
- refclkn => SD_REFCLK_N_IN,\r
- hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input\r
- hdinn0 => SD_RXD_N_IN,\r
- hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output\r
- hdoutn0 => SD_TXD_N_OUT,\r
- refck2core => refclkcore, -- reference clock from input\r
- -- RX part\r
- ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output\r
- ff_rxiclk_ch0 => sd_rx_clk,\r
- ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice\r
- ff_rxdata_ch0 => sd_rx_data, -- RX data output\r
- ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output\r
- ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output)\r
- ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error\r
- ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error\r
- -- TX part\r
- ff_txfullclk => sd_tx_clk, -- TX full clock output\r
- ff_txiclk_ch0 => sd_tx_clk, \r
- ff_txhalfclk => open,\r
- ff_txdata_ch0 => sd_tx_data, -- TX data input\r
- ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input\r
- ff_xmit_ch0 => '0', -- for autonegotiation (input)\r
- ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input)\r
- -- Resets and power down\r
- ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high)\r
- ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel\r
- ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel\r
- ffc_rrst_ch0 => '0', -- '0' for normal operation\r
- ffc_macro_rst => '0', -- '0' for normal operation\r
- ffc_trst => '0', -- '0' for normal operation\r
- ffc_txpwdnb_ch0 => '1', -- must be '1'\r
- ffc_rxpwdnb_ch0 => '1', -- must be '1'\r
- -- Status outputs\r
- ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas?\r
- ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel\r
- ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL\r
- ffs_plol => sd_link_error(2), -- loss of lock in TX PLL\r
- oob_out_ch0 => open -- not needed\r
- );\r
+clk_int : if (USE_125MHZ_EXTCLK = 0) generate \r
+ SERDES_GBE : serdes_gbe_0_intclock_8b\r
+ port map(\r
+ core_txrefclk => CLK_125_TX_IN,\r
+ core_rxrefclk => CLK_125_RX_IN,\r
+ hdinp0 => SD_RXD_P_IN,\r
+ hdinn0 => SD_RXD_N_IN,\r
+ hdoutp0 => SD_TXD_P_OUT,\r
+ hdoutn0 => SD_TXD_N_OUT,\r
+ ff_rxiclk_ch0 => sd_rx_clk,\r
+ ff_txiclk_ch0 => sd_tx_clk,\r
+ ff_ebrd_clk_0 => sd_rx_clk,\r
+ ff_txdata_ch0 => sd_tx_data,\r
+ ff_rxdata_ch0 => sd_rx_data,\r
+ ff_tx_k_cntrl_ch0 => sd_tx_kcntl,\r
+ ff_rx_k_cntrl_ch0 => sd_rx_kcntl,\r
+ ff_rxfullclk_ch0 => sd_rx_clk,\r
+ ff_xmit_ch0 => '0',\r
+ ff_correct_disp_ch0 => sd_tx_correct_disp,\r
+ ff_disp_err_ch0 => sd_rx_disp_error,\r
+ ff_cv_ch0 => sd_rx_cv_error,\r
+ ff_rx_even_ch0 => sd_rx_even,\r
+ ffc_rrst_ch0 => '0',\r
+ ffc_lane_tx_rst_ch0 => lane_rst,\r
+ ffc_lane_rx_rst_ch0 => lane_rst,\r
+ ffc_txpwdnb_ch0 => '1',\r
+ ffc_rxpwdnb_ch0 => '1',\r
+ ffs_rlos_lo_ch0 => sd_link_error(0),\r
+ ffs_ls_sync_status_ch0 => sd_link_ok,\r
+ ffs_rlol_ch0 => sd_link_error(1),\r
+ oob_out_ch0 => open,\r
+ ffc_macro_rst => '0',\r
+ ffc_quad_rst => quad_rst,\r
+ ffc_trst => '0',\r
+ ff_txfullclk => sd_tx_clk,\r
+ ff_txhalfclk => open,\r
+ refck2core => refclkcore,\r
+ ffs_plol => sd_link_error(2)\r
+ );\r
+end generate clk_int;\r
+\r
+clk_ext : if (USE_125MHZ_EXTCLK = 1) generate\r
+ SERDES_GBE : serdes_gbe_0_extclock_8b \r
+ port map( -- SerDes connection to outside world\r
+ refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input\r
+ refclkn => SD_REFCLK_N_IN,\r
+ hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input\r
+ hdinn0 => SD_RXD_N_IN,\r
+ hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output\r
+ hdoutn0 => SD_TXD_N_OUT,\r
+ refck2core => refclkcore, -- reference clock from input\r
+ -- RX part\r
+ ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output\r
+ ff_rxiclk_ch0 => sd_rx_clk,\r
+ ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice\r
+ ff_rxdata_ch0 => sd_rx_data, -- RX data output\r
+ ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output\r
+ ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output)\r
+ ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error\r
+ ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error\r
+ -- TX part\r
+ ff_txfullclk => sd_tx_clk, -- TX full clock output\r
+ ff_txiclk_ch0 => sd_tx_clk, \r
+ ff_txhalfclk => open,\r
+ ff_txdata_ch0 => sd_tx_data, -- TX data input\r
+ ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input\r
+ ff_xmit_ch0 => '0', -- for autonegotiation (input)\r
+ ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input)\r
+ -- Resets and power down\r
+ ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high)\r
+ ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel\r
+ ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel\r
+ ffc_rrst_ch0 => '0', -- '0' for normal operation\r
+ ffc_macro_rst => '0', -- '0' for normal operation\r
+ ffc_trst => '0', -- '0' for normal operation\r
+ ffc_txpwdnb_ch0 => '1', -- must be '1'\r
+ ffc_rxpwdnb_ch0 => '1', -- must be '1'\r
+ -- Status outputs\r
+ ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas?\r
+ ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel\r
+ ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL\r
+ ffs_plol => sd_link_error(2), -- loss of lock in TX PLL\r
+ oob_out_ch0 => open -- not needed\r
+ );\r
+end generate clk_ext;\r
\r
SD_RX_DATA_PROC: process( sd_rx_clk )\r
begin\r
jspc29 / trbnet.git / commitdiff