\begin{description*}
\item[Trb3 Vhdl]cvs -d lxi051.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3
\item[TrbNet Vhdl]cvs -d lxi051.gsi.de:/misc/hadesprojects/daq/cvsroot/trbnet
- \item[Trb3 Documentation]cvs -d lxi051.gsi.de:/misc/hadesprojects/daq/cvsroot/daq\_docu/trb3
- \item[Trb3 Software]cvs -d lxi051.gsi.de:/misc/hadesprojects/daq/cvsroot/trbsoft/trb3
+
+ \item[Trb3 Documentation]git clone git://jspc29.x-matter.uni-frankfurt.de/projects/daqdocu.git
+ \item[Trb3 SlowControl Software]git clone git://jspc29.x-matter.uni-frankfurt.de/projects/daqtools.git
+ \item[Trbnet Software Library]git clone git://jspc29.x-matter.uni-frankfurt.de/projects/trbnettools.git
+ \item[Data Server (Eventbuilder)]git clone git://jspc29.x-matter.uni-frankfurt.de/projects/daqdata.git
+
+
\item[Dabc Eventbuilder]http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/EventBuilderDabc
\end{description*}
--- /dev/null
+\subsection{Central Aspects}
+\begin{itemize*}
+ \item All FPGA run on a central clock, each network node recovers the clock from the optical link and uses it as the main clock source for all design components.
+ \item Low-level messages with deterministic latency can be inserted in the data stream and forwarded in the direction toward the front-ends
+ \item Links toward the front-ends run in bit-synchronous mode, i.e. the word alignment of the Serdes is always locked on Bit 0.
+ \item Links toward the read-out run in clock-synchronous mode only, i.e. the round-trip time for a packet can be measured with one word length (currently 5 ns) precision only.
+\end{itemize*}
+
+
+\subsection{Media Interfaces}
+
+\begin{figure}[htp]
+ \centering
+ \includegraphics[width=.5\textwidth]{figures/mediainterface_new.png}
+ \caption{New Media Interface Block Diagram}
+ \label{fig:medint_new}
+\end{figure}
+
+\paragraph{The link start-up procedure}~\\
+Each link has a defined master and slave side, given by the hard-wired configuration of each design. The reset of the TX and RX reset state machines follows the Lattice reference design.
+\begin{enumerate}
+ \item The master switches on its transceiver
+ \item The slave recovers the clock, resets itself as often as needed to lock on Bit 0. Lattice ECP3 reset recommendation takes 4~ms per try, but actual locking time seems to be about 1~ms. During this time, the RX clock (which is the main system clock) is not stable so that the slave logic needs to be in reset state.
+ \item The slave activates its transceiver (or: transceiver is already on, and slave switches to another idle comma character to signal readiness - to be investigated).
+ \item The master locks on the received stream / detects the new comma character. To make sure that the link is stable (e.g. when plugging in a cable by hand), a delay of about 500 ms is started
+ \item The master declares the connection active and changes its own idle comma character.
+\end{enumerate}
+
+Using a recovered clock to drive its own transceivers has the implication that if one link is lost and needs to be restarted, the full tree of boards behind the erroneous one needs to be resynchronized. It needs to be investigated if this is possible in a clean way or all these FPGA need to be resetted automatically because of loss of the RX clock. This needs in detail check of the transceiver PLLs in case of an unlock of the clock recovery PLL.
+
+The bi-directional hand-shake by changing comma characters is necessary when front-ends are able to actively send data to the read-out - it can be omitted if there is only a central master as in triggered systems.
+
+
+\paragraph{Comma Characters}~\\
+Each control word consists of two parts, a comma character and a data character. Assignment of individual character is not fixed and can be changed by constants in a vhdl package. CBMnet uses a set of 64 16 bit characters with big Hamming distance for error correction - this will not be done in TrbNet due to additional overhead and low error rates on transmission via SFP.
+
+
+\begin{table}[ht]
+\begin{center}
+\begin{tabular}{|c|c|c|c|}
+ \hline
+ \textbf{Name} & \textbf{Full Name} & \textbf{K Character} & \textbf{D Character}\\
+\hline\hline
+IDLE& Idle & BC & C5 (idle0) or 50 (idle1)\\
+SOP & Start of Packet & DC & Channel / Packet Type (not in first version)\\
+EOP & End of Packet & FD & CRC \\
+BGN & Begin of Transmission & 1C & Buffer Position\\
+REQ & Retransmit Request & 7C & Buffer Position\\
+DLM & DLM & FB & Deterministic Latency Message \\
+& & 3C & \\
+& & 5C & \\
+& & 9C & \\
+& & FC & \\
+& & F7 & \\
+Reset & Link reset & FE & none\\
+\hline
+\end{tabular}
+\caption{Comma Characters}
+\end{center}
+\end{table}
+
\input{CtsSlowControl}
\cleardoublepage
- \section{Media Interfaces}
- \input{MediaInterfaces}
\part{Experimental Setups and Configurations}
\section{Trigger Time vs Reference Time}
\input{trb3qs_part}
+\clearpage
+\part{Synchronous TrbNet}
+ \section{Clock Measurements}
+ \section{Media Interfaces}
+ \input{SyncMediaInterface}
\cleardoublepage
COP & Continuation of Packet & F7 & CRC \\
BGN & Begin of Transmission & 1C & Buffer Position\\
REQ & Retransmit Request & 7C & Buffer Position\\
-CTRL & Control & & Control Message \\
+DLM & DLM & FB & Deterministic Latency Message \\
+SYNC & Link Startup & 3C & Status \\
+& & 5C & \\
+& & 9C & \\
+& & DC & \\
+Reset & Link reset & FE & none\\
\hline
\end{tabular}
\caption{Comma Characters}