--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+\r
+library general_cores;\r
+use general_cores.wishbone_pkg.all;\r
+\r
+entity cri_trbnet_bridge_agwb_apl is\r
+ generic(\r
+ USE_CHANNELS : channel_config_t := (c_NO,c_NO,c_NO,c_YES)\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_40 : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ --TrbNet connect\r
+ APL_DATA_OUT : out std_logic_vector (16*4-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (3*4-1 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic_vector (4-1 downto 0);\r
+ APL_READ_IN : in std_logic_vector (4-1 downto 0);\r
+ APL_SHORT_TRANSFER_OUT : out std_logic_vector (4-1 downto 0);\r
+ APL_DTYPE_OUT : out std_logic_vector (4*4-1 downto 0);\r
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (32*4-1 downto 0);\r
+ APL_SEND_OUT : out std_logic_vector (4-1 downto 0);\r
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*4-1 downto 0);\r
+ APL_DATA_IN : in std_logic_vector (16*4-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (3*4-1 downto 0);\r
+ APL_TYP_IN : in std_logic_vector (3*4-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic_vector (4-1 downto 0);\r
+ APL_READ_OUT : out std_logic_vector (4-1 downto 0);\r
+ APL_RUN_IN : in std_logic_vector (4-1 downto 0);\r
+ APL_SEQNR_IN : in std_logic_vector (8*4-1 downto 0);\r
+ APL_FIFO_COUNT_IN : in std_logic_vector (11*4-1 downto 0);\r
+\r
+ --Internal Data Bus\r
+ WB_SLAVE_IN : in t_wishbone_slave_in;\r
+ WB_SLAVE_OUT : out t_wishbone_slave_out;\r
+\r
+-- EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0);\r
+ SEND_RESET_OUT : out std_logic;\r
+\r
+ --Debug\r
+ STAT : out std_logic_vector (31 downto 0);\r
+ CTRL : in std_logic_vector (31 downto 0)\r
+ );\r
+end entity;\r
+\r
+\r
+\r
+--700 - 71F DMA configuration\r
+\r
+\r
+\r
+architecture trb_net_bridge_pcie_apl_arch of trb_net_bridge_pcie_apl is\r
+ signal fifo_net_to_pci_read : std_logic_vector(3 downto 0);\r
+ signal fifo_net_to_pci_dout : std_logic_vector(32*4-1 downto 0);\r
+ signal fifo_net_to_pci_valid_read : std_logic_vector(3 downto 0);\r
+ signal fifo_net_to_pci_empty : std_logic_vector(3 downto 0);\r
+ signal next_APL_SEND_OUT : std_logic_vector(2 downto 0);\r
+ signal sender_control : std_logic_vector(32*4-1 downto 0);\r
+ signal sender_target : std_logic_vector(32*4-1 downto 0);\r
+ signal sender_error : std_logic_vector(32*4-1 downto 0);\r
+ signal sender_status : std_logic_vector(32*4-1 downto 0);\r
+ signal api_status : std_logic_vector(32*4-1 downto 0);\r
+\r
+ signal channel_address : integer range 0 to 3;\r
+\r
+ signal bus_ack_i : std_logic := '0';\r
+ signal bus_data_i : std_logic_vector(31 downto 0) := (others => '0');\r
+ signal bus_rdat_i : std_logic_vector(31 downto 0) := (others => '0');\r
+ signal bus_read_i : std_logic := '0';\r
+ signal bus_write_i : std_logic := '0';\r
+ signal bus_stb_rising : std_logic := '0';\r
+ signal bus_stb_last : std_logic := '0';\r
+ signal bus_write_last : std_logic := '0';\r
+ signal bus_read_last : std_logic := '0';\r
+\r
+ signal send_reset_counter : unsigned(10 downto 0);\r
+ \r
+ signal apl_data_out_i : std_logic_vector(15 downto 0);\r
+ signal apl_packet_num_out_i : std_logic_vector( 2 downto 0);\r
+ signal apl_datardy_out_i : std_logic;\r
+ signal apl_read_in_i : std_logic;\r
+ signal apl_shorttransfer_out_i : std_logic;\r
+ signal apl_dtype_out_i : std_logic_vector( 3 downto 0);\r
+ signal apl_errorpattern_out_i : std_logic_vector(31 downto 0);\r
+ signal apl_send_out_i : std_logic;\r
+ signal apl_target_addr_out_i : std_logic_vector(15 downto 0);\r
+ signal apl_data_in_i : std_logic_vector(15 downto 0);\r
+ signal apl_packet_num_in_i : std_logic_vector( 2 downto 0);\r
+ signal apl_typ_in_i : std_logic_vector( 2 downto 0);\r
+ signal apl_datardy_in_i : std_logic;\r
+ signal apl_read_out_i : std_logic;\r
+ signal apl_run_in_i : std_logic;\r
+ signal apl_seqnr_in_i : std_logic_vector( 7 downto 0);\r
+ signal apl_fifo_cnt_in_i : std_logic_vector( 10 downto 0);\r
+\r
+begin\r
+\r
+---- \r
+-- IDEA:\r
+-- \r
+-- * Two possibilities: \r
+-- 1) A mirror of all TrbNet registers. A set of 65535 registers has to be provided. Some idea of rm mode is needed.\r
+-- 2) A small interface is used to access registers. e.g.:\r
+-- - write to register the method of access (r, w, rm, wm), the register to access,\r
+-- - a dedicated register for write data, inlcuding end of transmission signal.\r
+-- - read register with answer from trbnet. Can be a long array. -> Store in fifo and read answers till FIFO empty.\r
+-- - end of data is encoded in read data. (a fifo almoust full in case of 1 ?)\r
+-- - after a fifo is empty, a status reg ist read -> e.g. Info on possible fifo full state during read.\r
+\r
+\r
+\r
+\r
+ STAT(9 downto 0) <= WB_SLAVE_IN.adr(9 downto 0);\r
+ STAT(10) <= bus_read_i;\r
+ STAT(11) <= bus_write_i;\r
+ STAT(12) <= WB_SLAVE_OUT.ack;\r
+ STAT(13) <= '0';--fifo_net_to_pci_read(1);\r
+ STAT(15 downto 14) <= WB_SLAVE_IN.data(1 downto 0);\r
+ STAT(16) <= '0'; --fifo_pci_to_net_read(1);\r
+ STAT(17) <= '0'; --fifo_pci_to_net_valid_read(1);\r
+ STAT(18) <= '0'; --fifo_pci_to_net_empty(1);\r
+ STAT(19) <= '0'; --fifo_pci_to_net_write(1);\r
+ STAT(20) <= APL_READ_IN(1);\r
+ STAT(21) <= '0'; --fifo_pci_to_net_full(1);\r
+ STAT(22) <= RESET;\r
+ STAT(23) <= '0';\r
+ STAT(24) <= '0'--fifo_net_to_pci_empty(1);\r
+ STAT(25) <= '0';\r
+ STAT(26) <= '0'; --fifo_net_to_pci_write(1);\r
+ STAT(31 downto 27) <= (others => '0');\r
+\r
+--------------------------------------------------------\r
+-- Terminate unused channles\r
+--------------------------------------------------------\r
+ APL_DATA_OUT (16*3-1 downto 0) <= (others => '0');\r
+ APL_PACKET_NUM_OUT (3*3-1 downto 0) <= (others => '0');\r
+ APL_DATAREADY_OUT (3-1 downto 0) <= (others => '0');\r
+ --APL_READ_IN(3-1 downto 0);\r
+ APL_SHORT_TRANSFER_OUT (3-1 downto 0) <= (others => '0');\r
+ APL_DTYPE_OUT (4*3-1 downto 0) <= (others => '0');\r
+ APL_ERROR_PATTERN_OUT (32*3-1 downto 0) <= (others => '0');\r
+ APL_SEND_OUT (3-1 downto 0) <= (others => '0');\r
+ APL_TARGET_ADDRESS_OUT (16*3-1 downto 0) <= (others => '0');\r
+ --APL_DATA_IN (16*3-1 downto 0);\r
+ --APL_PACKET_NUM_IN (3*3-1 downto 0);\r
+ --APL_TYP_IN (3*3-1 downto 0);\r
+ --APL_DATAREADY_IN (3-1 downto 0);\r
+ --APL_READ_OUT (3-1 downto 0);\r
+ --APL_RUN_IN (3-1 downto 0);\r
+ --APL_SEQNR_IN (8*3-1 downto 0);\r
+ --APL_FIFO_COUNT_IN (11*3-1 downto 0);\r
+\r
+--------------------------------\r
+-- r/w registers\r
+--------------------------------\r
+\r
+--------------------------------\r
+-- connection to SlowControl API\r
+--------------------------------\r
+ APL_DATA_OUT(16*4-1 downto 16*3) <= apl_data_out_i;\r
+ APL_PACKET_NUM_OUT(3*4-1 downto 3*3) <= apl_packet_num_out_i;\r
+ APL_DATAREADY_OUT(3) <= apl_datardy_out_i;\r
+ apl_read_in_i <= APL_READ_IN(3);\r
+ APL_SHORT_TRANSFER_OUT(3) <= apl_shorttransfer_out_i;\r
+ APL_DTYPE_OUT(4*4-1 downto 4*3) <= apl_dtype_out_i;\r
+ APL_ERROR_PATTERN_OUT(32*4-1 downto 16*3) <= apl_errorpattern_out_i;\r
+ APL_SEND_OUT(3) <= apl_send_out_i;\r
+ APL_TARGET_ADDRESS_OUT(16*4-1 downto 16*3) <= apl_target_addr_out_i;\r
+ \r
+ apl_data_in_i <= APL_DATA_IN(16*4-1 downto 16*3);\r
+ apl_packet_num_in_i <= APL_PACKET_NUM_IN(3*4-1 downto 3*3);\r
+ apl_typ_in_i <= APL_TYP_IN(3*4-1 downto 3*3);\r
+ apl_datardy_in_i <= APL_DATAREADY_IN(3);\r
+ APL_READ_OUT(3) <= apl_read_out_i;\r
+ apl_run_in_i <= APL_RUN_IN(3);\r
+ apl_seqnr_in_i <= APL_SEQNR_IN(8*4-1 downto 8*3);\r
+ apl_fifo_cnt_in_i <= APL_FIFO_COUNT_IN(11*4-1 downto 11*3);\r
+\r
+\r
+--------------------------------\r
+-- network reset\r
+--------------------------------\r
+ SEND_RESET_OUT <= not send_reset_counter(10);\r
+\r
+ process(CLK)\r
+ begin\r
+ if rising_edge(CLK) then\r
+ if RESET = '1' then\r
+ send_reset_counter <= (others => '1');\r
+ elsif WB_SLAVE_IN.adr = x"00000010" and bus_write_i = '1' and BUS_WDAT_IN(15) = '1' then\r
+ send_reset_counter <= (others => '0');\r
+ elsif send_reset_counter(10) = '0' then\r
+ send_reset_counter <= send_reset_counter + to_unsigned(1,1);\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+\r
+end architecture;\r
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+library general_cores;
+use general_cores.wishbone_pkg.all;
+
+entity cri_trbnet_bridge_agwb_endpoint is
+ generic(
+ USE_CHANNELS : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
+ g_SOURCE_TAG_WIDTH : integer;
+ g_SLR : integer range 0 to
+ );
+ port(
+ RESET : in std_logic;
+ CLK : in std_logic;
+ CLK_40_i : in std_logic;
+
+ -- connections to generic detector lev
+ --ALARM_BUS_OUT : out t_alarm_handler_bus;
+ --ALARM_BUS_IN : in t_alarm_handler_bus;
+
+ WB_SLAVE_IN : in t_wishbone_slave_in;
+ WB_SLAVE_OUT : out t_wishbone_slave_out;
+
+ -- connection to MediaInterface to Combiners
+ MED_DATAREADY_IN : in STD_LOGIC;
+ MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out STD_LOGIC;
+
+ MED_DATAREADY_OUT : out STD_LOGIC;
+ MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in STD_LOGIC;
+
+ MED_ERROR_IN : in std_logic_vector(2 downto 0);
+ SEND_RESET_OUT : out std_logic;
+ STAT : out std_logic_vector(31 downto 0);
+ STAT_ENDP : out std_logic_vector(31 downto 0);
+ STAT_API1 : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+
+architecture cri_trbnet_bridge_agwb_endpoint_arch of cri_trbnet_bridge_agwb_endpoint is
+
+
+ signal APL_STAT : std_logic_vector(31 downto 0);
+
+ signal APL_DATA_IN : std_logic_vector(4*16-1 downto 0);
+ signal APL_PACKET_NUM_IN : std_logic_vector(4*3-1 downto 0);
+ signal APL_DATAREADY_IN : std_logic_vector(4-1 downto 0);
+ signal APL_READ_OUT : std_logic_vector(4-1 downto 0);
+ signal APL_SHORT_TRANSFER_IN : std_logic_vector(4-1 downto 0);
+ signal APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0);
+ signal APL_SEND_IN : std_logic_vector(4-1 downto 0);
+ signal APL_DATA_OUT : std_logic_vector(4*16-1 downto 0);
+ signal APL_PACKET_NUM_OUT : std_logic_vector(4*3-1 downto 0);
+ signal APL_TYP_OUT : std_logic_vector(4*3-1 downto 0);
+ signal APL_DATAREADY_OUT : std_logic_vector(4-1 downto 0);
+ signal APL_READ_IN : std_logic_vector(4-1 downto 0);
+ signal APL_RUN_OUT : std_logic_vector(4-1 downto 0);
+ signal APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0);
+ signal APL_TARGET_ADDRESS_OUT : std_logic_vector(4*16-1 downto 0);
+ signal APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0);
+ signal APL_TARGET_ADDRESS_IN : std_logic_vector(4*16-1 downto 0);
+ signal APL_FIFO_COUNT_OUT : std_logic_vector(4*11-1 downto 0);
+ signal APL_MY_ADDRESS_IN : std_logic_vector(15 downto 0);
+
+ signal buf_api_stat_fifo_to_int : std_logic_vector(4*32-1 downto 0);
+ signal buf_api_stat_fifo_to_apl : std_logic_vector(4*32-1 downto 0);
+
+ signal CLK_EN : std_logic;
+
+ signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+ signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0);
+ signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0);
+ signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+ signal m_DATAREADY_IN : std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ signal m_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+ signal m_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+ signal m_READ_OUT : std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ signal MPLEX_CTRL : std_logic_vector (31 downto 0);
+
+ signal apl_to_buf_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal apl_to_buf_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ signal tmp_apl_to_buf_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
+ signal apl_to_buf_INIT_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
+
+ signal buf_to_apl_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal buf_to_apl_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
+ signal buf_to_apl_INIT_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
+
+ signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal apl_to_buf_REPLY_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
+ signal apl_to_buf_REPLY_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
+
+ signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal buf_to_apl_REPLY_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
+ signal buf_to_apl_REPLY_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
+
+
+ signal STAT_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal STAT_INIT_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal CTRL_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal CTRL_LOCKED : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal RESET_i : std_logic;
+ signal RESET_CNT : std_logic_vector(1 downto 0);
+ signal counter : std_logic_vector(12 downto 0);
+ signal buf_MED_DATAREADY_OUT : std_logic;
+ signal RESET_N_i : std_logic;
+
+ signal reg_extended_trigger_information : std_logic_vector(15 downto 0);
+
+begin
+ CLK_EN <= '1';
+ APL_MY_ADDRESS_IN <= x"F00C";
+ RESET_i <= RESET;
+ RESET_N_i <= not RESET;
+
+
+ MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT;
+
+
+ ----------------------------------------------------------
+ -- MULTIPLEXER : mux MedInt to iobufs
+ ----------------------------------------------------------
+ MPLEX_CTRL <= (others => '0');
+ THE_MPLEX: trb_net16_io_multiplexer
+ port map (
+ CLK => CLK,
+ RESET => RESET_i,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_DATAREADY_OUT => buf_MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT => m_DATA_IN,
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
+ INT_READ_IN => m_READ_OUT,
+ INT_DATAREADY_IN => m_DATAREADY_OUT,
+ INT_DATA_IN => m_DATA_OUT,
+ INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
+ INT_READ_OUT => m_READ_IN,
+ CTRL => MPLEX_CTRL
+ );
+
+
+ ----------------------------------------------------------
+ -- IoBufs: only for used channel (here mosgt propably
+ -- only SlowCntr (3)). All other channels are terminated
+ -- as on CRI data is transmitted directly via PCIe
+ ----------------------------------------------------------
+ gen_iobufs : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
+ gen_used_channel : if USE_CHANNELS(i) = c_YES generate
+ IOBUF: trb_net16_iobuf
+ generic map (
+ USE_CHECKSUM => cfg_USE_CHECKSUM(i),
+ INIT_CAN_SEND_DATA => c_YES,
+ INIT_CAN_RECEIVE_DATA => c_NO,
+ REPLY_CAN_SEND_DATA => c_NO,
+ REPLY_CAN_RECEIVE_DATA => c_YES
+ )
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => RESET_i,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
+ MED_INIT_READ_IN => m_READ_IN(i*2),
+ MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
+ MED_REPLY_READ_IN => m_READ_IN(i*2+1),
+ MED_DATAREADY_IN => m_DATAREADY_IN(i),
+ MED_DATA_IN => m_DATA_IN(i*c_DATA_WIDTH+15 downto i*c_DATA_WIDTH),
+ MED_PACKET_NUM_IN => m_PACKET_NUM_IN(i*c_NUM_WIDTH+2 downto i*c_NUM_WIDTH),
+ MED_READ_OUT => m_READ_OUT(i),
+ MED_ERROR_IN => MED_ERROR_IN,
+ -- Internal direction port
+ INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
+ INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_INIT_READ_IN => buf_to_apl_INIT_READ(i),
+ INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i),
+ INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i),
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),
+ INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i),
+ INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i),
+ INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i),
+ -- Status and control port
+ STAT_GEN => STAT_GEN((i+1)*32-1 downto i*32),
+ STAT_IBUF_BUFFER => STAT_INIT_BUFFER((i+1)*32-1 downto i*32),
+ CTRL_GEN => CTRL_GEN((i+1)*32-1 downto i*32)
+ );
+ end generate;
+
+ -- terminate trigger, data and unused channel.
+ gen_not_used_channel : if USE_CHANNELS(i) = c_NO generate
+ apl_to_buf_INIT_READ(i) <= '0';
+ apl_to_buf_INIT_DATAREADY(i) <= '0';
+ apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ apl_to_buf_REPLY_DATAREADY(i) <= '0';
+ apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ apl_to_buf_REPLY_READ(i) <= '0';
+ apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ buf_to_apl_INIT_READ(i) <= '0';
+ buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ buf_to_apl_INIT_DATAREADY(i) <= '0';
+ buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ buf_to_apl_REPLY_DATAREADY(i) <= '0';
+ buf_to_apl_REPLY_READ(i) <= '0';
+ buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ CTRL_GEN((i+1)*32-1 downto i*32) <= (others => '0');
+ STAT_GEN((i+1)*32-1 downto i*32) <= (others => '0');
+ STAT_INIT_BUFFER((i+1)*32-1 downto i*32) <= (others => '0');
+
+ termbuf: trb_net16_term_buf
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => m_DATAREADY_IN(i),
+ MED_DATA_IN => m_DATA_IN(i*16+15 downto i*16),
+ MED_PACKET_NUM_IN => m_PACKET_NUM_IN(i*3+2 downto i*3),
+ MED_READ_OUT => m_READ_OUT(i),
+
+ MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
+ MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
+ MED_INIT_READ_IN => m_READ_IN(i*2),
+ MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
+ MED_REPLY_READ_IN => m_READ_IN(i*2+1)
+ );
+ end generate;
+ end generate;
+
+ CTRL_GEN <= (others => '0');
+
+ -------------------------------------------------------
+ -- generate an (active) API only for SlowControl channel
+ -------------------------------------------------------
+ gen_pas_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
+ gen_used_api : if USE_CHANNELS(i) = c_YES generate
+ DAT_ACTIVE_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_ACTIVE,
+ FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
+ FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
+ FORCE_REPLY => cfg_FORCE_REPLY(i),
+ SBUF_VERSION => 0,
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS => c_YES,
+ BROADCAST_BITMASK => x"FF"
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET_i,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN(i*16+15 downto i*16),
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN(i*3+2 downto i*3),
+ APL_DATAREADY_IN => APL_DATAREADY_IN(i),
+ APL_READ_OUT => APL_READ_OUT(i),
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(i),
+ APL_DTYPE_IN => APL_DTYPE_IN(i*4+3 downto i*4),
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN(i*32+31 downto i*32),
+ APL_SEND_IN => APL_SEND_IN(i),
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN(i*16+15 downto i*16),
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT(i*16+15 downto i*16),
+ APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT(i*3+2 downto i*3),
+ APL_TYP_OUT => APL_TYP_OUT(i*3+2 downto i*3),
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT(i),
+ APL_READ_IN => APL_READ_IN(i),
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT(i),
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_LENGTH_IN => x"FFFF",
+ APL_SEQNR_OUT => APL_SEQNR_OUT(i*8+7 downto i*8),
+ APL_FIFO_COUNT_OUT => APL_FIFO_COUNT_OUT(i*11+10 downto i*11),
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
+ INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
+ INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+ INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
+ CTRL_SEQNR_RESET => '0',
+ -- Status and control port
+ STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl(i*32+31 downto i*32)
+ STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int(i*32+31 downto i*32),
+ );
+
+ end generate;
+ gen_no_api : if USE_CHANNELS(i) = c_NO generate
+ APL_READ_OUT(i) <= '1';
+ APL_DATA_OUT(i*16+15 downto i*16) <= (others => '0');
+ APL_PACKET_NUM_OUT(i*3+2 downto i*3) <= (others => '0');
+ APL_TYP_OUT(i*3+2 downto i*3) <= (others => '0');
+ APL_DATAREADY_OUT(i) <= '0';
+ APL_RUN_OUT(i) <= '0';
+ APL_SEQNR_OUT(i*8+7 downto i*8) <= (others => '0');
+ buf_api_stat_fifo_to_int(i*32+31 downto i*32) <= (others => '0');
+ buf_api_stat_fifo_to_apl(i*32+31 downto i*32) <= (others => '0');
+ tmp_apl_to_buf_init_data(i*16+15 downto i*16) <= (others => '0');
+ APL_FIFO_COUNT_OUT(i*11+10 downto i*11) <= (others => '0');
+ end generate;
+ end generate;
+
+
+ APL : cri_trbnet_bridge_agwb_apl
+ generic map(
+ USE_CHANNELS => USE_CHANNELS
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET_i,
+ CLK_EN => CLK_EN,
+ APL_DATA_OUT => APL_DATA_IN,
+ APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN,
+ APL_DATAREADY_OUT => APL_DATAREADY_IN,
+ APL_READ_IN => APL_READ_OUT,
+ APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_OUT => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_IN,
+ APL_SEND_OUT => APL_SEND_IN,
+ APL_DATA_IN => APL_DATA_OUT,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT,
+ APL_TYP_IN => APL_TYP_OUT,
+ APL_DATAREADY_IN => APL_DATAREADY_OUT,
+ APL_READ_OUT => APL_READ_IN,
+ APL_RUN_IN => APL_RUN_OUT,
+ APL_SEQNR_IN => APL_SEQNR_OUT,
+ APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN,
+ APL_FIFO_COUNT_IN => APL_FIFO_COUNT_OUT,
+ EXT_TRIGGER_INFO => reg_extended_trigger_information,
+ WB_SLAVE_IN => WB_SLAVE_IN,
+ WB_SLAVE_OUT => WB_SLAVE_OUT,
+ SEND_RESET_OUT => SEND_RESET_OUT,
+ STAT => STAT,
+ CTRL => (others => '0')
+ );
+
+STAT_ENDP(0) <= APL_SEND_IN(1);
+STAT_ENDP(4 downto 1) <= WB_SLAVE_IN.adr(3 downto 0);
+STAT_ENDP(5) <= WB_SLAVE_IN.we;
+STAT_ENDP(6) <= APL_READ_OUT(1);
+STAT_ENDP(7) <= buf_MED_DATAREADY_OUT;
+STAT_ENDP(11 downto 8) <= APL_DATA_OUT(51 downto 48);
+STAT_ENDP(13 downto 12) <= APL_PACKET_NUM_OUT(4 downto 3);
+STAT_ENDP(14) <= APL_DATAREADY_OUT(3);
+STAT_ENDP(15) <= buf_to_apl_REPLY_DATAREADY(0);
+STAT_ENDP(16) <= APL_READ_IN(3);
+
+STAT_ENDP(17) <= '0';
+STAT_ENDP(18) <= '0';
+
+STAT_ENDP(21 downto 19) <= APL_PACKET_NUM_OUT(11 downto 9);
+STAT_ENDP(22) <= APL_DATAREADY_OUT(3);
+STAT_ENDP(23) <= APL_READ_IN(3);
+STAT_ENDP(31 downto 24) <= APL_DATA_OUT(55 downto 48);
+
+
+STAT_API1(3 downto 0) <= apl_to_buf_REPLY_DATA(19 downto 16);
+STAT_API1(7 downto 4) <= apl_to_buf_REPLY_DATA(19 downto 16);
+
+STAT_API1(11) <= apl_to_buf_REPLY_READ(3);
+STAT_API1(12) <= buf_to_apl_REPLY_DATAREADY(3);
+STAT_API1(13) <= apl_to_buf_INIT_DATAREADY(3);
+STAT_API1(14) <= buf_to_apl_INIT_READ(3);
+STAT_API1(31 downto 15) <= (others => '0');
+
+--STAT_API1 <= buf_api_stat_fifo_to_int((2)*32-1 downto (1)*32);
+
+end architecture;
jspc29 / cri.git / commitdiff