Add design skeleton for PWM FPGAs

diff --git a/thresholds/compile.pl b/thresholds/compile.pl
new file mode 120000 (symlink)
index 0000000..8a19aa6
--- /dev/null
+++ b/thresholds/compile.pl
@@ -0,0 +1 @@
+../../trb3sc/scripts/compile.pl
\ No newline at end of file

diff --git a/thresholds/config_compile_frankfurt.pl b/thresholds/config_compile_frankfurt.pl
new file mode 100644 (file)
index 0000000..cfd0459
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+++ b/thresholds/config_compile_frankfurt.pl
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+Familyname  => 'MachXO3LF',
+Devicename  => 'LCMXO3LF-4300E',
+Package     => 'WLCSP81',
+Speedgrade  => '5',
+
+TOPNAME                      => "thresholds",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
+lattice_path                 => '/d/jspc29/lattice/diamond/3.7_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/K-2015.09/',
+# synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+# synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+# synplify_command             => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
+nodelist_file                => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+#pinout_file                  => '', #name of pin-out file, if not equal TOPNAME
+include_TDC                  => 0,
+include_GBE                  => 0,
+
+#Report settings
+firefox_open                 => 0,
+twr_number_of_errors         => 20,
+no_ltxt2ptxt                 => 1,  #if there is no serdes being used
+make_jed                     => 1,

diff --git a/thresholds/par.p2t b/thresholds/par.p2t
new file mode 100644 (file)
index 0000000..39a0684
--- /dev/null
+++ b/thresholds/par.p2t
@@ -0,0 +1,21 @@
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 1
+-c 1
+-e 2
+#-g guidefile.ncd
+#-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1

diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj
new file mode 100644 (file)
index 0000000..d3897b3
--- /dev/null
+++ b/thresholds/thresholds.prj
@@ -0,0 +1,86 @@
+#--  Synopsys, Inc.
+#--  Version J-2015.03L-SP1
+#--  Project file /d/jspc22/trb/git/LogicBox/diamond/LogicBox/run_options.txt
+
+#project files
+
+add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
+
+#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../logicbox/code/uart_sctrl.vhd"
+add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../mdcfee/code/pwm.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+
+add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
+add_file -vhdl -lib work "../../logicbox/cores/efb.vhd"
+add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
+add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
+
+add_file -vhdl -lib work "thresholds.vhd"
+
+
+
+#implementation: "Thresholds"
+impl -add workdir -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#par_1 attributes
+set_option -job par_1 -add par
+
+#device options
+set_option -technology MACHXO3LF
+set_option -part LCMXO3LF_4300E
+set_option -package UWG81CTR
+set_option -speed_grade -5
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "thresholds"
+
+# mapper_options
+set_option -frequency 1
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -srs_instrumentation 1
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file "workdir/thresholds.edf"
+
+#set log file 
+set_option log_file "workdir/thresholds.srf" 
+impl -active "workdir"

diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
new file mode 100644 (file)
index 0000000..33a5c59
--- /dev/null
+++ b/thresholds/thresholds.vhd
@@ -0,0 +1,227 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library machxo3lf;\r
+use machxo3lf.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+\r
+entity thresholds is\r
+  port(\r
+    CLK    : in  std_logic;\r
+  \r
+    OUTPUT : out std_logic_vector(15 downto 0);\r
+         TX_IN  : in  std_logic;\r
+         RX_OUT : out std_logic\r
+--     MISO_OUT : out std_logic;\r
+--     MOSI_IN  : in  std_logic;\r
+--     SCLK_IN  : in  std_logic;\r
+--     CS_IN    : in  std_logic\r
+    );\r
+end entity;\r
+\r
+architecture arch of thresholds is\r
+  signal clk_osc, clk_i : std_logic;\r
+\r
+  signal uart_rx_data : std_logic_vector(31 downto 0);\r
+  signal uart_tx_data : std_logic_vector(31 downto 0);\r
+  signal uart_addr    : std_logic_vector(7 downto 0);\r
+  signal bus_read     : std_logic := '0';\r
+  signal bus_write    : std_logic := '0';\r
+  signal bus_ready    : std_logic; \r
+  signal uart_busy    : std_logic; \r
+\r
+  signal sed_error : std_logic;\r
+  signal sed_debug : std_logic_vector(31 downto 0);\r
+  signal controlsed_i : std_logic_vector(3 downto 0);\r
+ \r
+  signal pwm_data_i : std_logic_vector(15 downto 0);\r
+  signal pwm_write_i : std_logic;\r
+  signal pwm_addr_i  : std_logic_vector(4 downto 0);\r
+\r
+  signal ram_write_i : std_logic;\r
+  signal ram_data_i: std_logic_vector(7 downto 0);\r
+  signal ram_data_o: std_logic_vector(7 downto 0);\r
+  signal ram_addr_i: std_logic_vector(3 downto 0);\r
+\r
+  signal flashram_addr_i : std_logic_vector(3 downto 0);\r
+  signal flashram_cen_i  : std_logic;\r
+  signal flashram_reset  : std_logic;\r
+  signal flashram_write_i: std_logic;\r
+  signal flashram_data_i : std_logic_vector(7 downto 0);\r
+  signal flashram_data_o : std_logic_vector(7 downto 0);\r
+\r
+  signal flash_command : std_logic_vector(2 downto 0);\r
+  signal flash_page    : std_logic_vector(12 downto 0);\r
+  signal flash_go      : std_logic;\r
+  signal flash_busy    : std_logic;\r
+  signal flash_err     : std_logic;\r
+\r
+\r
+  component OSCH\r
+    generic (NOM_FREQ: string := "33.25");\r
+    port (\r
+      STDBY :IN std_logic;\r
+      OSC   :OUT std_logic;\r
+      SEDSTDBY :OUT std_logic\r
+      );\r
+  end component; \r
+ \r
+  component UFM_WB\r
+    port(\r
+      clk_i : in std_logic;\r
+      rst_n : in std_logic;\r
+      cmd       : in std_logic_vector(2 downto 0);\r
+      ufm_page  : in std_logic_vector(12 downto 0);\r
+      GO        : in std_logic;\r
+      BUSY      : out std_logic;\r
+      ERR       : out std_logic;\r
+      mem_clk   : out std_logic;\r
+      mem_we    : out std_logic;\r
+      mem_ce    : out std_logic;\r
+      mem_addr  : out std_logic_vector(3 downto 0);\r
+      mem_wr_data : out std_logic_vector(7 downto 0);\r
+      mem_rd_data : in  std_logic_vector(7 downto 0)\r
+      );\r
+  end component;\r
+  \r
+begin\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock\r
+---------------------------------------------------------------------------\r
+clk_source: OSCH\r
+  generic map ( NOM_FREQ => "33.25" )\r
+  port map (\r
+    STDBY    => '0',\r
+    OSC      => clk_osc,\r
+    SEDSTDBY => open\r
+  );\r
+\r
+clk_i <= clk_osc;  \r
+  \r
+---------------------------------------------------------------------------\r
+-- UART\r
+---------------------------------------------------------------------------\r
+THE_UART : entity work.uart_sctrl\r
+  generic map(\r
+    CLOCK_SPEED => 133000000\r
+    )\r
+  port map(\r
+    CLK     => clk_i,\r
+    RESET   => '0',\r
+    UART_RX => TX_IN,\r
+    UART_TX => RX_OUT,\r
+    \r
+    DATA_OUT  => uart_rx_data,\r
+    DATA_IN   => uart_tx_data,\r
+    ADDR_OUT  => uart_addr,       \r
+    WRITE_OUT => bus_write,\r
+    READ_OUT  => bus_read,\r
+    READY_IN  => bus_ready,\r
+    \r
+    DEBUG     => open\r
+    );\r
+\r
+\r
+PROC_REGS : process begin\r
+  wait until rising_edge(clk_i);\r
+  bus_ready <= '0';\r
+  pwm_write_i<= '0';\r
+  if bus_read = '1' then\r
+    bus_ready <= '1';\r
+    case uart_addr is\r
+      when x"ee" => uart_tx_data <= sed_debug;\r
+    end case;\r
+  elsif bus_write = '1' then\r
+    if uart_addr < x"10" then\r
+      pwm_data_i <= uart_rx_data(15 downto 0);\r
+      pwm_addr_i <= uart_addr(4 downto 0);\r
+      pwm_write_i<= '1';\r
+    else\r
+      case uart_addr is\r
+--         when x"10" => reg <= uart_rx_data;\r
+        when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
+      end case;\r
+    end if;  \r
+  end if;\r
+end process;\r
+\r
+\r
+THE_SED : entity work.sedcheck\r
+  port map(\r
+    CLK        => clk_i,\r
+    ERROR_OUT  => sed_error,\r
+    \r
+    CONTROL_IN => controlsed_i,\r
+    DEBUG      => sed_debug\r
+    );\r
+\r
+---------------------------------------------------------------------------\r
+-- PWM\r
+---------------------------------------------------------------------------        \r
+THE_PWM_GEN : entity work.pwm_generator\r
+  generic map(\r
+    CHANNELS => 16\r
+    )\r
+  port map(\r
+    CLK        => clk_i,\r
+    DATA_IN    => pwm_data_i,\r
+    DATA_OUT   => open,\r
+    COMP_IN    => (others => '0'),\r
+    WRITE_IN   => pwm_write_i,\r
+    ADDR_IN    => pwm_addr_i,\r
+    PWM        => OUTPUT\r
+    );    \r
+    \r
+---------------------------------------------------------------------------\r
+-- Flash Controller\r
+---------------------------------------------------------------------------      \r
+\r
+THE_FLASH_RAM : entity work.flashram\r
+  port map(\r
+    DataInA   => ram_data_i,\r
+    AddressA  => ram_addr_i,\r
+    ClockA    => clk_i, \r
+    ClockEnA  => '1',\r
+    WrA       => ram_write_i, \r
+    ResetA    => '0',\r
+    QA        => ram_data_o,\r
+\r
+    DataInB   => flashram_data_i,\r
+    AddressB  => flashram_addr_i,\r
+    ClockB    => clk_i,\r
+    ClockEnB  => flashram_cen_i,\r
+    WrB       => flashram_write_i, \r
+    ResetB    => flashram_reset,\r
+    QB        => flashram_data_o\r
+    );\r
+\r
+\r
+\r
+THE_FLASH : UFM_WB\r
+  port map(\r
+    clk_i => clk_i,\r
+    rst_n => '1',\r
+    cmd       => flash_command,\r
+    ufm_page  => flash_page,\r
+    GO        => flash_go,\r
+    BUSY      => flash_busy,\r
+    ERR       => flash_err,\r
+    mem_clk    => open,\r
+    mem_we      => flashram_write_i,\r
+    mem_ce      => flashram_cen_i,\r
+    mem_addr    => flashram_addr_i,\r
+    mem_wr_data => flashram_data_i,\r
+    mem_rd_data => flashram_data_o\r
+    );    \r
+    \r
+    \r
+end architecture;\r
+\r
+       \r
+       
\ No newline at end of file