update Hades list of addresses

diff --git a/networkaddresses.tex b/networkaddresses.tex
index 60dfa3480fe4358544dc5f8f16bcaf03a6b6e041..cddf905c30d5202b1ce49cee8c0788cd36441976 100755 (executable)
--- a/networkaddresses.tex
+++ b/networkaddresses.tex
@@ -14,21 +14,22 @@ On boards with two or more FPGAs each FPGA gets its own address. The FPGA provid
 1000 - 17FF & MDC Concentrator & 2nd digit: inner(0) / outer(1) MDC; 3rd digit: sector (0-5), 4th
 digit FPGA (0-4) \\
 2000 - 2FFF & MDC OEP & 2nd digit: MDC layer (0-3); 3rd digit: sector (0-5); 4th digit MBO (0-F) \\
-3800 - 38FF & Pion  & 3rd digit station, 4th digit side (x/y)\\
 5000 - 50FF & StartTRB3 & Start/Veto/iTOF. 3rd digit: 0: Start, 1: Veto, 4th digit: FPGA (0-5)\\ 
 5555        & SEB & Dummy Address used in headers generated by SubEventBuilders \\
 5800 - 58FF & RPC & 3rd digit sector (0..5), 4th digit TDC (0..8) \\
 5C00 - 5CFF & TOF & 3rd digit sector (0..6), 4th digit TDC (0..3) \\ 
 5D00 - 5D0F & iTOF & 4th digit TDC (0..5) \\
 6000 - 60FF & Ecal & Ecal read-out. 3rd digit: Sector, 4th digit: Readout Board (0-6)\\
-6400 - 64FF & STT &  3rd digit board number (0-9), 4th digit FPGA (1-4) \\
-6800 - 68FF & f-RPC &  3rd digit board number (0-1), 4th digit FPGA (1-4)\\
+6400 - 64FF & STT &  3rd digit detector part (0-7), 4th digit FPGA (0-6) \\
+6700 - 67FF & Wall & 3rd digit board (0..2), 4th digit TDC (0..3) \\
+6800 - 68FF & f-RPC &  3rd digit board number (0-1), 4th digit FPGA (0-3)\\
 7000 - 7FFF & RICH & DiRich modules. 2nd/3rd digit backplane number, 4th digit: DiRich (0-11)\\
 8000 - 80FF & Central Hub & central hub\\
 8100 - 81FF & MDC Hub & Hub for inner MDC (3rd digit 0) or outer MDC (1)\\
 83C0 - 83DF & RICH Hubs & Hubs for old RICH, 4th digit: hub number (0..13)\\
 84C0 - 84CF & RPC Hubs & Hubs for RPC, 4th digit: sector (0..5) \\
 86C0 - 86CF & TOF Hub & Hubs (central FPGA TRB3), 4th digit: sector(0..6)\\
+8700 - 870F & Wall Hub & 4th digit: board(0..2)\\
 8800 - 88FF & Central Hub & Central Hubs with GbE  \\
 8880 - 88BF & Start Hub & Hubs for timing detectors, 8880: Start, 8890 Veto\\
 8900 - 89FF & Pion Tracker Hub & 3rd digit: station\\
@@ -37,7 +38,7 @@ digit FPGA (0-4) \\
 8C00 - 8CFF & f-RPC Hubs & 3rd digit board number (0-1)\\
 8D00 - 8D00 & iTOF & innerTOF \\
 F000 - FDFF & Test Setups & \\
-FE00 - FFFF & Broadcasts & Reserved for extension of broadcast addresses
+FE00 - FFFF & Broadcasts & Broadcast addresses
 \end{tabularx}
 \caption{Network Addresses}
 \label{networkaddresses}
@@ -52,6 +53,7 @@ FE00 - FFFF & Broadcasts & Reserved for extension of broadcast addresses
 \hline
 3000 - 31FF & RICH ADCM & 3rd digit: sector (0-5); 4th digit: segment (0-4) \\
 3200 - 37FF & Shower AddOn & 3rd digit: sector (0-5); 4th digit: FPGA (0-2) \\
+3800 - 38FF & Pion  & 3rd digit station, 4th digit side (x/y)\\
 4000 - 400F & Start & Start detector \\
 4010 - 401F & Veto & Veto detector \\
 4400 - 44FF & Wall & 3 TRBs for forward wall \\
@@ -100,6 +102,7 @@ If the bitmask configuration of an endpoint contains two unset bits it will answ
 \end{center}
 \end{table}
 
+The extended broadcast addresses in the range 0xFE00 - 0xFEFF can be found in the Trb3 Manual.
 
 \subsection{SubEventIDs}
 \label{subeventids}
@@ -113,10 +116,11 @@ MDC        & 1000 - 17FF & 12 & second digit is inner(0) or outer(1) MDC, 3rd di
 RICH       & 83C0 - 83CF & 12  &  RICH hubs\\
 RPC        & 84C0 - 84FF & 6  & \\
 TOF        & 86C0 - 86FF & 6 & \\
+Wall       & 8700 - 870F & 3 & \\
 CTS        & 8800 - 887F & 1 & central Hub, e.g. CTS, trigger generation \\
 Start      & 8880 - 88FF & 2 & 8880: Start, 8890: Veto \\
 Ecal       & 8A00 - 8A0F & 6 & Calorimeter\\
-FT         & 8B00 - 8BFF & 10 & Forward Tracker\\
+STT        & 8B00 - 8BFF & 10 & Forward Tracker\\
 f-RPC      & 8C00 - 8CFF & 2 & Forward RPC\\
 iTOF       & 8D00 - 8DFF & 1 & inner TOF\\
 \hline