--- /dev/null
+The Flash of the Padiwa FPGA contains two parts, the configuration ROM and the user ROM. Both can be erased individually and are organized in pages with 16 Byte each. Both are mapped to the same page address space:
+
+\begin{itemize*}
+\item Pages 0 - 5758 (0x0000 - 0x167E) Configuration ROM
+\item Pages 7168 - 7936 (0x1C00 - 0x1EFF) User space
+\end{itemize*}
+
+A flash command consists of a three Bit operation (Bit 15-13 in SPI register 0x50) and a 13 Bit page address (Bit 12 - 0). The address must be supplied for every command to affect the correct part of the Flash ROM.
+\begin{description*}
+\item[0x0 read]Read a page from Flash and store it in internal RAM.
+\item[0x4 write] Write a page of the Flash from the internal RAM.
+\item[0x8 enable] Enable Flash ROM. Has to be issued before any read/write operation. No address required.
+\item[0xA disable] Disable Flash ROM. Should be done after finishing all operations. No address required.
+\item[0xE erase] Erase either user or configuration Flash, depending on page address.
+\end{description*}
--- /dev/null
+All configuration is done via a single-device SPI bus. The interface is kept similar to the LTC2600 to use the same SPI master code.
+Note that up to 16 commands can be sent to a board with one trbnet access: Load all commands to registers 0xd400 - 0xd40f, set the correct amount in 0xd411 plus Bit 7 to select the multi-write mode.
+
+\begin{table}
+ \begin{tabularx}{\textwidth}{c|c|X}
+\textbf{Bits} & \textbf{Name} & \textbf{Content} \\
+\hline
+31 -- 24 & Select & See table \ref{tab:spiselect}\\
+23 -- 20 & Command & Command, 0: read, 8: write, other: no operation \\
+19 -- 16 & Channel & Channel / Register select (0 -- 15)\\
+15 -- 0\newline (\& following$\dagger$)& Data & 16 Bit data payload for write commands\\
+
+ \end{tabularx}
+\caption{SPI first data word structure. Following 32 bit words contain payload only}
+\label{tab:spidata}
+\end{table}
+
+
+\begin{table}
+ \begin{tabularx}{\textwidth}{c|c|c|X}
+\textbf{Value} & \textbf{Register} & \textbf{Name} & \textbf{Description} \\
+\hline
+0x00 & any & PWM & Write/read settings for PWM channels 0 - 15.\\
+0x10 & 0--3 & UId/Temp & read unique id. 64 Bit Id is divided in 4 16 Bit words. (r/o)\\
+0x10 & 4 & UId/Temp & Board Temperature. Units are 1/16 degrees centigrade (r/o)\\
+0x20 & 0 & I/O & Input Enable, one bit per input. 0: enable (default), 1: disable.\\
+0x20 & 1 & I/O & Input Status, one bit per input, represents the current status of the pin.\\
+0x20 & 2 & I/O & LED. Write: Override LED status. Bit 0-3: LED in alphabetical order. Bit 4: disable override. Read: LED status. LEDs are off by default due to influence on PMTs.\\
+0x20 & 3 & I/O & Monitor Select. 4 Bit to select one input to be routed to test output (SPARE\_LINE 5\&6)\\
+0x20 & 4 & I/O & Input Invert, one bit for each input signal\\
+0x20 & 5 & I/O & Input Stretch, one bit for each input signal. The input signal gets stretched to at least two clock cycles (about 16 ns) length. The timing information of the falling edge is lost.\\
+0x20 & 6 & I/O & Temperature Compensation, a 16 Bit value to adjust thresholds
+when temperature is changing. See below. \\
+0x20 & 10 & Test & Reads a word from the test Fifo. \\
+0x21 & 0--2 & Design & Design Information. Register 0/1: lower/upper part of
+Unix timestamp of time of compilation. Register 2: Padiwa version number.\\
+0x40 & any & Memory & Read/Write to/from RAM. 16 registers with 8 Bit each.\\
+0x50 & 0 & Flash & Execute Flash command.\\
+0x51 & 0--1 & Flash & Load RAM content to PWM settings. Channel Bit 0 selects upper or lower half of PWM channels. No data payload\\
+0x5C & 0 & Flash & Enable access to configuration Flash when a '1' is written to register 0. Be careful!\\
+ \end{tabularx}
+\caption{SPI component selection}
+\label{tab:spiselect}
+\end{table}
--- /dev/null
+As measured, the thresholds of input LVDS buffers shift by about 0.1 mV/K. For compensation, an offset is
+added to the actually set threshold according to \\
+$\mbox{Offset} = \mbox{Temperature} \cdot \mbox{CompensationSetting} / 256$\\
+where the temperature is given in degrees centigrade. Note that the temperature
+is measured with 1/16 degree resolution.
+This feature is not available in all design versions.
+If register 0x26 does not exist, it is not present.
--- /dev/null
+The device contains:
+\begin{itemize*}
+ \item 16 channel LVDS input/output using discriminators only
+ \item SPI Interface for configuration / monitoring
+ \item PWM generation with 16 channels and 16 bit for each of the input comparators
+ \item 1-wire interface for temperature sensor and unique ID
+ \item on-chip Flash to store configuration data
+\end{itemize*}
--- /dev/null
+This document describes the PaDiWa discriminator front-end board as
+well as the Padiwa Amps integrator board. Although the hardware is
+different, they share similar concepts and firmwares.
+
+The front-end is used in combination with corresponding TDC
+implementations in the TRB3. A special AddOn is used on the TRB3 to
+connect up to four front-ends to one FPGA.
--- /dev/null
+Just some quick notes from a first user perspectives.
+
+\begin{itemize*}
+\item The thresholds can either be set by the \verb!padiwa.pl! script
+ in the daqtools repository or via the web frontend (choose Padiwa
+ SPI and set the reference to 3300 mV). There's also some script
+ which sets the thresholds automagically, see folder \verb!thresholds!.
+\item Due to the somewhat special design, it is expected behaviour
+ that you see no counts for very low thresholds, then some noise at
+ about the bias voltage ($\approx1.7\,\text{V}$) and then again no
+ counts at very high thresholds. The Board is designed for negative
+ input peaks, but positive could also work.
+\item Maybe you need to set the invert feature of the Padiwa board
+ such that the TDC in the peripheral accepts the events (only events
+ which are green highlighted in the Webinterface seem to be read
+ out). This is not valid for the two edge versions of the padiwa TDC
+ firmwares.
+\item Ensure that the TRB3 and your PaDiWa FEE share the same ground,
+ otherwise the \verb!padiwa.pl! might return a random uid or
+ temperature, so your frontend is not accessible. Note that the power
+ supply ``ground'' of the TRB is NOT the same as the ground of the
+ board itself (The TRB3 components are powered over galvanically
+ separated supplies on the board itself, again). Thus, you should
+ connect your probably galvanically separated ground of the PaDiWa
+ power supply with one of the four pins JGND headers of the TRB3.
+ Thus, also note that such problems caused by improper grounding of
+ the FEE can appear and disappear without any obvious reasons.
+
+\end{itemize*}
--- /dev/null
+Some table where all available hardware modifications or variations
+are listed, including revisions. Also list planned ones.
\cleardoublepage
\part{General Remarks}
- \section{Description}
- \section{Modifications: Available and Planned}
+\section{Description}
+\input{intro_desc}
+\section{Modifications: Available and Planned}
+\input{intro_mods}
+\section{Hints for Beginners}
+\input{intro_hints}
\cleardoublepage
-
-\part{Hardware}
- \section{Building Blocks}
- \section{Schematics / Documentation}
- \section{Troubleshooting}
+\part{Hardware}
+\section{Building Blocks}
+\input{hw_blocks}
+\section{Schematics / Documentation}
+\section{Troubleshooting}
\cleardoublepage
\part{Firmware}
- \section{Flash ROM}
- \section{Temperature Compensation}
-
+\section{Configuration over SPI}
+\input{fw_spiconfig}
+\section{Flash ROM}
+\input{fw_flashrom}
+\section{Temperature Compensation}
+\input{fw_temperature}
\cleardoublepage
\part{Measurements / Tests}
- \section{Temperature Compensation}
- \section{Padiwa: Timings}
- \section{Padiwa Amps: Charge and Timings}
-
+\section{Temperature Compensation}
+\input{meas_temperature}
+\section{Padiwa: Timings}
+\section{Padiwa Amps: Charge and Timings}
+\input{meas_amps_charge}
\cleardoublepage
--- /dev/null
+Will be written by A.Neiser...
\ No newline at end of file
--- /dev/null
+The uncompensated treshold voltage is affected by a thermal variation , around
+-150uV per 1°C. For a threshold of 1V and a temperature rise of 35°C (35°C to
+70°C) an offset of 5,5mV has been measured. The linear proportion of the
+thermal variation can be compensated which results in a voltage rise of only
+500uV for a temperature rise of 35°C.
+
+The compensation value of 0x02c0 was determined by measurement.
+
+To set the compensation value use the padiwa.pl script. For example
+``./padiwa.pl 0x303 0 comp 02C0''.
+
+\begin{figure}[htp]
+ \centering
+ \includegraphics[width=0.8\textwidth]{figures/padiwa_thresh_without_compensation.pdf}
+ \caption[]{Temperature dependence of the threshold without internal compensation.}
+ \label{fig:pad_without_calib}
+\end{figure}
+
+\begin{figure}[htp]
+ \centering
+ \includegraphics[width=0.8\textwidth]{figures/padiwa_thresh_with_compensation.pdf}
+ \caption[]{Temperature dependence of the threshold with internal compensation.}
+ \label{fig:pad_with_calib}
+\end{figure}
jspc29 / padiwadocu.git / commitdiff