end if;
when SCTRL =>
if sci_reg_i = '1' then
- --BUS_TX.data <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(4 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(4 downto 0)))));
- --BUS_TX.ack <= '1';
LOC_BUS_RX.read <= BUS_RX.read;
LOC_BUS_RX.write <= BUS_RX.write;
SCI_WR <= '0';
sci_state <= IDLE;
when GET_WA =>
- if cnt = 4 then
+ if cnt = 4 or BUS_RX.read = '1' or BUS_RX.write = '1' then
cnt := 0;
sci_state <= IDLE;
else
end if;
when GET_WA_WAIT =>
sci_state <= GET_WA_WAIT2;
+ if BUS_RX.read = '1' or BUS_RX.write = '1' then
+ sci_state <= IDLE;
+ end if;
when GET_WA_WAIT2 =>
sci_state <= GET_WA_FINISH;
+ if BUS_RX.read = '1' or BUS_RX.write = '1' then
+ sci_state <= IDLE;
+ end if;
when GET_WA_FINISH =>
wa_position(cnt*4+3 downto cnt*4) <= SCI_RDDATA(3 downto 0);
sci_state <= GET_WA;
cnt := cnt + 1;
+ if BUS_RX.read = '1' or BUS_RX.write = '1' then
+ sci_state <= IDLE;
+ end if;
end case;
--- if (BUS_RX.read = '1' or BUS_RX.write = '1') and sci_state /= IDLE and sci_reg_i = '0' then
--- BUS_TX.nack <= '1'; BUS_TX.ack <= '0';
--- end if;
+ if (BUS_RX.read = '1' or BUS_RX.write = '1') and sci_state /= IDLE and sci_reg_i = '0' then
+ BUS_TX.nack <= '1';
+ BUS_TX.ack <= '0';
+ end if;
end process;