on the way...

diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj
index f2d9f986f06899f11cc0d54e21683f0477d3c921..bba0af242630f536663ced0822477361944174a7 100644 (file)
--- a/cts/trb3sc_cts.prj
+++ b/cts/trb3sc_cts.prj
@@ -144,6 +144,8 @@ add_file -vhdl -lib work "../../trb3sc/cores/pll_in120_out624.vhd"
 add_file -vhdl -lib work "../../trbnet/special/ddmtd.vhd"
 add_file -vhdl -lib work "../../trbnet/special/deglitch.vhd"
 add_file -vhdl -lib work "../../trbnet/special/statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/special/clockbox.vhd"
+add_file -vhdl -lib work "../../trbnet/special/clockpoint.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/statmem.vhd"
 
 #TrbNet Endpoint

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 84e894d2e142df29f4d33674fa5634dea17c045f..61c4a7a1bc60ed1fe82d61e2577527c557291272 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -270,8 +270,10 @@ architecture trb3sc_arch of trb3sc_cts is
   
   signal phaser_data                 : std_logic_vector(31 downto 0);
   signal ping_i                      : std_logic;
+  signal ping_iq                     : std_logic;
   signal ping_q                      : std_logic;
   signal pong_i                      : std_logic;
+  signal pong_iq                     : std_logic;
   signal pong_q                      : std_logic;
   signal pong_clk_i                  : std_logic;
 
@@ -343,7 +345,7 @@ begin
                 clk_full_osc   when (LINK_SPEED = 200) else
                 '0';
   
--- Reset by GbE: a minimum delay of 1us is kept before the reset 
+-- Reset by GbE: a minimum delay of 1us is pong_qkept before the reset 
 -- pulse is injected into the reset handler.
   PROC_MAKE_RESET : process 
   begin
@@ -571,12 +573,23 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
     LOCK    => open
   );
 
+  THE_CLOCKBOX: entity clockbox
+  port map(
+    SAMPLE_CLK    => clk_sample,
+    PING_IN       => ping_i,
+    CLK_PING      => master_clk_i,
+    PONG_IN       => pong_i,
+    CLK_PONG      => pong_clk_i,
+    PING_OUT      => ping_iq,
+    PONG_OUT      => pong_iq
+  );
+    
   THE_DDMTD: entity ddmtd
   port map(
     AUXCLK           => clk_sample,
     RESET            => reset_i,
-    PING_IN          => ping_i,
-    PONG_IN          => pong_i,
+    PING_IN          => ping_iq,
+    PONG_IN          => pong_iq,
     PING_OUT         => ping_stretched_i,
     PONG_OUT         => pong_stretched_i,
     START_PING_OUT   => start_ping_i,