#implementation attributes
+set_option -vhdl2008 1
set_option -vlog_std v2001
set_option -project_relative_includes 1
impl -active "workdir"
add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd"
add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
+
#SlowControl files
add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0');
- LED_HUB_LINKOK : out std_logic_vector(8*USE_ADDON-1 downto 1);
- LED_HUB_RX : out std_logic_vector(8*USE_ADDON-1 downto 1);
- LED_HUB_TX : out std_logic_vector(8*USE_ADDON-1 downto 1);
- HUB_MOD0 : in std_logic_vector(8*USE_ADDON-1 downto 1);
- HUB_MOD1 : inout std_logic_vector(8*USE_ADDON-1 downto 1);
- HUB_MOD2 : inout std_logic_vector(8*USE_ADDON-1 downto 1);
- HUB_TXDIS : out std_logic_vector(8*USE_ADDON-1 downto 1);
- HUB_LOS : in std_logic_vector(8*USE_ADDON-1 downto 1);
+ LED_HUB_LINKOK : out std_logic_vector(8*USE_ADDON downto 1);
+ LED_HUB_RX : out std_logic_vector(8*USE_ADDON downto 1);
+ LED_HUB_TX : out std_logic_vector(8*USE_ADDON downto 1);
+ HUB_MOD0 : in std_logic_vector(8*USE_ADDON downto 1);
+ HUB_MOD1 : inout std_logic_vector(8*USE_ADDON downto 1);
+ HUB_MOD2 : inout std_logic_vector(8*USE_ADDON downto 1);
+ HUB_TXDIS : out std_logic_vector(8*USE_ADDON downto 1);
+ HUB_LOS : in std_logic_vector(8*USE_ADDON downto 1);
--Lines to slaves
BACK_MASTER_READY : out std_logic_vector(9*USE_BACKPLANE-1 downto 0);
RESET_IN => reset_i,
TIMER_CLOCK_IN => timer.tick_us,
- TIMER_RESET_IN => RJ_IO_IN(0),
+ TIMER_RESET_IN => RJ_IO_IN(1),
TRIGGER_IN => cts_trigger_out,
BUSRDO_RX => cts_rdo_rx,
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1710\@jspc29",
lattice_path => '/d/jspc29/lattice/diamond/3.12',
-synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2',
+synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2',
#synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/',
#synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
-REGION "MEDIA_DOWN1" "R102C20D" 13 120;
+REGION "MEDIA_DOWN1" "R102C20D" 14 150;
LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ;
LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
MAXDELAY TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-
+# PROHIBIT PRIMARY NET "gen_hub_no_gbe.THE_HUB/stat_busycntexcl_ack";
+# PROHIBIT SECONDARY NET "gen_hub_no_gbe.THE_HUB/stat_busycntexcl_ack";
+# PROHIBIT PRIMARY NET "gen_hub_no_gbe.THE_HUB/stat_busycntincl_ack";
+# PROHIBIT SECONDARY NET "gen_hub_no_gbe.THE_HUB/stat_busycntincl_ack";
# PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
set_option -symbolic_fsm_compiler 1
set_option -top_module "trb3sc_hub"
set_option -resource_sharing false
+set_option -vhdl2008 true
# map options
set_option -frequency 120
not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else
'1';
- TEST_LINE(0) <= med2int(INTERFACE_NUM-1).stat_op(13);
- TEST_LINE(1) <= med2int(INTERFACE_NUM-1).stat_op(15);
- TEST_LINE(2) <= clear_i;
- TEST_LINE(3) <= reset_i;
+ --TEST_LINE(0) <= med2int(INTERFACE_NUM-1).stat_op(13);
+ --TEST_LINE(1) <= med2int(INTERFACE_NUM-1).stat_op(15);
+ --TEST_LINE(2) <= clear_i;
+ --TEST_LINE(3) <= reset_i;
-- TEST_LINE(4) <= time_counter(26);
-- TEST_LINE(5) <= BACK_GPIO(1);
-- TEST_LINE(6) <= sfp_txdis_i;
- TEST_LINE(7) <= med2int(INTERFACE_NUM-1).stat_op(9);
+ --TEST_LINE(7) <= med2int(INTERFACE_NUM-1).stat_op(9);
end architecture;
# RJ-45 connectors\r
#################################################################\r
LOCATE COMP "RJ_IO_0" SITE "R28";\r
-LOCATE COMP "RJ_IO_1" SITE "R31";\r
+#LOCATE COMP "RJ_IO_1" SITE "R31";\r
LOCATE COMP "RJ_IO_2" SITE "R26";\r
LOCATE COMP "RJ_IO_3" SITE "R34";\r
#LOCATE COMP "RJ_IO_1_N" SITE "R27";\r
#LOCATE COMP "RJ_IO_3_N" SITE "R25";\r
#LOCATE COMP "RJ_IO_4_N" SITE "R33";\r
IOBUF PORT "RJ_IO_0" IO_TYPE=LVDS25 ;\r
-IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ;\r
+#IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ;\r
IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25E ;\r
IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ;\r
\r