git-svn-id: file:///d/jspc55.1/Elektronik/repo@10 44570794-fe78-5344-a7c8-9252e64eda2e

diff --git a/CB2013/CB13_FebOutput.SchDoc b/CB2013/CB13_FebOutput.SchDoc
index 13b81c9ff0354f35bb5baaef309937f45f2890fd..487ce092a0d3dc0b185cfeea30852d02b47e1d02 100644 (file)
Binary files a/CB2013/CB13_FebOutput.SchDoc and b/CB2013/CB13_FebOutput.SchDoc differ

diff --git a/CB2013/CB2013.PcbDoc b/CB2013/CB2013.PcbDoc
index da1b8cea57f46a4c09ecf06dd975eece15d8fdfa..d8b1c5c2ec3283a6743f3b76f4ccf4f92a03e0a9 100644 (file)
Binary files a/CB2013/CB2013.PcbDoc and b/CB2013/CB2013.PcbDoc differ

diff --git a/CB2013/CB2013.PrjPCB b/CB2013/CB2013.PrjPCB
index 3c02d470cb3bcbb8990ad9480b751e3602cba8a7..89329506ee186cff4005537f572f0f041fd0059e 100644 (file)
--- a/CB2013/CB2013.PrjPCB
+++ b/CB2013/CB2013.PrjPCB
@@ -29,7 +29,7 @@ PowerPortNamesTakePriority=0
 PushECOToAnnotationFile=1\r
 DItemRevisionGUID=\r
 ReportSuppressedErrorsInMessages=0\r
-OutputPath=Project Outputs for CB2013\r
+OutputPath=\r
 \r
 [Document1]\r
 DocumentPath=CB13_ADC.SchDoc\r
@@ -452,7 +452,7 @@ SCH_HasExpandLogicalToPhysicalSheets=-1
 SaveSettingsToOutJob=-1\r
 \r
 [Generic_EDE]\r
-OutputDir=Project Outputs for CB2013\r
+OutputDir=\r
 \r
 [OutputGroup1]\r
 Name=Netlist Outputs\r
@@ -1460,8 +1460,8 @@ IndexStartValue15=1
 Suffix15=\r
 \r
 [PrjClassGen]\r
-CompClassManualEnabled=0\r
-CompClassManualRoomEnabled=0\r
+CompClassManualEnabled=1\r
+CompClassManualRoomEnabled=1\r
 NetClassAutoBusEnabled=1\r
 NetClassAutoCompEnabled=0\r
 NetClassAutoNamedHarnessEnabled=0\r

diff --git a/CB2013/ConverterBoard2013.SchDoc b/CB2013/ConverterBoard2013.SchDoc
index feb1689995fdf804f05ceb1d8340c6a24da1504a..4e2f81ef06f29d08c7685d6d2281c98c6e7c7d44 100644 (file)
Binary files a/CB2013/ConverterBoard2013.SchDoc and b/CB2013/ConverterBoard2013.SchDoc differ