latest Padiwa TDC test files

diff --git a/wasa/cores/pll_shifted_clocks.ipx b/wasa/cores/pll_shifted_clocks.ipx
index e872f6ac05b84b85094fcb3f288a00143fa6530f..55f87978942327ac0bc3aa1ec036c097eb64879e 100644 (file)
--- a/wasa/cores/pll_shifted_clocks.ipx
+++ b/wasa/cores/pll_shifted_clocks.ipx
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_shifted_clocks" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 01 14:46:58.314" version="5.3" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="pll_shifted_clocks" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 01 20:16:48.328" version="5.4" type="Module" synthesis="" source_format="VHDL">
   <Package>
-               <File name="pll_shifted_clocks.lpc" type="lpc" modified="2013 10 01 14:46:55.000"/>
-               <File name="pll_shifted_clocks.vhd" type="top_level_vhdl" modified="2013 10 01 14:46:56.000"/>
-               <File name="pll_shifted_clocks_tmpl.vhd" type="template_vhdl" modified="2013 10 01 14:46:56.000"/>
+               <File name="pll_shifted_clocks.lpc" type="lpc" modified="2013 10 01 20:07:31.000"/>
+               <File name="pll_shifted_clocks.vhd" type="top_level_vhdl" modified="2013 10 01 20:07:32.000"/>
+               <File name="pll_shifted_clocks_tmpl.vhd" type="template_vhdl" modified="2013 10 01 20:07:32.000"/>
   </Package>
 </DiamondModule>

diff --git a/wasa/cores/pll_shifted_clocks.lpc b/wasa/cores/pll_shifted_clocks.lpc
index 4ad6b731b2809538e7cccb3f59c0e8f7ce7d5a11..31668f38d3308f7f25301b1e420346926def697a 100644 (file)
--- a/wasa/cores/pll_shifted_clocks.lpc
+++ b/wasa/cores/pll_shifted_clocks.lpc
@@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation
 CoreType=LPM
 CoreStatus=Demo
 CoreName=PLL
-CoreRevision=5.3
+CoreRevision=5.4
 ModuleName=pll_shifted_clocks
 SourceFormat=VHDL
 ParameterFileVersion=1.0
 Date=10/01/2013
-Time=14:46:55
+Time=20:07:31
 
 [Parameters]
 Verilog=0
@@ -30,7 +30,9 @@ IO=0
 mode=Frequency
 CLKI=133
 CLKI_DIV=1
-fb_mode=INT_OP
+BW=532.000
+VCO=10.504
+fb_mode=INT_OS3
 CLKFB_DIV=2
 FRACN_ENABLE=0
 FRACN_DIV=0
@@ -50,7 +52,7 @@ CLKOP_DIV=2
 FREQ_PIN_CLKOP=266
 OP_Tol=10.0
 CLKOP_AFREQ=266.000000
-CLKOP_PHASEADJ=0
+CLKOP_PHASEADJ=225
 CLKOP_TRIM_POL=Rising
 CLKOP_TRIM_DELAY=0
 EnCLKOS=1
@@ -60,7 +62,7 @@ CLKOS_DIV=2
 FREQ_PIN_CLKOS=266
 OS_Tol=10.0
 CLKOS_AFREQ=266.000000
-CLKOS_PHASEADJ=45
+CLKOS_PHASEADJ=270
 CLKOS_TRIM_POL=Rising
 CLKOS_TRIM_DELAY=0
 EnCLKOS2=1
@@ -70,7 +72,7 @@ CLKOS2_DIV=2
 FREQ_PIN_CLKOS2=266
 OS2_Tol=10.0
 CLKOS2_AFREQ=266.000000
-CLKOS2_PHASEADJ=90
+CLKOS2_PHASEADJ=315
 EnCLKOS3=1
 OS3Bypass=0
 OS3UseDiv=0
@@ -78,4 +80,4 @@ CLKOS3_DIV=2
 FREQ_PIN_CLKOS3=266
 OS3_Tol=10.0
 CLKOS3_AFREQ=266.000000
-CLKOS3_PHASEADJ=135
+CLKOS3_PHASEADJ=0

diff --git a/wasa/cores/pll_shifted_clocks.vhd b/wasa/cores/pll_shifted_clocks.vhd
index 043f2b93dc3ce1683cd7736b06d8641f0529f001..ef170b92c914e1e2bc7e52092b1a9ed8ce29e317 100644 (file)
--- a/wasa/cores/pll_shifted_clocks.vhd
+++ b/wasa/cores/pll_shifted_clocks.vhd
@@ -1,8 +1,8 @@
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module  Version: 5.3
---/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n pll_shifted_clocks -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 133 -fclkop 266 -fclkop_tol 10.0 -fclkos 266 -fclkos_tol 10.0 -fclkos2 266 -fclkos2_tol 10.0 -fclkos3 266 -fclkos3_tol 10.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5 -e 
+-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
+-- Module  Version: 5.4
+--/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n pll_shifted_clocks -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 133 -fclkop 266 -fclkop_tol 10.0 -fclkos 266 -fclkos_tol 10.0 -fclkos2 266 -fclkos2_tol 10.0 -fclkos3 266 -fclkos3_tol 10.0 -trimp 0 -phasep 225 -trimp_r -trims 0 -phases 270 -trims_r -phases2 315 -phases3 0 -phase_cntl STATIC -fb_mode 8 -e 
 
--- Tue Oct  1 14:46:56 2013
+-- Tue Oct  1 20:07:32 2013
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -41,7 +41,7 @@ architecture Structure of pll_shifted_clocks is
         generic (INTFB_WAKE : in String; DDRST_ENA : in String; 
                 DCRST_ENA : in String; MRST_ENA : in String; 
                 PLLRST_ENA : in String; DPHASE_SOURCE : in String; 
-                OUTDIVIDER_MUXD2 : in String; 
+                STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String; 
                 OUTDIVIDER_MUXC2 : in String; 
                 OUTDIVIDER_MUXB2 : in String; 
                 OUTDIVIDER_MUXA2 : in String; 
@@ -93,7 +93,6 @@ architecture Structure of pll_shifted_clocks is
             PLLDATO3: out  std_logic; PLLDATO2: out  std_logic; 
             PLLDATO1: out  std_logic; PLLDATO0: out  std_logic);
     end component;
-    attribute STDBY_ENABLE : string; 
     attribute FREQUENCY_PIN_CLKOS3 : string; 
     attribute FREQUENCY_PIN_CLKOS2 : string; 
     attribute FREQUENCY_PIN_CLKOS : string; 
@@ -101,7 +100,6 @@ architecture Structure of pll_shifted_clocks is
     attribute FREQUENCY_PIN_CLKI : string; 
     attribute ICP_CURRENT : string; 
     attribute LPF_RESISTOR : string; 
-    attribute STDBY_ENABLE of PLLInst_0 : label is "DISABLED";
     attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "266.000000";
     attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "266.000000";
     attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "266.000000";
@@ -112,6 +110,8 @@ architecture Structure of pll_shifted_clocks is
     attribute syn_keep : boolean;
     attribute syn_noprune : boolean;
     attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
 
 begin
     -- component instantiation statements
@@ -121,11 +121,11 @@ begin
     PLLInst_0: EHXPLLJ
         generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED", 
         MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 
-        DPHASE_SOURCE=> "DISABLED", PLL_USE_WB=> "DISABLED", 
-        CLKOS3_FPHASE=>  6, CLKOS3_CPHASE=>  1, CLKOS2_FPHASE=>  4, 
-        CLKOS2_CPHASE=>  1, CLKOS_FPHASE=>  2, CLKOS_CPHASE=>  1, 
-        CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  1, PLL_LOCK_MODE=>  0, 
-        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 
+        PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  1, 
+        CLKOS2_FPHASE=>  6, CLKOS2_CPHASE=>  2, CLKOS_FPHASE=>  4, 
+        CLKOS_CPHASE=>  2, CLKOP_FPHASE=>  2, CLKOP_CPHASE=>  2, 
+        PLL_LOCK_MODE=>  0, CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
         CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=>  0, 
         FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD", 
         PREDIVIDER_MUXD1=>  0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "ENABLED", 
@@ -135,7 +135,7 @@ begin
         OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=>  0, VCO_BYPASS_A0=> "DISABLED", 
         CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  2, CLKOS2_DIV=>  2, 
         CLKOS_DIV=>  2, CLKOP_DIV=>  2, CLKFB_DIV=>  2, CLKI_DIV=>  1, 
-        FEEDBK_PATH=> "INT_DIVA")
+        FEEDBK_PATH=> "INT_DIVD")
         port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, 
             PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 
             PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo, 

diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd
index 2232804b69dde3770fdac1e3eaf5b45a0f773bb4..344840a3987b19be88ed6650def65b1bbc42edb5 100644 (file)
--- a/wasa/panda_dirc_wasa.vhd
+++ b/wasa/panda_dirc_wasa.vhd
@@ -485,7 +485,7 @@ end process;
 gen_ffarr : if TDCTEST = 1 generate
  THE_FFARR : entity work.ffarray
    port map(
-    CLK        => clk_i,
+    CLK        => clk_osc,
     SIGNAL_IN  => SPI_IN,
     
     DATA_OUT   => ffarr_data(7 downto 0),

diff --git a/wasa/panda_dirc_wasa_constraints.lpf b/wasa/panda_dirc_wasa_constraints.lpf
index cb83993a3461ee9e35e0ee9ee47fef36f137ed6e..f80557142997eb47fa62e20da8592a7b349b5004 100644 (file)
--- a/wasa/panda_dirc_wasa_constraints.lpf
+++ b/wasa/panda_dirc_wasa_constraints.lpf
@@ -5,40 +5,42 @@ FREQUENCY NET clk_i_c  133 MHz;
 UGROUP "ffarr0group" 
   BLKNAME gen_ffarr_THE_FFARR/ffarr_0_0
   BLKNAME gen_ffarr_THE_FFARR/ffarr_1_0
-  BLKNAME gen_ffarr_THE_FFARR/ffarr_1_1
-  BLKNAME gen_ffarr_THE_FFARR/ffarr_1_2
   BLKNAME gen_ffarr_THE_FFARR/ffarr_2_0
-  BLKNAME gen_ffarr_THE_FFARR/ffarr_2_1
-  BLKNAME gen_ffarr_THE_FFARR/ffarr_2_2
-  BLKNAME gen_ffarr_THE_FFARR/ffarr_3_0
-  BLKNAME gen_ffarr_THE_FFARR/ffarr_3_1
-  BLKNAME gen_ffarr_THE_FFARR/ffarr_3_2
   BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_0_1
   BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_0_2
   BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_0_3
   BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_0_4
   BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_0_5
   BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_0_6
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_0_7
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_3_ffarr_1_3
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_4_ffarr_1_4
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_5_ffarr_1_5
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_6_ffarr_1_6
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_7_ffarr_1_7
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_3_ffarr_2_3
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_4_ffarr_2_4
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_5_ffarr_2_5
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_6_ffarr_2_6
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_7_ffarr_2_7
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_3_ffarr_3_3
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_4_ffarr_3_4
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_5_ffarr_3_5
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_6_ffarr_3_6
-  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_7_ffarr_3_7;  
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_0_7;
   
-REGION "FFARR0" "R19C26" 2 4 DEVSIZE;
-LOCATE UGROUP "ffarr0group" REGION "FFARR0";
-
+UGROUP "ffarr12group" 
+  BLKNAME gen_ffarr_THE_FFARR/ffarr_1_0
+  BLKNAME gen_ffarr_THE_FFARR/ffarr_2_0
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_1_1
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_2_1
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_1_2
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_2_2
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_1_3
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_2_3
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_1_4
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_2_4
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_1_5
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_2_5
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_1_6
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_2_6
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_1_7
+  BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_2_7;  
+  
+  
+REGION "FFARR0"  "R19C26" 1 2 DEVSIZE;
+REGION "FFARR12" "R19C27" 2 2 DEVSIZE;
+LOCATE UGROUP "ffarr0group"  REGION "FFARR0";
+LOCATE UGROUP "ffarr12group" REGION "FFARR12";
 
-USE SECONDARY NET "gen_ffarr_THE_FFARR/CLKa*";
-USE SECONDARY NET "gen_ffarr_THE_FFARR_CLKa*";
\ No newline at end of file
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa*";
+USE PRIMARY NET "gen_ffarr_THE_FFARR_CLKa*";
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_0";
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_1";
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_2";
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_3";

diff --git a/wasa/source/ffarray.vhd b/wasa/source/ffarray.vhd
index e9fd9526a9146dba7f6ff1390e1851916ce44305..e87ef086bd702cda0018148e650b7c94d0777597 100644 (file)
--- a/wasa/source/ffarray.vhd
+++ b/wasa/source/ffarray.vhd
@@ -59,18 +59,21 @@ CLKa(7 downto 4) <= not CLKt(3 downto 0);
 
 gen_ffarr_first : for i in 0 to 7 generate
   ffarr(0)(i) <= SIGNAL_IN when rising_edge(CLKa(i));
+  ffarr(1)(i) <= ffarr(0)(i) when rising_edge(CLKa((i/4)*4));
+  ffarr(2)(i) <= ffarr(1)(i) when rising_edge(CLKa(0));
 end generate;
 
-gen_ffarr_j : for j in 1 to 3 generate
-  gen_ffarr_i : for i in 0 to 7 generate
-    ffarr(j)(i) <= ffarr(j-1)(i) when rising_edge(CLKa(maximum(i-j*2,0)));
-  end generate;
-end generate;
+
+-- gen_ffarr_j : for j in 1 to 3 generate
+--   gen_ffarr_i : for i in 0 to 7 generate
+--     ffarr(j)(i) <= ffarr(j-1)(i) when rising_edge(CLKa(maximum(i-j*2-1,0)));
+--   end generate;
+-- end generate;
 
 
 process begin
   wait until rising_edge(CLK);
-  final_t <= ffarr(3);
+  final_t <= ffarr(2);
   if ((not and_all(final_t) and or_all(final_t)) = '1') then
     fifo_write <= '1';
     final <= final_t;