<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_shifted_clocks" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 01 14:46:58.314" version="5.3" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="pll_shifted_clocks" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 01 20:16:48.328" version="5.4" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="pll_shifted_clocks.lpc" type="lpc" modified="2013 10 01 14:46:55.000"/>
- <File name="pll_shifted_clocks.vhd" type="top_level_vhdl" modified="2013 10 01 14:46:56.000"/>
- <File name="pll_shifted_clocks_tmpl.vhd" type="template_vhdl" modified="2013 10 01 14:46:56.000"/>
+ <File name="pll_shifted_clocks.lpc" type="lpc" modified="2013 10 01 20:07:31.000"/>
+ <File name="pll_shifted_clocks.vhd" type="top_level_vhdl" modified="2013 10 01 20:07:32.000"/>
+ <File name="pll_shifted_clocks_tmpl.vhd" type="template_vhdl" modified="2013 10 01 20:07:32.000"/>
</Package>
</DiamondModule>
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
-CoreRevision=5.3
+CoreRevision=5.4
ModuleName=pll_shifted_clocks
SourceFormat=VHDL
ParameterFileVersion=1.0
Date=10/01/2013
-Time=14:46:55
+Time=20:07:31
[Parameters]
Verilog=0
mode=Frequency
CLKI=133
CLKI_DIV=1
-fb_mode=INT_OP
+BW=532.000
+VCO=10.504
+fb_mode=INT_OS3
CLKFB_DIV=2
FRACN_ENABLE=0
FRACN_DIV=0
FREQ_PIN_CLKOP=266
OP_Tol=10.0
CLKOP_AFREQ=266.000000
-CLKOP_PHASEADJ=0
+CLKOP_PHASEADJ=225
CLKOP_TRIM_POL=Rising
CLKOP_TRIM_DELAY=0
EnCLKOS=1
FREQ_PIN_CLKOS=266
OS_Tol=10.0
CLKOS_AFREQ=266.000000
-CLKOS_PHASEADJ=45
+CLKOS_PHASEADJ=270
CLKOS_TRIM_POL=Rising
CLKOS_TRIM_DELAY=0
EnCLKOS2=1
FREQ_PIN_CLKOS2=266
OS2_Tol=10.0
CLKOS2_AFREQ=266.000000
-CLKOS2_PHASEADJ=90
+CLKOS2_PHASEADJ=315
EnCLKOS3=1
OS3Bypass=0
OS3UseDiv=0
FREQ_PIN_CLKOS3=266
OS3_Tol=10.0
CLKOS3_AFREQ=266.000000
-CLKOS3_PHASEADJ=135
+CLKOS3_PHASEADJ=0
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module Version: 5.3
---/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n pll_shifted_clocks -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 133 -fclkop 266 -fclkop_tol 10.0 -fclkos 266 -fclkos_tol 10.0 -fclkos2 266 -fclkos2_tol 10.0 -fclkos3 266 -fclkos3_tol 10.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5 -e
+-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
+-- Module Version: 5.4
+--/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n pll_shifted_clocks -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 133 -fclkop 266 -fclkop_tol 10.0 -fclkos 266 -fclkos_tol 10.0 -fclkos2 266 -fclkos2_tol 10.0 -fclkos3 266 -fclkos3_tol 10.0 -trimp 0 -phasep 225 -trimp_r -trims 0 -phases 270 -trims_r -phases2 315 -phases3 0 -phase_cntl STATIC -fb_mode 8 -e
--- Tue Oct 1 14:46:56 2013
+-- Tue Oct 1 20:07:32 2013
library IEEE;
use IEEE.std_logic_1164.all;
generic (INTFB_WAKE : in String; DDRST_ENA : in String;
DCRST_ENA : in String; MRST_ENA : in String;
PLLRST_ENA : in String; DPHASE_SOURCE : in String;
- OUTDIVIDER_MUXD2 : in String;
+ STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
OUTDIVIDER_MUXC2 : in String;
OUTDIVIDER_MUXB2 : in String;
OUTDIVIDER_MUXA2 : in String;
PLLDATO3: out std_logic; PLLDATO2: out std_logic;
PLLDATO1: out std_logic; PLLDATO0: out std_logic);
end component;
- attribute STDBY_ENABLE : string;
attribute FREQUENCY_PIN_CLKOS3 : string;
attribute FREQUENCY_PIN_CLKOS2 : string;
attribute FREQUENCY_PIN_CLKOS : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
- attribute STDBY_ENABLE of PLLInst_0 : label is "DISABLED";
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "266.000000";
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "266.000000";
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "266.000000";
attribute syn_keep : boolean;
attribute syn_noprune : boolean;
attribute syn_noprune of Structure : architecture is true;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
PLLInst_0: EHXPLLJ
generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
- DPHASE_SOURCE=> "DISABLED", PLL_USE_WB=> "DISABLED",
- CLKOS3_FPHASE=> 6, CLKOS3_CPHASE=> 1, CLKOS2_FPHASE=> 4,
- CLKOS2_CPHASE=> 1, CLKOS_FPHASE=> 2, CLKOS_CPHASE=> 1,
- CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 1, PLL_LOCK_MODE=> 0,
- CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
+ PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 1,
+ CLKOS2_FPHASE=> 6, CLKOS2_CPHASE=> 2, CLKOS_FPHASE=> 4,
+ CLKOS_CPHASE=> 2, CLKOP_FPHASE=> 2, CLKOP_CPHASE=> 2,
+ PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0,
FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "ENABLED",
OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 2, CLKOS2_DIV=> 2,
CLKOS_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1,
- FEEDBK_PATH=> "INT_DIVA")
+ FEEDBK_PATH=> "INT_DIVD")
port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
gen_ffarr : if TDCTEST = 1 generate
THE_FFARR : entity work.ffarray
port map(
- CLK => clk_i,
+ CLK => clk_osc,
SIGNAL_IN => SPI_IN,
DATA_OUT => ffarr_data(7 downto 0),
UGROUP "ffarr0group"
BLKNAME gen_ffarr_THE_FFARR/ffarr_0_0
BLKNAME gen_ffarr_THE_FFARR/ffarr_1_0
- BLKNAME gen_ffarr_THE_FFARR/ffarr_1_1
- BLKNAME gen_ffarr_THE_FFARR/ffarr_1_2
BLKNAME gen_ffarr_THE_FFARR/ffarr_2_0
- BLKNAME gen_ffarr_THE_FFARR/ffarr_2_1
- BLKNAME gen_ffarr_THE_FFARR/ffarr_2_2
- BLKNAME gen_ffarr_THE_FFARR/ffarr_3_0
- BLKNAME gen_ffarr_THE_FFARR/ffarr_3_1
- BLKNAME gen_ffarr_THE_FFARR/ffarr_3_2
BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_0_1
BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_0_2
BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_0_3
BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_0_4
BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_0_5
BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_0_6
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_0_7
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_3_ffarr_1_3
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_4_ffarr_1_4
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_5_ffarr_1_5
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_6_ffarr_1_6
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_7_ffarr_1_7
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_3_ffarr_2_3
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_4_ffarr_2_4
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_5_ffarr_2_5
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_6_ffarr_2_6
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_7_ffarr_2_7
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_3_ffarr_3_3
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_4_ffarr_3_4
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_5_ffarr_3_5
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_6_ffarr_3_6
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_7_ffarr_3_7;
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_0_7;
-REGION "FFARR0" "R19C26" 2 4 DEVSIZE;
-LOCATE UGROUP "ffarr0group" REGION "FFARR0";
-
+UGROUP "ffarr12group"
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_1_0
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_2_0
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_1_1
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_2_1
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_1_2
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_2_2
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_1_3
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_2_3
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_1_4
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_2_4
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_1_5
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_2_5
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_1_6
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_2_6
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_1_7
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_2_7;
+
+
+REGION "FFARR0" "R19C26" 1 2 DEVSIZE;
+REGION "FFARR12" "R19C27" 2 2 DEVSIZE;
+LOCATE UGROUP "ffarr0group" REGION "FFARR0";
+LOCATE UGROUP "ffarr12group" REGION "FFARR12";
-USE SECONDARY NET "gen_ffarr_THE_FFARR/CLKa*";
-USE SECONDARY NET "gen_ffarr_THE_FFARR_CLKa*";
\ No newline at end of file
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa*";
+USE PRIMARY NET "gen_ffarr_THE_FFARR_CLKa*";
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_0";
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_1";
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_2";
+USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_3";
gen_ffarr_first : for i in 0 to 7 generate
ffarr(0)(i) <= SIGNAL_IN when rising_edge(CLKa(i));
+ ffarr(1)(i) <= ffarr(0)(i) when rising_edge(CLKa((i/4)*4));
+ ffarr(2)(i) <= ffarr(1)(i) when rising_edge(CLKa(0));
end generate;
-gen_ffarr_j : for j in 1 to 3 generate
- gen_ffarr_i : for i in 0 to 7 generate
- ffarr(j)(i) <= ffarr(j-1)(i) when rising_edge(CLKa(maximum(i-j*2,0)));
- end generate;
-end generate;
+
+-- gen_ffarr_j : for j in 1 to 3 generate
+-- gen_ffarr_i : for i in 0 to 7 generate
+-- ffarr(j)(i) <= ffarr(j-1)(i) when rising_edge(CLKa(maximum(i-j*2-1,0)));
+-- end generate;
+-- end generate;
process begin
wait until rising_edge(CLK);
- final_t <= ffarr(3);
+ final_t <= ffarr(2);
if ((not and_all(final_t) and or_all(final_t)) = '1') then
fifo_write <= '1';
final <= final_t;