Add list of input signals to trigger logic in most common designs

diff --git a/trb3/CodeRepository.tex b/trb3/CodeRepository.tex
index 464e056446a7171c3553c137d0f96a3ad2c7a9b1..e9b8eddf5cd4d1dc81f47c66efa12f2448dc3cc9 100644 (file)
--- a/trb3/CodeRepository.tex
+++ b/trb3/CodeRepository.tex
@@ -69,7 +69,7 @@ tutorial here (this can be googled duckduckgo'ed).
   \verb!git stash pop! afterwards.
 \end{itemize*}
 
-\subsection{FPGA designs}
+\section{FPGA designs}
 \begin{itemize*}
  \item All information is collected on \url{http://trb.gsi.de}, some direct links are:
  \item A list of current FPGA design files can be obtained from \\\url{http://jspc29.x-matter.uni-frankfurt.de/trbweb/?action=page&url=design-files}
@@ -78,7 +78,7 @@ tutorial here (this can be googled duckduckgo'ed).
 \end{itemize*}
 
 
-\subsection{Coding Style}
+\section{Coding Style}
 There is no mandatory coding style, but most code follows these simple rules to make it easier to read by others:
 \begin{itemize*}
 \item Indentation is done using two spaces per level. If tabs are used, make sure the width is set to two.

diff --git a/trb3/Trb5sc.tex b/trb3/Trb5sc.tex
index 25a4f548521c71280c9850c7b3fb4ebc4fbd3587..de4e167f872c16eb9ee0298f8d3ed5ae487db6d8 100644 (file)
--- a/trb3/Trb5sc.tex
+++ b/trb3/Trb5sc.tex
@@ -24,5 +24,5 @@ The Trb5sc is functionally compatible to Trb3sc, with a few exceptions. The FPGA
   \end{itemize} 
  \item AddOn boards may have up to two SFPs for any purpose. E.g. there is support for GbE, to increase the read-out bandwidth.
  \item A tiny switch near the backside allows to select the source of the trigger signal and the external clock: If "on" signals from the RJ-45 connector are used, if "off" signals from the backplane are routed to the FPGA. The status is shown on a blue LED.
- 
+ \item If the board is locked to an external clock, the green LED behind the RJ-45 close to the switch lights up, otherwise the red one is lit.
 \end{itemize}

diff --git a/trb3/TriggerModule.tex b/trb3/TriggerModule.tex
index f6eabb6b6f493bcf85a24d2265977e155965b099..cb01bc59741840ed8b0038757756e099601bb285 100644 (file)
--- a/trb3/TriggerModule.tex
+++ b/trb3/TriggerModule.tex
@@ -44,3 +44,70 @@ logic and store their data synchronously. Filling of the Fifos has to be trigger
 To save resources, it is also possible to use only one monitoring Fifo combined 
 with a multiplexer to select one of the inputs as source.  (resources: 1300 slices in FPGA for 32 inputs)
 
+\subsubsection{Inputs}
+The number, order and selection of inputs varies depending on the hardware and design used in the FPGAs. This list shows the most common design options:
+
+\begin{itemize}
+\item Trb3sc CTS: Backplane master
+\begin{itemize}
+ \item 1..0: Spare\_in
+ \item 17..2: KEL 1
+ \item 33..18: KEL 2
+ \item 35..34: Trigger logic outputs
+ \item (37..36) - (53..52): Backplane signals from all 9 slots
+\end{itemize}
+
+\item Trb3sc CTS: RJ adapter
+\begin{itemize}
+ \item 1..0: Spare\_in
+ \item (3..2) - (17..16): Inputs from 8 RJ I/O
+ \item 21..18: Input from extra RJ connector
+ \item 23..22: Trigger logic outputs
+\end{itemize}
+
+\item Trb3sc CTS: KEL input
+\begin{itemize}
+ \item 1..0: Spare\_in
+ \item 17..2: KEL 1
+ \item 33..18: KEL 2
+ \item 35..34: Trigger logic outputs
+\end{itemize}
+
+\item Trb3sc Backplane master
+\begin{itemize}
+ \item (1..0) - (17..16): Backplane signals from all 9 slots
+ \item 21..18: Trigger logic outputs
+ \item 37..22: KEL 1
+ \item 53..38: KEL 2
+\end{itemize}
+
+\item Trb3sc Backplane half master
+\begin{itemize}
+ \item (1..0) - (7..6): Backplane signals from first 4 slots
+ \item 11..8: Trigger logic outputs
+ \item 27..12: KEL 1
+ \item 43..28: KEL 2
+\end{itemize}
+
+\item Trb3sc TDC
+\begin{itemize}
+ \item (N..0): Same as TDC channels N+1..1
+ \item (N+4..N+1): Trigger logic outputs
+\end{itemize}
+
+\item Trb5sc TDC
+\begin{itemize}
+ \item (N..0): Same as TDC channels N+1..1
+\end{itemize}
+
+\item Trb3 TDC
+\begin{itemize}
+\item (N..0): Same as TDC channels N+1..1
+\end{itemize}
+\item Trb3 central hub
+\begin{itemize}
+ \item (3..0)-(15..12):4 inputs from each peripheral FPGA
+ \item 19..16: Trigger logic outputs
+\end{itemize}
+
+\end{itemize}